Processor Architectures

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1 ECPE 170 Jeff Shafer University of the Pacific Processor Architectures

2 2 Schedule Exam 3 Tuesday, December 6 th Caches Virtual Memory Input / Output OperaKng Systems Compilers & Assemblers Processor Architecture Review the lecture notes before the exam (not just the homework!)

3 3 Homework #15 Review HW #15 Amdahl s Law Disk capacity / access Kme Hard drive prefixes are powers of 10, not 2 SSD boyleneck changing a byte! SSD opkmizakon - TRIM

4 4 Homework #16 Review HW #16 Real- Kme OS (RTOS) Assembly vs High- Level Language Mobile OS

5 5 Database Software

6 6 Database Software Database systems contain the most valuable assets of an enterprise Build applicakons on top of databases

7 7 Database Software Most databases support transac'ons to assure that the database is always in a consistent state TransacKon is a group of related updates bundled together TransacKons provides the following properkes: Atomicity - All related updates occur or no updates occur Consistency - All updates conform to defined data constraints (i.e. data types, min/max legal values, etc ) IsolaKon - No transackon can interfere with another transackon Durability - Successful updates are wriyen to durable media as soon as possible (i.e. RAM isn t safe if the system crashes or the power fails) These are the ACID properkes of transackon management

8 8 Database Software Without the ACID properkes, race condikons can occur

9 9 Database Software Record locking mechanisms assure isolated, atomic database updates:

10 10 Processor Architectures

11 11 Processor Architectures StarKng Chapter 9 More details on RISC versus CISC! Leaving the safe, familiar world of the von Neumann processor What is the von Neumann model? Stored program computer Three systems: CPU, memory, I/O SequenKal instruckon processing Single data path between CPU and memory von Neumann boyleneck More than one processor! MulKprocessor architectures different types

12 12 RISC vs CISC Machines RISC systems access memory only with explicit load and store instruckons InstrucKon length is fixed Fetch- decode- execute Kme is constant CISC systems access memory with many different types of instruckons InstrucKon length is variable Fetch- decode- execute Kme is unpredictable

13 13 RISC vs CISC Machines Basic computer performance equakon: RISC systems shorten execukon Kme by reducing the clock cycles per instruckon CISC systems improve performance by reducing the number of instruckons per program

14 14 RISC vs CISC Machines RISC processors have a simpler instruckon set Build a hardwired control unit (faster!) Easier to implement pipelining and speculakve execukon CISC processors have a complex/variable instruckon set Build a microcode- based control unit to interpret instruckons Microcode processing takes Kme

15 15 RISC vs CISC Machines Because of their load- store ISAs, RISC architectures require a large number of CPU registers Register allow fast access to data during sequenkal program execukon no need to go to memory! Registers can also be used to reduce the overhead of calling subrouknes Contrast this to MARIE, where you had to store all your arguments in memory before jumping to a subroukne Instead of pulling parameters off of a stack, the subroukne is directed to use a subset of registers

16 16 Overlapping Registers Windows Divide all the registers into windows Your subroukne only sees one window The current window pointer (CWP) points to the ackve register window Shij when calling a subroukne Outputs become inputs Global registers shared by all

17 17 RISC vs CISC Machines It is becoming increasingly difficult to disknguish RISC architectures from CISC architectures. Some RISC systems provide more extravagant instruckon sets than some CISC systems Some systems combine both approaches Typical differences between the architectures

18 18 RISC vs CISC Machines RISC CISC MulKple register sets Single register set Three operands per instruckon One or two register operands per instruckon Parameter passing through register windows Parameter passing through memory Single- cycle instruckons MulKple cycle instruckons Hardwired control Microprogrammed control Highly pipelined Less pipelined 18

19 19 RISC vs CISC Machines RISC CISC Simple instruckons, few in number Many complex instruckons Variable length instruckons Fixed length instruckons Complexity in microcode Complexity in compiler Only LOAD/STORE instruckons access memory Many instruckons can access memory Many addressing modes Few addressing modes 19

20 20 Intel So, are Intel x86-32 or x86-64 chips RISC or CISC? Both! InstrucKon set is CISC- like Many complex instruckons Variable length instruckons Many instruckons can access memory (not just load/store) MulKple cycle instruckons etc

21 21 Intel But, what happens internally is completely different Dedicated hardware unit that decodes the CISC- like x86 instruckons and replaces them with a sequence of RISC- like micro- ops Intel has been RISC- like internally since the PenKum Pro era (~1996)

22 22 Intel versus ARM Intel ARM CISC- like ISA RISC- like ISA Dominant market: Desktop PCs Laptop PCs Server PCs Performance crikcal? Dominant market: Mobile devices (cell phones, music players, etc ) Power crikcal? Embedded devices Why does Intel dominate these markets? Why does ARM dominate these markets?

23 23 Intel versus ARM Intel Manufacturing: Every chip made by Intel Performance Huge amount of legacy sojware for desktops/ servers wriyen for the x86 ISA ARM Manufacturing: None ARM licenses its design to other companies to integrate/build Apple, NVIDIA, IBM, Texas Instruments, Nintendo, Samsung, Freescale, Qualcomm and VIA Technologies, and Intel! Performance per wax Huge amount of legacy sojware for cell phones wriyen for ARM ISA

Computer Architecture Lecture 2: Instruction Set Principles (Appendix A) Chih Wei Liu 劉志尉 National Chiao Tung University cwliu@twins.ee.nctu.edu.

Computer Architecture Lecture 2: Instruction Set Principles (Appendix A) Chih Wei Liu 劉志尉 National Chiao Tung University cwliu@twins.ee.nctu.edu.tw Review Computers in mid 50 s Hardware was expensive