Chapter 4 Lecture 5 The Microarchitecture Level Integer JAVA Virtual Machine

Size: px
Start display at page:

Download "Chapter 4 Lecture 5 The Microarchitecture Level Integer JAVA Virtual Machine"

Transcription

1 Chapter 4 Lecture 5 The Microarchitecture Level Integer JAVA Virtual Machine This is a limited version of a hardware implementation to execute the JAVA programming language. 1 of 23 Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, ISBN

2 Review IJVM Programmer Model and Organization Method Area External Program Memory containing the IJVM program to be executed. The internal PC is a pointer in the Method Area to the next instruction to be executed. The method area is accessed using the PC with 8-bit instructions and parameters loaded into the MBR. Constant Pool External Data Memory containing compiled constants (e.g. values, strings, pointers, etc.) required by the Methods to execute programs. Local Variable Frame Operand Stack External Data Memory allocated for the storage of variables for the method being executed. When a method is invoked, a local variable frame of predefined size is established (allocated) for all local variables used by the method External Data Memory used for the storage of temporary operands that are placed on the stack. The Operand Stack maximum size is known when a Method is invoked. Note on the IJVM Theory of operations: Data memory is accessed using an indexed offset from known internal register memory pointers (i.e. LV local variable, CPP constant pool) The local variable frame includes both the local variables and the operand stack. Note that since the maximum size of the stack is known, the maximum size of the local variable frame is known. 2 of 23 Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, ISBN

3 IJVM Microinstruction 1 (MIC-1) Architecture Language: iload & wide iload & ldc_w Using common elements for instructions pushing data onto the stack. main1 PC = PC + 1; fetch; goto (MBR) MBR holds opcode; get next byte; dispatch iload1 H = LV MBR contains index; copy LV to H iload2 MAR = MBRU + H; rd MAR = address of local variable to push iload3 MAR = SP = SP + 1 SP points to new top of stack; prepare write iload4 PC = PC + 1; fetch; wr Inc PC; get next opcode; write top of stack iload5 TOS = MDR; goto main1 Update TOS main1 PC = PC + 1; fetch; goto (MBR) MBR holds opcode; get next byte; dispatch wide1 PC = PC+ 1; fetch; Multiway branch with high bit set goto (MBR OR 0x100) wide_iload1 PC = PC + 1; fetch MBR contains 1st index byte; fetch 2nd wide_iload2 H = MBRU << 8 H = 1st index byte shifted left 8 bits wide_iload3 H = MBRU OR H H = 16-bit index of local variable wide_iload4 MAR = LV + H; rd; goto iload3 MAR = address of local variable to push main1 PC = PC + 1; fetch; goto (MBR) MBR holds opcode; get next byte; dispatch wide1 PC = PC+ 1; fetch; Multiway branch with high bit set goto (MBR OR 0x100) ldc_w1 PC = PC + 1; fetch MBR contains 1st index byte; fetch 2nd ldc_w2 H = MBRU << 8 H = 1st index byte << 8 ldc_w3 H = MBRU OR H H = 16-bit index into constant pool ldc_w4 MAR = H + CPP; rd; goto iload3 MAR = address of constant in pool iload3 MAR = SP = SP + 1 SP points to new top of stack; prepare write iload4 PC = PC + 1; fetch; wr Inc PC; get next opcode; write top of stack iload5 TOS = MDR; goto main1 Update TOS 3 of 23 Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, ISBN

4 ILOAD (0x15h) Pushing a variable from the Local Variable Memory Space unto the stack JAVA: ILOAD varnum MAL: main1 and iload1(0x015) to iload5 Label Operations Comments main1 PC = PC + 1; fetch; goto (MBR) MBR holds opcode; get next byte; dispatch iload1 H = LV MBR contains index; copy LV to H iload2 MAR = MBRU + H; rd MAR = address of local variable to push iload3 MAR = SP = SP + 1 SP points to new top of stack; prepare write iload4 PC = PC + 1; fetch; wr Inc PC; get next opcode; write top of stack iload5 TOS = MDR; goto main1 Update TOS Similar instructions: ISTORE 4 of 23 Structured Computer Organization 5th ed., Prentice Hall, Upper Sable River, NJ, ISBN

5 Executing the JAVA ILOAD Instruction in Mic-1 Cycle MPC main1 iload1 iload2 iload3 iload4 iload5 main1 INST PC= PC+1; fetch; goto (MBR) H= LV MAR= MBRU + H; rd MAR= SP = SP+1 PC= PC+1; fetch; wr TOS= MDR; goto main1 PC= PC+1; fetch; goto (MBR) Next MPC gt (iload1) iload2 iload3 iload4 iload5 main1 gt (MBR) PC fetch PC PC+1 fetch PC+2 fetch MBR iload1 VARNM INST MAR rd/wr LV+VARNM rd SP+1 wr MDR PARAM SP SP SP+1 LV CPP TOS (@SP) PARAM H LV 5 of 23

6 WIDE ILOAD (0xC4 0x15) Pushing a variable from the Local Variable Memory Space unto the stack JAVA: WIDE ILOAD varnum1 varnum2 MAL: main1 and wide_iload1(0x115) to wide_iload4 and iload3 to iload5 Note, wide requires that the instruction path from the instruction memory to the micropc uses a gated latch instead of being super-synchronous operation. The MBR register with output to the B-bus is still a super-synchronous multiplexed clocked register. See notes chap. 4-3 for more detail. Label Operations Comments main1 PC = PC + 1; fetch; goto (MBR) MBR holds opcode; get next byte; dispatch wide1 PC = PC+ 1; fetch; goto (MBR OR 0x100) Multiway branch with high bit set wide_iload1 PC = PC + 1; fetch MBR contains 1st index byte; fetch 2nd wide_iload2 H = MBRU << 8 H = 1st index byte shifted left 8 bits wide_iload3 H = MBRU OR H wide_iload4 MAR = LV + H; rd; goto iload3 H = 16-bit index of local variable MAR = address of local variable to push iload3 MAR = SP = SP + 1 SP points to new top of stack; prepare write iload4 PC = PC + 1; fetch; wr Inc PC; get next opcode; write top of stack iload5 TOS = MDR; goto main1 Update TOS Similar instructions: WIDE ISTORE, WIDE LDC_W index1 index2 6 of 23 Structured Computer Organization 4th ed., Prentice Hall, Upper Sable River, NJ, ISBN

7 Executing the JAVA WIDE ILOAD Instruction in Mic-1 Cycle MPC main1 wide1 wide_iload1 wide_iload2 wide_iload3 wide_iload4 iload3 INST Next MPC PC fetch PC= PC+1; fetch; goto (MBR) gt (wide1) PC PC = PC+ 1; fetch; goto (MBR OR 0x100) (0x100 OR JAMC) PC+1 fetch PC = PC + 1; fetch H = MBRU << 8 H = MBRU OR H MAR = LV + H; rd; goto iload3 MAR= SP = SP+1 wide_iload2 wide_iload3 wide_iload4 iload3 iload4 PC+1 fetch PC+1 fetch MBR wide1 iload1 VAR1 VAR2 MAR rd/wr MDR SP SP LV CPP TOS (@SP) PC+2 fetch H VAR1<< 8 VAR1<< 8 OR VAR2 iload1 is forwarded to the MPC by using fetch as a gated path. MBR represents a clocked path to the B-bus. LV+H rd 7 of 23

8 Invoking Methods and Returning processes involved in subroutine/object calls For the IJVM, this is how a known subroutine would be executed. (This implementation is technically not object oriented.) For JAVA, additional software would be used to discover the method (dynamically locate), acquire the appropriate address (dynamically linking to the object), and then execute the method. JAVA Inst: INVOKEVIRTUAL disp Disp is a 16-bit offset into the constant pool where the subroutine s address is stored. Method (Subroutine) Area Structure: 4-bytes of Special Data followed by instructions Special Data needed to describe: How many parameters were passed to the method (Num_parms) How many variables are needed by the method (LV_size) Setting up the local variable frame: How many parameters were passed to the method (SP-#parms LV) How many variables are needed by the method Program Memory Space: IRETURN Post- MethodPC PC Next INST disp ls-byte disp ms-byte INVOKEVIRTUAL Method PC 1st INST LV_size ls-byte LV_size ms-byte Num_parms ls-byte Num_parms ms-byte Program Memory Space Required for a Method to be invoked 8 of 23

9 How a subroutine (or method) is called: the IJVM definition (1) push an object reference (pointer) to the object to be called (consistent with JVMs) (2) push method parameters onto the stack (3) invoke the method Use the CPP to locate the new method s address. Use special data (4-bytes) at the method s address to define storage needed Create a new local variable frame Store values required to return from the method (PC, LV) Necessary Local Variable Frame and Stack Changes Data Memory (a) before and (b) after invoking a method 9 of 23

10 IJVM invokevirtual microinstructions The process reads the address of the method The old PC is temporarily saved in the OPC register The new PC is installed and the 1 st 16-bit value will be fetched main1 PC = PC + 1; fetch; goto (MBR) MBR holds opcode; get next byte; dispatch invokevirtual1 PC = PC + 1; fetch MBR = index byte 1; inc. PC, get 2nd byte invokevirtual2 H = MBRU << 8 Shift and save first byte in H invokevirtual3 H = MBRU OR H H = offset of method pointer from CPP invokevirtual4 MAR = CPP + H; rd Get pointer to method from CPP area invokevirtual5 OPC = PC + 1 Save Return PC in OPC temporarily invokevirtual6 PC = MDR; fetch PC points to new method; get param count Use the first 16-bit value to determine where the original SP was (OBJREF storage-1) Prepare to overwrite OBJREF and determine the new value for LV Fetch the size of the local variable frame invokevirtual7 PC = PC + 1; fetch Fetch 2nd byte of parameter count invokevirtual8 H = MBRU << 8 Shift and save first byte in H invokevirtual9 H = MBRU OR H H = number of parameters invokevirtual10 PC = PC + 1; fetch Fetch first byte of # locals invokevirtual11 TOS = SP - H TOS = address of OBJREF - 1 invokevirtual12 TOS = MAR = TOS + 1 TOS = address of OBJREF (new LV) Manipulations of the local-variable frame after the previous instructions INVOKE SP OLD SP Parm2 Parm1 OBJREF INVOKE SP TOS and eventual LV Parm2 Parm1 OBJREF OLD Local Variable Frame OLD Local Variable Frame 10 of 23

11 Overwrite the OBJREF with the top value of the parameters and local variables or link pointer(also where the return PC is going to go) Set the SP to be at the top of the parameters and local variables Set the MAR to write the old PC and old LV invokevirtual13 PC = PC + 1; fetch invokevirtual14 H = MBRU << 8 invokevirtual15 H = MBRU OR H invokevirtual16 MDR = SP + H + 1; wr invokevirtual17 MAR = SP = MDR; Fetch second byte of # locals Shift and save first byte in H H = # locals Overwrite OBJREF with link pointer Set SP, MAR to location to hold old PC Manipulations of the local-variable frame after the previous instructions SP INVOKE SP TOS and eventual LV Parm2 Parm1 OBJREF TOS and eventual LV Parm2 Parm1 OBJREF OLD Local Variable Frame OLD Local Variable Frame 11 of 23

12 Finally, Write the OLD PC to the stack Write the OLD LV to the stack Set the new LV to the address of the link pointer. fetch the first instruction of the new method. DONE!!! invokevirtual18 MDR = OPC; wr invokevirtual19 MAR = SP = SP + 1 invokevirtual20 MDR = LV; wr invokevirtual21 PC = PC + 1; fetch invokevirtual22 LV = TOS; goto main1 Save old PC above the local variables SP points to location to hold old LV Save old LV above saved PC Fetch first opcode of new method. Set LV to point to LV Frame Necessary Local Variable Frame and Stack Changes Data Memory (a) before and (b) after invoking a method 12 of 23

13 Returning from a Method Returning from a method must return operation to the original program, restore the original LV, restore the stack pointer to the previous location and add a return value (from the TOS register) onto the top of the stack IJVM Microinstruction 1 (MIC-1) Architecture Language ireturn1 MAR = SP = LV; rd Reset SP, MAR to get link pointer ireturn2 Wait for read ireturn3 LV = MAR = MDR; rd Set LV to link ptr; get old PC ireturn4 MAR = LV + 1 Set MAR to read old LV ireturn5 PC = MDR; rd; fetch Restore PC; fetch next opcode ireturn6 MAR = SP Set MAR to write TOS ireturn7 LV = MDR Restore LV ireturn8 MDR = TOS; wr; goto main1 Save return value on original top of stack The end of IJVM Microarchitecture 1 (Mic-1) 13 of 23

14 Speeding Up Microarchitecture 1 of the Integer JAVA Virtual Machine How can we attain higher clock rates for the machine? Take the basic concept and design it over more engineering time ($$) Add more gates where the design needs it more time, more gates, more silicon ($$$) 14 of 23

15 Ideas: (1) Reduce the number of clock cycles per instruction (CPI) (2) Perform instruction fetch and data processing in parallel (3) Make each one of the clock cycles shorter (4) Simplify data flow to the ALU (H-register loading) (5) Overlap the execution of instructions (pipeline) Possibilities: (1) Make an intelligent instruction fetch unit (a) Eliminate PC increment from using the execution unit (b) Eliminate main1 (c) Eliminate multi-byte instruction fetch delays (d) Add an instruction queue (precursor to a cache) (2) Eliminate the need to load the H register (a) Add a new data path bus, the A-Bus (b) Increase the MIR size to add an A-Bus decoder and multiplexer 15 of 23

16 Instruction Fetch Unit (1) Make an intelligent instruction fetch unit (a) Eliminate PC increment from using the execution unit (b) Eliminate main1 (c) Eliminate multi-byte instruction fetch delays (d) Add an instruction queue (precursor to a cache) Architecture Elements (1) The PC has it s own incrementer! New Instruction Fetch Unit (2) An instruction queue has been added so that future instructions can be preloaded. (a) This requires an Instruction memory address register (IMAR) that is ahead of the PC (b) Special consideration must be made for branching (flush queue and stall) (3) Two pseudo-register created to hold 1-Byte and 2-Byte offsets, displacements, etc. (MBR1 and MBR2) (4) Queued instruction interpretation predetermine the length of each instruction (a) Necessary to drive the IMAR logic and prefetch (b) The IFU instruction fetch finite state machine Note: IMAR fetches 32-bit words (4 bytes) whenever the queue nears empty. 16 of 23

17 How the instruction queue is filled: queue depth and queue byte count Advantages Eliminated main1 code and delays Eliminated PC manipulations Generated 8-byte and 16-byte instruction values Allows 32-bit memory accesses (similar to data path) 17 of 23

18 Datapath for the Mic-2 Eliminate the need to load the H register (a) Add a new data path bus, the A-Bus (b) Increase the MIR size to add an A-Bus decoder and multiplexer (+ 4-bits) Architecture Elements: (1) A three-bus internal processor architecture: 2 operand buses with 1 result bus (2) Hardware design optimization of the ALU. That is use another ALU design with less delay! Other methods discussed, but not shown. 18 of 23

19 The modified microinstruction code speedup a.) b.) Main 1 removed (one clock cycle for every instruction executed) ALU arithmetic and logical operations: iadd,, isub, iand, ior, dup, swap are all similar (reduced by one cycle per instruction) Limitation to speed-up: significant amount of reading and writing memory c.) Stack Manipulation: bipush eliminates Byte reading iload and istore eliminate reading the offset value wide_iload and wide_istore eliminate reading the wide offset value ldc_w eliminate reading the wide offset value iinc eliminate both offset and immediate value fetching Significant improvement due to MBR1 and MBR2 availability Nominally 3 cycles per instruction savings d.) Branching Operations: goto eliminate target address computations iflt and ifeq and if_icmpeq no significant changes (memory read bound) T no change F must signal Instruction Fetch Unit to remove the branch address from MBR2 (more logic) e.) Subroutine Call: invokevirtual goes from 22 to 11 cycles ireturn no changes Overall: A significant reduction in the required microcode store and a significantly faster machine. Instructions least affected: data reading and writing Instructions most affected: those requiring immediate values from the instruction stream 19 of 23

20 The modified microinstruction code (MIC-2): IJVM Microinstruction 2 (MIC-2) Architecture Language (1 of 4) nop1 goto (MBR) Branch to next instruction iadd1 MAR = SP = SP-1; rd Read in next-to-top word on stack iadd2 H = TOS H = top of stack (optional) iadd3 MDR = TOS = MDR+H; wr; goto (MBR1) Add top two words; write to new top of stack isub1 MAR = SP = SP-1; rd Read in next-to-top word on stack isub2 H = TOS H = top of stack (optional) isub3 MDR = TOS = MDR-H; wr; goto (MBR1) Subtract TOS from Fetched TOS- 1 iand1 MAR = SP = SP-1; rd Read in next-to-top word on stack iand2 H = TOS H = top of stack (optional) iand3 MDR= TOS = MDR AND H; wr; AND Fetched TOS-1 with TOS goto (MBR1) ior1 MAR = SP = SP-1; rd Read in next-to-top word on stack ior2 H = TOS H = top of stack (optional) ior3 MDR= TOS = MDR OR H; wr; OR Fetched TOS-1 with TOS goto (MBR1) dup1 MAR = SP = SP + 1 Increment SP; copy to MAR dup2 MDR = TOS; wr; goto (MBR1) Write new stack word pop1 MAR = SP = SP-1; rd Read in next-to-top word on stack pop2 Wait for read pop3 TOS = MDR; goto (MBR1) Copy new word to TOS swap1 MAR = SP-1; rd Read 2nd word from stack; set MAR to SP swap2 MAR = SP Prepare to write new 2nd word swap3 H = MDR; wr Save new TOS; write 2nd word to stack swap4 MDR = TOS Copy old TOS to MDR swap5 MAR = SP-1; wr Write old TOS to 2nd place on stack swap6 TOS = H; goto (MBR1) Update TOS Overview: Main 1 removed iadd,, isub, iand, ior, dup, swap are all similar (reduced by one cycle per instruction) Limitation to speed-up: significant amount of reading and writing memory 20 of 23

21 IJVM Microinstruction 2 (MIC-2) Architecture Language (2 of 4) bipush1 SP = MAR = SP + 1 Set up MAR for writing to new top of stack bipush2 MDR = TOS = MBR1; wr; goto Update stack in TOS and memory (MBR1) iload1 MAR = LV + MBR1U; rd Move LV + index to MAR; read operand iload2 MAR = SP = SP + 1 Increment SP; Move new SP to MAR iload3 TOS = MDR; wr; goto (MBR1) Update stack in TOS and memory istore1 MAR = LV + MBR1U Set MAR to LV + index istore2 MDR = TOS; wr Copy TOS for storing istore3 MAR = SP = SP 1; rd Decrement SP; read new TOS istore4 Wait for read istore5 TOS = MDR; goto (MBR1) Update TOS wide1 goto (MBR1 OR 0x100) Next address is 0x100 Ored with opcode wide_iload1 MAR = LV + MBR2U; rd; goto iload2 Identical to iload1 but using 2-byte index wide_istore1 MAR = LV + MBR2U; goto istore2 Identical to istore1 but using 2- byte index ldc_w1 MAR = CPP + MBR2U; rd; goto iload2 Same as wide_iload1 but indexing off CPP Overview: bipush eliminates Byte reading! iload and istore eliminate reading the offset value wide_iload and wide_istore eliminate reading the wide offset value ldc_w eliminate reading the wide offset value Significant improvement due to MBR1 and MBR2 availability Nominally 3 cycles per instruction savings 21 of 23

22 IJVM Microinstruction 2 (MIC-2) Architecture Language (3 of 4) iinc1 MAR = LV + MBR1U; rd Set MAR to LV + index for read iinc2 H = MBR1 Set H to constant iinc3 MDR = MDR + H; wr; goto Increment by constant and update (MBR1) goto1 H = PC 1 Copy PC to H goto2 PC = H + MBR2 Add offset and update PC goto3 Have to wait for IFU to fetch new opcode goto4 goto (MBR1) Dispatch to next instruction iflt1 MAR = SP = SP 1; rd Read in next-to-top word on stack iflt2 OPC = TOS Save TOS in OPC temporarily iflt3 TOS = MDR Put new top of stack in TOS iflt4 N = OPC; if (N) goto T; else goto F Branch on N bit ifeq1 MAR = SP = SP 1; rd Read in next-to-top word of stack ifeq2 OPC = TOS Save TOS in OPC temporarily ifeq3 TOS = MDR Put new top of stack in TOS ifeq4 Z = OPC; if (Z) goto T; else goto F Branch on Z bit if_icmpeq1 MAR = SP = SP 1; rd Read in next-to-top word of stack if_icmpeq2 MAR = SP = SP 1 Set MAR to read in new top-ofstack if_icmpeq3 H = MDR; rd Copy second stack word to H if_icmpeq4 OPC = TOS Save TOS in OPC temporarily if_icmpeq5 TOS = MDR Put new top of stack in TOS if_icmpeq6 Z = H OPC; if (Z) goto T; else goto F If top 2 words are equal, goto T, else goto F T H=PC 1; goto goto2 Same as goto1 F H = MBR2 Touch bytes in MBR2 to discard F2 goto (MBR1) Overview: iinc eliminate both offset and immediate value fetching goto eliminates target address computations iflt and ifeq and if_icmpeq no significant changes (memory read bound) T no change F must signal IFO to remove the branch address from MBR2 22 of 23

23 IJVM Microinstruction 2 (MIC-2) Architecture Language (4 of 4) invokevirtual1 MAR = CPP + MBR2U; rd Put address of method pointer in MAR invokevirtual2 OPC = PC Save Return PC in OPC invokevirtual3 PC = MDR Set PC to 1st byte of method code. invokevirtual4 TOS = SP MBR2U TOS = address of OBJREF 1 invokevirtual5 TOS = MAR = H = TOS + 1 TOS = address of OBJREF invokevirtual6 MDR = SP + MBR2U + 1; wr Overwrite OBJREF with link pointer invokevirtual7 MAR = SP = MDR Set SP, MAR to location to hold old PC invokevirtual8 MDR = OPC; wr Prepare to save old PC invokevirtual9 MAR = SP = SP + 1 Inc. SP to point to location to hold old LV invokevirtual10 MDR = LV; wr Save old LV invokevirtual11 LV = TOS; goto (MBR1) Set LV to point to zeroth parameter. ireturn1 MAR = SP = LV; rd Reset SP, MAR to read Link ptr ireturn2 Wait for link ptr ireturn3 LV = MAR = MDR; rd Set LV, MAR to link ptr; read old PC ireturn4 MAR = LV + 1 Set MAR to point to old LV; read old LV ireturn5 PC = MDR; rd Restore PC ireturn6 MAR = SP ireturn7 LV = MDR Restore LV ireturn8 MDR = TOS; wr; goto (MBR1) Save return value on original top of stack Overview: invokevirtual goes from 22 to 11 cycles ireturn no changes Overall: A significant reduction in the required microcode store and a significantly faster machine. Instructions least affected: data reading and writing Instructions most affected: those requiring immediate values from the instruction stream 23 of 23

Chapter 7D The Java Virtual Machine

Chapter 7D The Java Virtual Machine This sub chapter discusses another architecture, that of the JVM (Java Virtual Machine). In general, a VM (Virtual Machine) is a hypothetical machine (implemented in either hardware or software) that directly

More information

picojava TM : A Hardware Implementation of the Java Virtual Machine

picojava TM : A Hardware Implementation of the Java Virtual Machine picojava TM : A Hardware Implementation of the Java Virtual Machine Marc Tremblay and Michael O Connor Sun Microelectronics Slide 1 The Java picojava Synergy Java s origins lie in improving the consumer

More information

Interpreters and virtual machines. Interpreters. Interpreters. Why interpreters? Tree-based interpreters. Text-based interpreters

Interpreters and virtual machines. Interpreters. Interpreters. Why interpreters? Tree-based interpreters. Text-based interpreters Interpreters and virtual machines Michel Schinz 2007 03 23 Interpreters Interpreters Why interpreters? An interpreter is a program that executes another program, represented as some kind of data-structure.

More information

MICROPROCESSOR. Exclusive for IACE Students www.iace.co.in iacehyd.blogspot.in Ph: 9700077455/422 Page 1

MICROPROCESSOR. Exclusive for IACE Students www.iace.co.in iacehyd.blogspot.in Ph: 9700077455/422 Page 1 MICROPROCESSOR A microprocessor incorporates the functions of a computer s central processing unit (CPU) on a single Integrated (IC), or at most a few integrated circuit. It is a multipurpose, programmable

More information

Advanced Computer Architecture-CS501. Computer Systems Design and Architecture 2.1, 2.2, 3.2

Advanced Computer Architecture-CS501. Computer Systems Design and Architecture 2.1, 2.2, 3.2 Lecture Handout Computer Architecture Lecture No. 2 Reading Material Vincent P. Heuring&Harry F. Jordan Chapter 2,Chapter3 Computer Systems Design and Architecture 2.1, 2.2, 3.2 Summary 1) A taxonomy of

More information

A3 Computer Architecture

A3 Computer Architecture A3 Computer Architecture Engineering Science 3rd year A3 Lectures Prof David Murray david.murray@eng.ox.ac.uk www.robots.ox.ac.uk/ dwm/courses/3co Michaelmas 2000 1 / 1 6. Stacks, Subroutines, and Memory

More information

02 B The Java Virtual Machine

02 B The Java Virtual Machine 02 B The Java Virtual Machine CS1102S: Data Structures and Algorithms Martin Henz January 22, 2010 Generated on Friday 22 nd January, 2010, 09:46 CS1102S: Data Structures and Algorithms 02 B The Java Virtual

More information

CHAPTER 7: The CPU and Memory

CHAPTER 7: The CPU and Memory CHAPTER 7: The CPU and Memory The Architecture of Computer Hardware, Systems Software & Networking: An Information Technology Approach 4th Edition, Irv Englander John Wiley and Sons 2010 PowerPoint slides

More information

Central Processing Unit (CPU)

Central Processing Unit (CPU) Central Processing Unit (CPU) CPU is the heart and brain It interprets and executes machine level instructions Controls data transfer from/to Main Memory (MM) and CPU Detects any errors In the following

More information

Overview. CISC Developments. RISC Designs. CISC Designs. VAX: Addressing Modes. Digital VAX

Overview. CISC Developments. RISC Designs. CISC Designs. VAX: Addressing Modes. Digital VAX Overview CISC Developments Over Twenty Years Classic CISC design: Digital VAX VAXÕs RISC successor: PRISM/Alpha IntelÕs ubiquitous 80x86 architecture Ð 8086 through the Pentium Pro (P6) RJS 2/3/97 Philosophy

More information

1 The Java Virtual Machine

1 The Java Virtual Machine 1 The Java Virtual Machine About the Spec Format This document describes the Java virtual machine and the instruction set. In this introduction, each component of the machine is briefly described. This

More information

Computer Architecture Lecture 2: Instruction Set Principles (Appendix A) Chih Wei Liu 劉 志 尉 National Chiao Tung University cwliu@twins.ee.nctu.edu.

Computer Architecture Lecture 2: Instruction Set Principles (Appendix A) Chih Wei Liu 劉 志 尉 National Chiao Tung University cwliu@twins.ee.nctu.edu. Computer Architecture Lecture 2: Instruction Set Principles (Appendix A) Chih Wei Liu 劉 志 尉 National Chiao Tung University cwliu@twins.ee.nctu.edu.tw Review Computers in mid 50 s Hardware was expensive

More information

150127-Microprocessor & Assembly Language

150127-Microprocessor & Assembly Language Chapter 3 Z80 Microprocessor Architecture The Z 80 is one of the most talented 8 bit microprocessors, and many microprocessor-based systems are designed around the Z80. The Z80 microprocessor needs an

More information

language 1 (source) compiler language 2 (target) Figure 1: Compiling a program

language 1 (source) compiler language 2 (target) Figure 1: Compiling a program CS 2112 Lecture 27 Interpreters, compilers, and the Java Virtual Machine 1 May 2012 Lecturer: Andrew Myers 1 Interpreters vs. compilers There are two strategies for obtaining runnable code from a program

More information

(Refer Slide Time: 00:01:16 min)

(Refer Slide Time: 00:01:16 min) Digital Computer Organization Prof. P. K. Biswas Department of Electronic & Electrical Communication Engineering Indian Institute of Technology, Kharagpur Lecture No. # 04 CPU Design: Tirning & Control

More information

UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180B Lab 7: MISP Processor Design Spring 1995

UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180B Lab 7: MISP Processor Design Spring 1995 UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180B Lab 7: MISP Processor Design Spring 1995 Objective: In this lab, you will complete the design of the MISP processor,

More information

How It All Works. Other M68000 Updates. Basic Control Signals. Basic Control Signals

How It All Works. Other M68000 Updates. Basic Control Signals. Basic Control Signals CPU Architectures Motorola 68000 Several CPU architectures exist currently: Motorola Intel AMD (Advanced Micro Devices) PowerPC Pick one to study; others will be variations on this. Arbitrary pick: Motorola

More information

LSN 2 Computer Processors

LSN 2 Computer Processors LSN 2 Computer Processors Department of Engineering Technology LSN 2 Computer Processors Microprocessors Design Instruction set Processor organization Processor performance Bandwidth Clock speed LSN 2

More information

The Java Virtual Machine and Mobile Devices. John Buford, Ph.D. buford@alum.mit.edu Oct 2003 Presented to Gordon College CS 311

The Java Virtual Machine and Mobile Devices. John Buford, Ph.D. buford@alum.mit.edu Oct 2003 Presented to Gordon College CS 311 The Java Virtual Machine and Mobile Devices John Buford, Ph.D. buford@alum.mit.edu Oct 2003 Presented to Gordon College CS 311 Objectives Review virtual machine concept Introduce stack machine architecture

More information

Chapter 5, The Instruction Set Architecture Level

Chapter 5, The Instruction Set Architecture Level Chapter 5, The Instruction Set Architecture Level 5.1 Overview Of The ISA Level 5.2 Data Types 5.3 Instruction Formats 5.4 Addressing 5.5 Instruction Types 5.6 Flow Of Control 5.7 A Detailed Example: The

More information

Computer organization

Computer organization Computer organization Computer design an application of digital logic design procedures Computer = processing unit + memory system Processing unit = control + datapath Control = finite state machine inputs

More information

PROBLEMS. which was discussed in Section 1.6.3.

PROBLEMS. which was discussed in Section 1.6.3. 22 CHAPTER 1 BASIC STRUCTURE OF COMPUTERS (Corrisponde al cap. 1 - Introduzione al calcolatore) PROBLEMS 1.1 List the steps needed to execute the machine instruction LOCA,R0 in terms of transfers between

More information

MICROPROCESSOR AND MICROCOMPUTER BASICS

MICROPROCESSOR AND MICROCOMPUTER BASICS Introduction MICROPROCESSOR AND MICROCOMPUTER BASICS At present there are many types and sizes of computers available. These computers are designed and constructed based on digital and Integrated Circuit

More information

PROBLEMS #20,R0,R1 #$3A,R2,R4

PROBLEMS #20,R0,R1 #$3A,R2,R4 506 CHAPTER 8 PIPELINING (Corrisponde al cap. 11 - Introduzione al pipelining) PROBLEMS 8.1 Consider the following sequence of instructions Mul And #20,R0,R1 #3,R2,R3 #$3A,R2,R4 R0,R2,R5 In all instructions,

More information

Instruction Set Architecture. or How to talk to computers if you aren t in Star Trek

Instruction Set Architecture. or How to talk to computers if you aren t in Star Trek Instruction Set Architecture or How to talk to computers if you aren t in Star Trek The Instruction Set Architecture Application Compiler Instr. Set Proc. Operating System I/O system Instruction Set Architecture

More information

Chapter 5 Instructor's Manual

Chapter 5 Instructor's Manual The Essentials of Computer Organization and Architecture Linda Null and Julia Lobur Jones and Bartlett Publishers, 2003 Chapter 5 Instructor's Manual Chapter Objectives Chapter 5, A Closer Look at Instruction

More information

Habanero Extreme Scale Software Research Project

Habanero Extreme Scale Software Research Project Habanero Extreme Scale Software Research Project Comp215: Java Method Dispatch Zoran Budimlić (Rice University) Always remember that you are absolutely unique. Just like everyone else. - Margaret Mead

More information

An Overview of Stack Architecture and the PSC 1000 Microprocessor

An Overview of Stack Architecture and the PSC 1000 Microprocessor An Overview of Stack Architecture and the PSC 1000 Microprocessor Introduction A stack is an important data handling structure used in computing. Specifically, a stack is a dynamic set of elements in which

More information

Q. Consider a dynamic instruction execution (an execution trace, in other words) that consists of repeats of code in this pattern:

Q. Consider a dynamic instruction execution (an execution trace, in other words) that consists of repeats of code in this pattern: Pipelining HW Q. Can a MIPS SW instruction executing in a simple 5-stage pipelined implementation have a data dependency hazard of any type resulting in a nop bubble? If so, show an example; if not, prove

More information

VLIW Processors. VLIW Processors

VLIW Processors. VLIW Processors 1 VLIW Processors VLIW ( very long instruction word ) processors instructions are scheduled by the compiler a fixed number of operations are formatted as one big instruction (called a bundle) usually LIW

More information

An Introduction to the ARM 7 Architecture

An Introduction to the ARM 7 Architecture An Introduction to the ARM 7 Architecture Trevor Martin CEng, MIEE Technical Director This article gives an overview of the ARM 7 architecture and a description of its major features for a developer new

More information

Chapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language

Chapter 4 Register Transfer and Microoperations. Section 4.1 Register Transfer Language Chapter 4 Register Transfer and Microoperations Section 4.1 Register Transfer Language Digital systems are composed of modules that are constructed from digital components, such as registers, decoders,

More information

Systems I: Computer Organization and Architecture

Systems I: Computer Organization and Architecture Systems I: Computer Organization and Architecture Lecture : Microprogrammed Control Microprogramming The control unit is responsible for initiating the sequence of microoperations that comprise instructions.

More information

Instruction Set Architecture (ISA)

Instruction Set Architecture (ISA) Instruction Set Architecture (ISA) * Instruction set architecture of a machine fills the semantic gap between the user and the machine. * ISA serves as the starting point for the design of a new machine

More information

EE361: Digital Computer Organization Course Syllabus

EE361: Digital Computer Organization Course Syllabus EE361: Digital Computer Organization Course Syllabus Dr. Mohammad H. Awedh Spring 2014 Course Objectives Simply, a computer is a set of components (Processor, Memory and Storage, Input/Output Devices)

More information

CPU Organization and Assembly Language

CPU Organization and Assembly Language COS 140 Foundations of Computer Science School of Computing and Information Science University of Maine October 2, 2015 Outline 1 2 3 4 5 6 7 8 Homework and announcements Reading: Chapter 12 Homework:

More information

CPU Organisation and Operation

CPU Organisation and Operation CPU Organisation and Operation The Fetch-Execute Cycle The operation of the CPU 1 is usually described in terms of the Fetch-Execute cycle. 2 Fetch-Execute Cycle Fetch the Instruction Increment the Program

More information

Computer Organization and Components

Computer Organization and Components Computer Organization and Components IS5, fall 25 Lecture : Pipelined Processors ssociate Professor, KTH Royal Institute of Technology ssistant Research ngineer, University of California, Berkeley Slides

More information

ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-12: ARM

ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-12: ARM ADVANCED PROCESSOR ARCHITECTURES AND MEMORY ORGANISATION Lesson-12: ARM 1 The ARM architecture processors popular in Mobile phone systems 2 ARM Features ARM has 32-bit architecture but supports 16 bit

More information

Instruction Set Architecture

Instruction Set Architecture Instruction Set Architecture Consider x := y+z. (x, y, z are memory variables) 1-address instructions 2-address instructions LOAD y (r :=y) ADD y,z (y := y+z) ADD z (r:=r+z) MOVE x,y (x := y) STORE x (x:=r)

More information

A single register, called the accumulator, stores the. operand before the operation, and stores the result. Add y # add y from memory to the acc

A single register, called the accumulator, stores the. operand before the operation, and stores the result. Add y # add y from memory to the acc Other architectures Example. Accumulator-based machines A single register, called the accumulator, stores the operand before the operation, and stores the result after the operation. Load x # into acc

More information

Real-time Java Processor for Monitoring and Test

Real-time Java Processor for Monitoring and Test Real-time Java Processor for Monitoring and Test Martin Zabel, Thomas B. Preußer, Rainer G. Spallek Technische Universität Dresden {zabel,preusser,rgs}@ite.inf.tu-dresden.de Abstract This paper introduces

More information

Instruction Folding in a Hardware-Translation Based Java Virtual Machine

Instruction Folding in a Hardware-Translation Based Java Virtual Machine Instruction Folding in a Hardware-Translation Based Java Virtual Machine Hitoshi Oi Department of Computer Science The University of Aizu Aizu-Wakamatsu, JAPAN hitoshi at u-aizu.ac.jp ABSTRACT Bytecode

More information

Chapter 2 Basic Structure of Computers. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 2 Basic Structure of Computers. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Chapter 2 Basic Structure of Computers Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Functional Units Basic Operational Concepts Bus Structures Software

More information

MACHINE ARCHITECTURE & LANGUAGE

MACHINE ARCHITECTURE & LANGUAGE in the name of God the compassionate, the merciful notes on MACHINE ARCHITECTURE & LANGUAGE compiled by Jumong Chap. 9 Microprocessor Fundamentals A system designer should consider a microprocessor-based

More information

Computer Organization and Architecture

Computer Organization and Architecture Computer Organization and Architecture Chapter 11 Instruction Sets: Addressing Modes and Formats Instruction Set Design One goal of instruction set design is to minimize instruction length Another goal

More information

PROBLEMS (Cap. 4 - Istruzioni macchina)

PROBLEMS (Cap. 4 - Istruzioni macchina) 98 CHAPTER 2 MACHINE INSTRUCTIONS AND PROGRAMS PROBLEMS (Cap. 4 - Istruzioni macchina) 2.1 Represent the decimal values 5, 2, 14, 10, 26, 19, 51, and 43, as signed, 7-bit numbers in the following binary

More information

The Java Virtual Machine (JVM) Pat Morin COMP 3002

The Java Virtual Machine (JVM) Pat Morin COMP 3002 The Java Virtual Machine (JVM) Pat Morin COMP 3002 Outline Topic 1 Topic 2 Subtopic 2.1 Subtopic 2.2 Topic 3 2 What is the JVM? The JVM is a specification of a computing machine Instruction set Primitive

More information

what operations can it perform? how does it perform them? on what kind of data? where are instructions and data stored?

what operations can it perform? how does it perform them? on what kind of data? where are instructions and data stored? Inside the CPU how does the CPU work? what operations can it perform? how does it perform them? on what kind of data? where are instructions and data stored? some short, boring programs to illustrate the

More information

Solution: start more than one instruction in the same clock cycle CPI < 1 (or IPC > 1, Instructions per Cycle) Two approaches:

Solution: start more than one instruction in the same clock cycle CPI < 1 (or IPC > 1, Instructions per Cycle) Two approaches: Multiple-Issue Processors Pipelining can achieve CPI close to 1 Mechanisms for handling hazards Static or dynamic scheduling Static or dynamic branch handling Increase in transistor counts (Moore s Law):

More information

EC 362 Problem Set #2

EC 362 Problem Set #2 EC 362 Problem Set #2 1) Using Single Precision IEEE 754, what is FF28 0000? 2) Suppose the fraction enhanced of a processor is 40% and the speedup of the enhancement was tenfold. What is the overall speedup?

More information

PART B QUESTIONS AND ANSWERS UNIT I

PART B QUESTIONS AND ANSWERS UNIT I PART B QUESTIONS AND ANSWERS UNIT I 1. Explain the architecture of 8085 microprocessor? Logic pin out of 8085 microprocessor Address bus: unidirectional bus, used as high order bus Data bus: bi-directional

More information

1 Classical Universal Computer 3

1 Classical Universal Computer 3 Chapter 6: Machine Language and Assembler Christian Jacob 1 Classical Universal Computer 3 1.1 Von Neumann Architecture 3 1.2 CPU and RAM 5 1.3 Arithmetic Logical Unit (ALU) 6 1.4 Arithmetic Logical Unit

More information

More on Pipelining and Pipelines in Real Machines CS 333 Fall 2006 Main Ideas Data Hazards RAW WAR WAW More pipeline stall reduction techniques Branch prediction» static» dynamic bimodal branch prediction

More information

Central Processing Unit Simulation Version v2.5 (July 2005) Charles André University Nice-Sophia Antipolis

Central Processing Unit Simulation Version v2.5 (July 2005) Charles André University Nice-Sophia Antipolis Central Processing Unit Simulation Version v2.5 (July 2005) Charles André University Nice-Sophia Antipolis 1 1 Table of Contents 1 Table of Contents... 3 2 Overview... 5 3 Installation... 7 4 The CPU

More information

Lecture: Pipelining Extensions. Topics: control hazards, multi-cycle instructions, pipelining equations

Lecture: Pipelining Extensions. Topics: control hazards, multi-cycle instructions, pipelining equations Lecture: Pipelining Extensions Topics: control hazards, multi-cycle instructions, pipelining equations 1 Problem 6 Show the instruction occupying each stage in each cycle (with bypassing) if I1 is R1+R2

More information

Central Processing Unit

Central Processing Unit Chapter 4 Central Processing Unit 1. CPU organization and operation flowchart 1.1. General concepts The primary function of the Central Processing Unit is to execute sequences of instructions representing

More information

l C-Programming l A real computer language l Data Representation l Everything goes down to bits and bytes l Machine representation Language

l C-Programming l A real computer language l Data Representation l Everything goes down to bits and bytes l Machine representation Language 198:211 Computer Architecture Topics: Processor Design Where are we now? C-Programming A real computer language Data Representation Everything goes down to bits and bytes Machine representation Language

More information

A s we saw in Chapter 4, a CPU contains three main sections: the register section,

A s we saw in Chapter 4, a CPU contains three main sections: the register section, 6 CPU Design A s we saw in Chapter 4, a CPU contains three main sections: the register section, the arithmetic/logic unit (ALU), and the control unit. These sections work together to perform the sequences

More information

Let s put together a Manual Processor

Let s put together a Manual Processor Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce

More information

Z80 Microprocessors Z80 CPU. User Manual UM008006-0714. Copyright 2014 Zilog, Inc. All rights reserved. www.zilog.com

Z80 Microprocessors Z80 CPU. User Manual UM008006-0714. Copyright 2014 Zilog, Inc. All rights reserved. www.zilog.com Z80 Microprocessors Z80 CPU UM008006-0714 Copyright 2014 Zilog, Inc. All rights reserved. www.zilog.com ii Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG S PRODUCTS

More information

8085 INSTRUCTION SET

8085 INSTRUCTION SET DATA TRANSFER INSTRUCTIONS Opcode Operand Description 8085 INSTRUCTION SET INSTRUCTION DETAILS Copy from source to destination OV Rd, Rs This instruction copies the contents of the source, Rs register

More information

CHAPTER 4 MARIE: An Introduction to a Simple Computer

CHAPTER 4 MARIE: An Introduction to a Simple Computer CHAPTER 4 MARIE: An Introduction to a Simple Computer 4.1 Introduction 195 4.2 CPU Basics and Organization 195 4.2.1 The Registers 196 4.2.2 The ALU 197 4.2.3 The Control Unit 197 4.3 The Bus 197 4.4 Clocks

More information

Pipelining Review and Its Limitations

Pipelining Review and Its Limitations Pipelining Review and Its Limitations Yuri Baida yuri.baida@gmail.com yuriy.v.baida@intel.com October 16, 2010 Moscow Institute of Physics and Technology Agenda Review Instruction set architecture Basic

More information

Introduction. Application Security. Reasons For Reverse Engineering. This lecture. Java Byte Code

Introduction. Application Security. Reasons For Reverse Engineering. This lecture. Java Byte Code Introduction Application Security Tom Chothia Computer Security, Lecture 16 Compiled code is really just data which can be edit and inspected. By examining low level code protections can be removed and

More information

INSTRUCTION LEVEL PARALLELISM PART VII: REORDER BUFFER

INSTRUCTION LEVEL PARALLELISM PART VII: REORDER BUFFER Course on: Advanced Computer Architectures INSTRUCTION LEVEL PARALLELISM PART VII: REORDER BUFFER Prof. Cristina Silvano Politecnico di Milano cristina.silvano@polimi.it Prof. Silvano, Politecnico di Milano

More information

Addressing The problem. When & Where do we encounter Data? The concept of addressing data' in computations. The implications for our machine design(s)

Addressing The problem. When & Where do we encounter Data? The concept of addressing data' in computations. The implications for our machine design(s) Addressing The problem Objectives:- When & Where do we encounter Data? The concept of addressing data' in computations The implications for our machine design(s) Introducing the stack-machine concept Slide

More information

İSTANBUL AYDIN UNIVERSITY

İSTANBUL AYDIN UNIVERSITY İSTANBUL AYDIN UNIVERSITY FACULTY OF ENGİNEERİNG SOFTWARE ENGINEERING THE PROJECT OF THE INSTRUCTION SET COMPUTER ORGANIZATION GÖZDE ARAS B1205.090015 Instructor: Prof. Dr. HASAN HÜSEYİN BALIK DECEMBER

More information

CSC 8505 Handout : JVM & Jasmin

CSC 8505 Handout : JVM & Jasmin CSC 8505 Handout : JVM & Jasmin Note: This handout provides you with the basic information about JVM. Although we tried to be accurate about the description, there may be errors. Feel free to check your

More information

CS:APP Chapter 4 Computer Architecture. Wrap-Up. William J. Taffe Plymouth State University. using the slides of

CS:APP Chapter 4 Computer Architecture. Wrap-Up. William J. Taffe Plymouth State University. using the slides of CS:APP Chapter 4 Computer Architecture Wrap-Up William J. Taffe Plymouth State University using the slides of Randal E. Bryant Carnegie Mellon University Overview Wrap-Up of PIPE Design Performance analysis

More information

Instruction Folding in a Hardware-Translation Based Java Virtual Machine

Instruction Folding in a Hardware-Translation Based Java Virtual Machine Journal of Instruction-Level Parallelism 10 (2008) 1-16 Submitted 8/06; published 6/08 Instruction Folding in a Hardware-Translation Based Java Virtual Machine Hitoshi Oi Department of Computer Science

More information

Summary of the MARIE Assembly Language

Summary of the MARIE Assembly Language Supplement for Assignment # (sections.8 -. of the textbook) Summary of the MARIE Assembly Language Type of Instructions Arithmetic Data Transfer I/O Branch Subroutine call and return Mnemonic ADD X SUBT

More information

EE282 Computer Architecture and Organization Midterm Exam February 13, 2001. (Total Time = 120 minutes, Total Points = 100)

EE282 Computer Architecture and Organization Midterm Exam February 13, 2001. (Total Time = 120 minutes, Total Points = 100) EE282 Computer Architecture and Organization Midterm Exam February 13, 2001 (Total Time = 120 minutes, Total Points = 100) Name: (please print) Wolfe - Solution In recognition of and in the spirit of the

More information

The ARM Architecture. With a focus on v7a and Cortex-A8

The ARM Architecture. With a focus on v7a and Cortex-A8 The ARM Architecture With a focus on v7a and Cortex-A8 1 Agenda Introduction to ARM Ltd ARM Processors Overview ARM v7a Architecture/Programmers Model Cortex-A8 Memory Management Cortex-A8 Pipeline 2 ARM

More information

a storage location directly on the CPU, used for temporary storage of small amounts of data during processing.

a storage location directly on the CPU, used for temporary storage of small amounts of data during processing. CS143 Handout 18 Summer 2008 30 July, 2008 Processor Architectures Handout written by Maggie Johnson and revised by Julie Zelenski. Architecture Vocabulary Let s review a few relevant hardware definitions:

More information

CS412/CS413. Introduction to Compilers Tim Teitelbaum. Lecture 20: Stack Frames 7 March 08

CS412/CS413. Introduction to Compilers Tim Teitelbaum. Lecture 20: Stack Frames 7 March 08 CS412/CS413 Introduction to Compilers Tim Teitelbaum Lecture 20: Stack Frames 7 March 08 CS 412/413 Spring 2008 Introduction to Compilers 1 Where We Are Source code if (b == 0) a = b; Low-level IR code

More information

Giving credit where credit is due

Giving credit where credit is due CSCE 230J Computer Organization Processor Architecture VI: Wrap-Up Dr. Steve Goddard goddard@cse.unl.edu http://cse.unl.edu/~goddard/courses/csce230j Giving credit where credit is due ost of slides for

More information

University of Twente. A simulation of the Java Virtual Machine using graph grammars

University of Twente. A simulation of the Java Virtual Machine using graph grammars University of Twente Department of Computer Science A simulation of the Java Virtual Machine using graph grammars Master of Science thesis M. R. Arends, November 2003 A simulation of the Java Virtual Machine

More information

Section 44. CPU with Extended Data Space (EDS)

Section 44. CPU with Extended Data Space (EDS) Section 44. CPU with Extended Data Space (EDS) HIGHLIGHTS This section of the manual contains the following topics: 44.1 Introduction... 44-2 44.2 Programmer s Model... 44-5 44.3 Software Stack Pointer...

More information

MICROPROCESSOR BCA IV Sem MULTIPLE CHOICE QUESTIONS

MICROPROCESSOR BCA IV Sem MULTIPLE CHOICE QUESTIONS MICROPROCESSOR BCA IV Sem MULTIPLE CHOICE QUESTIONS 1) Which is the microprocessor comprises: a. Register section b. One or more ALU c. Control unit 2) What is the store by register? a. data b. operands

More information

Instruction Set Design

Instruction Set Design Instruction Set Design Instruction Set Architecture: to what purpose? ISA provides the level of abstraction between the software and the hardware One of the most important abstraction in CS It s narrow,

More information

A Microprogramming Animation

A Microprogramming Animation A Microprogramming Animation Steven Robbins and Kay A. Robbins!"## Division of Computer Science The University of Texas at San Antonio San Antonio, TX 78249 Submitted: December 23, 1994 Last Revision:

More information

Computer System: User s View. Computer System Components: High Level View. Input. Output. Computer. Computer System: Motherboard Level

Computer System: User s View. Computer System Components: High Level View. Input. Output. Computer. Computer System: Motherboard Level System: User s View System Components: High Level View Input Output 1 System: Motherboard Level 2 Components: Interconnection I/O MEMORY 3 4 Organization Registers ALU CU 5 6 1 Input/Output I/O MEMORY

More information

Administrative Issues

Administrative Issues CSC 3210 Computer Organization and Programming Introduction and Overview Dr. Anu Bourgeois (modified by Yuan Long) Administrative Issues Required Prerequisites CSc 2010 Intro to CSc CSc 2310 Java Programming

More information

Computer Organization. and Instruction Execution. August 22

Computer Organization. and Instruction Execution. August 22 Computer Organization and Instruction Execution August 22 CSC201 Section 002 Fall, 2000 The Main Parts of a Computer CSC201 Section Copyright 2000, Douglas Reeves 2 I/O and Storage Devices (lots of devices,

More information

612 CHAPTER 11 PROCESSOR FAMILIES (Corrisponde al cap. 12 - Famiglie di processori) PROBLEMS

612 CHAPTER 11 PROCESSOR FAMILIES (Corrisponde al cap. 12 - Famiglie di processori) PROBLEMS 612 CHAPTER 11 PROCESSOR FAMILIES (Corrisponde al cap. 12 - Famiglie di processori) PROBLEMS 11.1 How is conditional execution of ARM instructions (see Part I of Chapter 3) related to predicated execution

More information

Network Traffic Monitoring an architecture using associative processing.

Network Traffic Monitoring an architecture using associative processing. Network Traffic Monitoring an architecture using associative processing. Gerald Tripp Technical Report: 7-99 Computing Laboratory, University of Kent 1 st September 1999 Abstract This paper investigates

More information

Pipeline Hazards. Structure hazard Data hazard. ComputerArchitecture_PipelineHazard1

Pipeline Hazards. Structure hazard Data hazard. ComputerArchitecture_PipelineHazard1 Pipeline Hazards Structure hazard Data hazard Pipeline hazard: the major hurdle A hazard is a condition that prevents an instruction in the pipe from executing its next scheduled pipe stage Taxonomy of

More information

Inside the Java Virtual Machine

Inside the Java Virtual Machine CS1Bh Practical 2 Inside the Java Virtual Machine This is an individual practical exercise which requires you to submit some files electronically. A system which measures software similarity will be used

More information

Operating System Overview. Otto J. Anshus

Operating System Overview. Otto J. Anshus Operating System Overview Otto J. Anshus A Typical Computer CPU... CPU Memory Chipset I/O bus ROM Keyboard Network A Typical Computer System CPU. CPU Memory Application(s) Operating System ROM OS Apps

More information

Introduction to Microcoded Implementation of a CPU Architecture

Introduction to Microcoded Implementation of a CPU Architecture Introduction to Microcoded Implementation of a CPU Architecture N.S. Matloff, revised by D. Franklin January 30, 1999, revised March 2004 1 Microcoding Throughout the years, Microcoding has changed dramatically.

More information

Microprocessor and Microcontroller Architecture

Microprocessor and Microcontroller Architecture Microprocessor and Microcontroller Architecture 1 Von Neumann Architecture Stored-Program Digital Computer Digital computation in ALU Programmable via set of standard instructions input memory output Internal

More information

Levels of Programming Languages. Gerald Penn CSC 324

Levels of Programming Languages. Gerald Penn CSC 324 Levels of Programming Languages Gerald Penn CSC 324 Levels of Programming Language Microcode Machine code Assembly Language Low-level Programming Language High-level Programming Language Levels of Programming

More information

Chapter 2 Logic Gates and Introduction to Computer Architecture

Chapter 2 Logic Gates and Introduction to Computer Architecture Chapter 2 Logic Gates and Introduction to Computer Architecture 2.1 Introduction The basic components of an Integrated Circuit (IC) is logic gates which made of transistors, in digital system there are

More information

Stack machines The MIPS assembly language A simple source language Stack-machine implementation of the simple language Readings: 9.1-9.

Stack machines The MIPS assembly language A simple source language Stack-machine implementation of the simple language Readings: 9.1-9. Code Generation I Stack machines The MIPS assembly language A simple source language Stack-machine implementation of the simple language Readings: 9.1-9.7 Stack Machines A simple evaluation model No variables

More information

Solutions. Solution 4.1. 4.1.1 The values of the signals are as follows:

Solutions. Solution 4.1. 4.1.1 The values of the signals are as follows: 4 Solutions Solution 4.1 4.1.1 The values of the signals are as follows: RegWrite MemRead ALUMux MemWrite ALUOp RegMux Branch a. 1 0 0 (Reg) 0 Add 1 (ALU) 0 b. 1 1 1 (Imm) 0 Add 1 (Mem) 0 ALUMux is the

More information

Chapter 11 I/O Management and Disk Scheduling

Chapter 11 I/O Management and Disk Scheduling Operating Systems: Internals and Design Principles, 6/E William Stallings Chapter 11 I/O Management and Disk Scheduling Dave Bremer Otago Polytechnic, NZ 2008, Prentice Hall I/O Devices Roadmap Organization

More information

A Lab Course on Computer Architecture

A Lab Course on Computer Architecture A Lab Course on Computer Architecture Pedro López José Duato Depto. de Informática de Sistemas y Computadores Facultad de Informática Universidad Politécnica de Valencia Camino de Vera s/n, 46071 - Valencia,

More information

Java Programming. Binnur Kurt binnur.kurt@ieee.org. Istanbul Technical University Computer Engineering Department. Java Programming. Version 0.0.

Java Programming. Binnur Kurt binnur.kurt@ieee.org. Istanbul Technical University Computer Engineering Department. Java Programming. Version 0.0. Java Programming Binnur Kurt binnur.kurt@ieee.org Istanbul Technical University Computer Engineering Department Java Programming 1 Version 0.0.4 About the Lecturer BSc İTÜ, Computer Engineering Department,

More information