SP720 Lead-free/Green

Transcription

1 TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP0 Leadfree/Green The SP0 is an array of SCR/Diode bipolar structures for ESD and overvoltage protection to sensitive input circuits. The SP0 has protection SCR/Diode device structures per input. A total of 4 available inputs can be used to protect up to 4 external signal or bus lines. Overvoltage protection is from the (pins and 9) to V+ or V. The SCR structures are designed for fast triggering at a threshold of one +V BE diode threshold above V+ (Pin ) or a V BE diode threshold below V (Pin ). From an input, a clamp to V+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one V BE above V+. A similar clamp to V is activated if a negative pulse, one V BE less than V, is applied to an input. Standard ESD Human Body Model (HBM) Capability is: HBM STANDARD MODE R C ESD (V) IEC 0004 Air 330Ω 0pF >kv Refer to Figure and Table for further detail. Refer to Application Note AN9304 and AN9 for additional information. Ordering Information Direct 330Ω 0pF >4kV Direct, Dual Pins 330Ω 0pF >kv MILSTD30. Direct, Incircuit.kΩ 00pF >kv TEMP. RANGE ENVIRONMENTAL Min. PART NO. ( o C) PACKAGE FORMATON MARKG Order SP0APP 40 to 0 Ld PDIP Leadfree 0APP 00 Features ESD Interface Capability for HBM Standards MIL STD kv IEC 0004, Direct Discharge, Single Input kV (Level ) Two Inputs in Parallel kv (Level 4) IEC 0004, Air Discharge kv (Level 4) High Peak Current Capability IEC 0004 (/0µs) ±3A Single Pulse, 00µs Pulse Width ±A Single Pulse, 4µs Pulse Width ±A Designed to Provide OverVoltage Protection SingleEnded Voltage Range to V Differential Voltage Range to ±V SP0ABG 40 to 0 Ld SOIC Green 0ABG SP0ABTG 40 to 0 Ld SOIC Green 0ABG Tape and Reel Fast Switching ns Risetime Low Input Leakages na at o C (Typ) Low Input Capacitance pF (Typ) An Array of 4 SCR/Diode Pairs Pinout SP0 (PDIP, SOIC) TOP VIEW V Operating Temperature Range o C to 0 o C Applications Microprocessor/Logic Input Protection Data Bus Protection Analog Device Input Protection Voltage Clamp Functional Block Diagram V+ 0 V V

2 Electronic Protection Array for ESD and Overvoltage Protection SP0 LeadFree/Green Absolute Maximum Ratings Continuous Supply Voltage, (V+) (V) V Forward Peak Current, I to V CC, I to GND (Refer to Figure )....±A, 00µs ESD Ratings and Capability (Figure, Table ) Load Dump and Reverse Battery (Note ) Thermal Information Thermal Resistance (Typical, Note ).... JA ( o C/W) PDIP Package SOIC Package Maximum Storage Temperature Range o C to 0 o C Maximum Junction Temperature (Plastic Package)....0 o C Maximum Lead Temperature (Soldering 0s) o C (SOIC Lead Tips Only) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications T A = 40 o C to 0 o C; V = 0.V CC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS M TYP MAX UNITS Operating Voltage Range, V SUPPLY to 30 V V SUPPLY = [(V+) (V)] Forward Voltage Drop: I = A (Peak Pulse) to V to V+ V FWDL V FWDH V V Input Leakage Current I 0 0 na Quiescent Supply Current I QUIESCENT 0 00 na Equivalent SCR ON Threshold Note 3. V Equivalent SCR ON Resistance V FWD /I FWD ; Note 3 Ω Input Capacitance C 3 pf Input Switching Speed t ON ns NOTES:. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the V+ and V pins are connected to the same supply voltage source as the device or control line under protection, a current limiting resistor should be connected in series between the external supply and the SP0 supply pins to limit reverse battery current to within the rated maximum limits. Bypass capacitors of typically 0.0µF or larger from the V+ and V pins to ground are recommended. 3. Refer to the Figure 3 graph for definitions of equivalent SCR ON Threshold and SCR ON Resistance. These characteristics are given here for thumbrule information to determine peak current and dissipation under EOS conditions. ESD Capability ESD capability is dependent on the application and defined test standard. The evaluation results for various test standards and methods based on Figure are shown in Table. For the Modified MILSTD30. condition that is defined as an incircuit method of ESD testing, the V+ and V pins have a return path to ground and the SP0 ESD capability is typically greater than kv from 00pF through.kω. By strict definition of MILSTD30. using pintopin device testing, the ESD voltage capability is greater than kv. The MILSTD30. results were determined from AT&T ESD Test Lab measurements. The HBM capability to the IEC 0004 standard is greater than kv for air discharge (Level 4) and greater than 4kV for direct discharge (Level ). Dual pin capability ( adjacent pins in parallel) is well in excess of kv (Level 4). For ESD testing of the SP0 to EIAJ IC Machine Model (MM) standard, the results are typically better than kv from 00pF with no series resistance. TABLE. ESD TEST CONDITIONS STANDARD TYPE/MODE R D C D ±V D MIL STD 30. Modified HBM.kΩ 00pF kv Standard HBM.kΩ 00pF kv IEC 0004 HBM, Air Discharge 330Ω 0pF kv HBM, Direct Discharge 330Ω 0pF 4kV HBM, Direct Discharge, 330Ω 0pF kv Two Parallel Input Pins EIAJ IC Machine Model 0kΩ 00pF kv H.V. SUPPLY ±V D CHARGE SWITCH R C D R D DISCHARGE SWITCH IEC 0004: R 0 to 00MΩ MIL STD 30.: R to 0MΩ DUT TVS DIODE ARRAYS FIGURE. ELECTROSTATIC DISCHARGE TEST 3

3 TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP0 LeadFree/Green 00 T A = o C SGLE PULSE. T A = o C SGLE PULSE 0 FORWARD SCR CURRENT (ma) FORWARD SCR CURRENT (A). 0. EQUIV. SAT. ON THRESHOLD ~.V V FWD I FWD FORWARD SCR VOLTAGE DROP (mv) FIGURE. LOW CURRENT SCR FORWARD VOLTAGE DROP CURVE FORWARD SCR VOLTAGE DROP (V) FIGURE 3. HIGH CURRENT SCR FORWARD VOLTAGE DROP CURVE +V CC +V CC PUT DRIVERS OR SIGNAL SOURCES LEAR OR DIGITAL IC TERFACE 9 TO +V CC V+ SP0 V SP0 PUT PROTECTION CIRCUIT ( OF 4 ON CHIP) FIGURE 4. TYPICAL APPLICATION OF THE SP0 AS AN PUT CLAMP FOR OVERVOLTAGE, GREATER THAN V BE ABOVE V+ OR LESS THAN V BE BELOW V 4

4 Electronic Protection Array for ESD and Overvoltage Protection SP0 LeadFree/Green Peak Transient Current Capability of the SP0 The peak transient current capability rises sharply as the width of the current pulse narrows. Destructive testing was done to fully evaluate the SP0 s ability to withstand a wide range of transient current pulses. The circuit used to generate current pulses is shown in Figure. The test circuit of Figure is shown with a positive pulse input. For a negative pulse input, the () current pulse input goes to an SP0 input pin and the (+) current pulse input goes to the SP0 V pin. The V+ to V supply of the SP0 must be allowed to float. (i.e., It is not tied to the ground reference of the current pulse generator.) Figure shows the point of overstress as defined by increased leakage in excess of the data sheet published limits. The maximum peak input current capability is dependent on the V+ to V voltage supply level, improving as the supply voltage is reduced. Values of 0,, and 30 voltages are shown. The safe operating range of the transient peak current should be limited to no more than % of the measured overstress level for any given pulse width as shown in Figure. When adjacent input pins are paralleled, the sustained peak current capability is increased to nearly twice that of a single pin. For comparison, tests were run using dual pin combinations +, 3+4, +, +9, 0+, +3 and The overstress curve is shown in Figure for a V supply condition. The dual pins are capable of 0A peak current for a 0µs pulse and 4A peak current for a ms pulse. The complete for single pulse peak current vs. pulse width time ranging up to second are shown in Figure. + V G R VOLTAGE PROBE R ~ 0Ω TYPICAL V G ADJ. 0V/A TYPICAL C ~ 00µF (+) VARIABLE TIME DURATION CURRENT PULSE GENERATOR CURRENT SENSE 3 4 V V+ 4 3 SP0 0 9 FIGURE. TYPICAL SP0 PEAK CURRENT TEST CIRCUIT WITH A VARIABLE PULSE WIDTH PUT () C + TVS DIODE ARRAYS PEAK CURRENT (A) 4 CAUTION: SAFE OPERATG CONDITIONS LIMIT THE MAXIMUM PEAK CURRENT FOR A GIVEN PULSE WIDTH TO BE NO GREATER THAN % OF THE VALUES SHOWN ON EACH CURVE. SGLE P STRESS CURVES DUAL P STRESS CURVE 3 0V V 30V V V V+ TO V SUPPLY PULSE WIDTH TIME (ms) FIGURE. SP0 TYPICAL SGLE PULSE PEAK CURRENT CURVES SHOWG THE MEASURED POT OF OVERSTRESS AMPERES vs PULSE TIME MILLISECONDS (T A = o C)

5 TVS Diode Arrays Electronic Protection Array for ESD and Overvoltage Protection SP0 LeadFree/Green DualInLine Plastic Packages (PDIP) DEX AREA BASE PLANE SEATG PLANE D B C A N 3 N/ B D e D E NOTES:. Controlling Dimensions: CH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y4.M9. 3. Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A and L are measured with the package seated in JE DEC seating plane gauge GS3.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.00 inch (0.mm).. E and e A are measured with the leads constrained to be perpendicular to datum C.. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.00 inch (0.mm). 9. N is the maximum number of terminal positions. 0. Corner leads (, N, N/ and N/ + ) for E.3, E.3, E.3, E.3, E4. will have a B dimension of inch (0..4mm). B A 0.00 (0.) M C A A L B S A e C E C L e A C e B E.3 (JEDEC MS00 BB ISSUE D) LEAD DUALLE PLASTIC PACKAGE CHES MILLIMETERS SYMBOL M MAX M MAX NOTES A A A B B , 0 C D D E E e 0.00 BSC.4 BSC e A BSC. BSC e B L N 9

6 Electronic Protection Array for ESD and Overvoltage Protection SP0 LeadFree/Green Small Outline Plastic Packages (SOIC) M. (JEDEC MS0AC ISSUE C) N DEX AREA 3 e D B 0.(0.00) M C A M E B A C A B S H SEATG PLANE A NOTES:. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y4.M9. 3. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.mm (0.00 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.mm (0.00 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.. L is the length of terminal for soldering to a substrate.. N is the number of terminal positions.. Terminal numbers are shown for reference only. 9. The lead width B, as measured 0.3mm (0.04 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.04 inch). 0. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. µ 0.(0.00) M B 0.0(0.004) L M h x 4 o C LEAD NARROW BODY SMALL OUTLE PLASTIC PACKAGE CHES MILLIMETERS SYMBOL M MAX M MAX NOTES A A B C D E e 0.00 BSC. BSC H h L N µ 0 o o 0 o o TVS DIODE ARRAYS