HA Features. 600MHz, Very High Slew Rate Operational Amplifier. Applications. Pinout. Part Number Information. Data Sheet May 2003 FN2896.

Transcription

1 NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1--INTERSIL or HA-2539 Data Sheet May 23 FN MHz, Very High Slew Rate Operational Amplifier The Intersil HA-2539 represents the ultimate in high slew rate, wideband, monolithic operational amplifiers. It has been designed and constructed with the Intersil High Frequency Bipolar Dielectric Isolation process and features dynamic parameters never before available from a truly differential device. With a 6V/ s slew rate and a 6MHz gain bandwidth product, the HA-2539 is ideally suited for use in video and RF amplifier designs, in closed loop gains of 1 or greater. Full 1V swing coupled with outstanding AC parameters and complemented by high open loop gain makes the devices useful in high speed data acquisition systems. For further design assistance please refer to Application Note AN51 (Using the HA-2539 Very High Slew Rate Wideband Operational Amplifiers) and Application Note AN556 (Thermal Safe-Operating-Areas For High Current Operational Amplifiers. For military grade product information, the HA-2539/3 data sheet is available upon request. Part Number Information Features Very High Slew Rate V/ s Open Loop Gain kV/V Wide Gain-Bandwidth (A V 1) MHz Power Bandwidth MHz Low Offset Voltage mv Input Voltage Noise nV/ Hz Output Voltage Swing V Monolithic Bipolar Dielectric Construction Applications Pulse and Video Amplifiers Wideband Amplifiers High Speed Sample-Hold Circuits RF Oscillators Pinout HA-2539 (PDIP) TOP VIEW PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. HA to 75 1 Ld PDIP E1.3 +IN IN V OUTPUT NOTE: No-Connection () leads may be tied to a ground plane for better isolation and heat dissipation. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1--INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 23. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 Absolute Maximum Ratings Supply Voltage Between V+ and Terminals V Differential Input Voltage V Peak Output Current mA Continuous Output Current mA RMS Operating Conditions Temperature Range HA o C to 75 o C Thermal Information Thermal Resistance (Typical, Note 2) JA ( o C/W) JC ( o C/W) PDIP Package N/A Maximum Internal Quiescent Power Dissipation (Note 1) Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 15 o C Maximum Lead Temperature (Soldering 1s) o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation with load conditions must be designed to maintain the maximum junction temperature below 15 o C for the plastic package. By using Application Note AN556 on Safe Operating Area equations, along with the thermal resistances, proper load conditions can be determined. Heat sinking is recommended above 75 o C. 2. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications V SUPPLY = ±15V, R L = 1kW, C L < 1pF, Unless Otherwise Specified PARAMETER TEMP. ( o C) MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage mv Full mv Average Offset Voltage Drift Full V/ o C Bias Current A Full A Offset Current A Full - - A Input Resistance k Input Capacitance pf Common Mode Range Full V Input Current Noise (f = 1kHz, R SOURCE = ) Input Voltage Noise (f = 1kHz, R SOURCE = ) pa/ Hz nv/ Hz TRANSFER CHARACTERISTICS Large Signal Voltage Gain (Note 3) Common Mode Rejection Ratio (Note ) kv/v Full kv/v Full db Minimum Stable Gain V/V Gain Bandwidth (Notes 5, 6) MHz 2

3 Electrical Specifications V SUPPLY = ±15V, R L = 1kW, C L < 1pF, Unless Otherwise Specified (Continued) PARAMETER TEMP. ( o C) MIN TYP MAX UNITS OUTPUT CHARACTERISTICS Output Voltage Swing (Notes 3, 1) Full V Output Current (Note 3) ma Output Resistance Full Power Bandwidth (Notes 3, 7) MHz TRANSIENT RESPONSE (Note ) Rise Time ns Overshoot % Slew Rate V/ s Settling Time: 1V Step to.1% ns POWER REQUIREMENTS Supply Current Full ma Power Supply Rejection Ratio (Note 9) Full db NOTES: 3. R L = 1k, V O = 1V.. V CM = 1.V. 5. V O = 9mV. 6. A V = 1. Slew Rate 7. Full Power Bandwidth guaranteed based on slew rate measurement using: FPBW = V. Refer to Test Circuits section of data sheet. PEAK 9. V SUPPLY = 5V, -15V and +15V, -5V. 1. Guaranteed range for output voltage is 1V. Functional operation outside of this range is not guaranteed. 3

4 Test Circuits and Waveforms IN OUT NOTES: 11. V S = 15V. 12. A V = C L 1pF. FIGURE 1. TEST CIRCUIT A B Vertical Scale: A =.5V/Div., B = 5.V/Div. Horizontal Scale: 5ns/Div. Vertical Scale: Input = 1mV/Div., Output = 5mV/Div. Horizontal Scale: 2ns/Div. FIGURE 2. LARGE SIGNAL RESPONSE FIGURE 3. SMALL SIGNAL RESPONSE INPUT 2 5 V F 1 F.1 F 1 F 2k OUTPUT <1pF PROBE MONITOR NOTES: 1. A V = Load Capacitance should be less than 1pF. 16. It is recommended that resistors be carbon composition and that feedback and summing network ratios be matched to.1%. 17. SETTLE POINT (Summing Node) capacitance should be less than 1pF. For optimum settling time results, it is recommended that the test circuit be constructed directly onto the device pins. A Tektronix 56 Sampling Oscilloscope with S-3A sampling heads is recommended as a settle point monitor. SETTLE POINT 5k FIGURE. SETTLING TIME CIRCUIT

5 Schematic Diagram V+ R 23 R 1 R 2 Q P2 R 3 Q P1 R Q P22 Q P6 Q P19 R 13 Q P17 R 5 R 2 Q P5 Q P25 R 22 Q N1 Q N2 C 1 R +INPUT R 6 R 7 Q N7 Q N9 Q P23 QN21 R R9 Q P R 1 OUTPUT Q P3 Q P Q N1 R 19 -INPUT R 21 V+ Q P11 Z 1 Q N25 Q N12 R 25 V+ Q N2 R 1 Q N15 R 16 D Z1 Q N1 Q N13 Q N16 D Z2 R11 R 12 Q N29 R 1 R 15 R 17 5

6 Typical Applications 2-1pF HA-2539 SET A V = 1+ R 1 R 2 = 5 R 1 R 2 R R 2 SET A V = = -3 R 2 R1 Z IN FIGURE 5. FREQUEY COMPENSATION BY OVERDAMPING FIGURE 6. STABILIZATION USING Z IN R 5 1k R 1k INPUT R 1 1k 39pF C 1 C 2 R 2.39 F 1k HA R 1k HA OUTPUT FIGURE 7. REDUCING DC ERRORS; COMPOSITE AMPLIFIER FIGURE. DIFFERENTIAL GAIN ERROR (3%) HA dB VIDEO GAIN BLOCK Typical Performance Curves R SOURCE = V S = 15V 5 INPUT BIAS CURRENT ( A) OFFSET VOLTAGE BIAS CURRENT V IO OFFSET VOLTAGE (mv) NOISE VOLTAGE (nv/ Hz) VOLTAGE NOISE CURRENT NOISE NOISE CURRENT (pa/ Hz) TEMPERATURE ( o C) FIGURE 9. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs TEMPERATURE 1 1 1K 1K 1K FREQUEY (Hz) FIGURE 1. INPUT NOISE VOLTAGE AND NOISE CURRENT vs FREQUEY 6

7 Typical Performance Curves (Continued) + V +3 V +2 V +1 V V -1 V -2 V -3 V CMRR (db) V Vertical Scale: 1mV/Div. Horizontal Scale: 5ms/Div. 1K 1K 1K 1M 1M FREQUEY (Hz) FIGURE 11. BROADBAND NOISE (.1Hz TO 1MHz) FIGURE 12. COMMON MODE REJECTION RATIO vs FREQUEY 1 1 GAIN 6 PHASE 5 PSRR (db) 6 2 GAIN (db) PHASE (DEGREES) 1K 1K 1K 1M 1M FREQUEY (Hz) FIGURE 13. POWER SUPPLY REJECTION RATIO vs FREQUEY CLOSED LOOP GAIN (db) V S = 15V K 1K 1K 1M 1M 1M FREQUEY (Hz) FIGURE 15. CLOSED LOOP FREQUEY RESPONSE OUTPUT VOLTAGE (V P-P ) K 1K 1K 1M 1M 1M FREQUEY (Hz) FIGURE 1. OPEN LOOP GAIN/PHASE vs FREQUEY V S = 15V V S = 1V V S = 5V 1K 1K 1K 1M 1M 1M FREQUEY (Hz) FIGURE 16. OUTPUT VOLTAGE SWING vs FREQUEY 7

8 Typical Performance Curves (Continued) 1. OUTPUT VOLTAGE SWING (V P-P ) K 1.2K RESISTAE ( ) NORMALIZED PARAMETERS REFERRED TO VALUES AT 25 o C BANDWIDTH SLEW RATE TEMPERATURE ( o C) FIGURE 17. OUTPUT VOLTAGE SWING vs LOAD RESISTAE FIGURE 1. NORMALIZED AC PARAMETERS vs TEMPERATURE 2 OUTPUT VOLTAGE STEP (V) mV 1mV 1mV 1mV SUPPLY CURRENT (ma) V S = 15V V S = 5V SETTLING TIME (ns) FIGURE 19. SETTLING TIME FOR VARIOUS OUTPUT STEP VOLTAGES TEMPERATURE ( o C) FIGURE 2. POWER SUPPLY CURRENT vs TEMPERATURE

9 Die Characteristics DIE DIMENSIONS: 62 mils x 76 mils x 19 mils 1575 m x 193 m x 3 m METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ 2kÅ PASSIVATION: Type: Nitride (Si 3 N ) over Silox (SiO 2, 5% Phos.) Silox Thickness: 12kÅ 2kÅ Nitride Thickness: 3.5kÅ 1.5kÅ Metallization Mask Layout SUBSTRATE POTENTIAL (POWERED UP): TRANSISTOR COUNT: 3 PROCESS: Bipolar Dielectric Isolation +IN OUTPUT V+ -IN 9

10 Dual-In-Line Plastic Packages (PDIP) INDEX AREA BASE PLANE SEATING PLANE D1 B1 -C- -A- N N/2 B D e D1 E1 NOTES: 1. Controlling Dimensions: IH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y1.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed.1 inch (.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater.. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed.1 inch (.25mm). 9. N is the maximum number of terminal positions. 1. Corner leads (1, N, N/2 and N/2 + 1) for E.3, E16.3, E1.3, E2.3, E2.6 will have a B1 dimension of inch ( mm). -B- A1.1 (.25) M C A A2 L B S A e C E C L e A C e B E1.3 (JEDEC MS-1-AA ISSUE D) 1 LEAD DUAL-IN-LINE PLASTIC PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B C D D E E e.1 BSC 2.5 BSC - e A.3 BSC 7.62 BSC 6 e B L N Rev. 12/93 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO91 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 1