Darshan Institute of Engineering & Technology for Diploma Studies Unit - 2

Transcription

1 4. Draw and explain flowchart for instruction cycle. In a stored programmed concept computer data, the instructions are stored in main memory. Instructions & Data (operand) are read from the memory one by one starting from the beginning to the end of program. Temporary and final results are stored in the memory. Control unit undergoes a cycle for executing one instruction. This is known as instruction cycle. Four phases of instruction cycle:- 1. Fetching (Reading) the instruction code from the memory. 2. Decoding the instruction. 3. Second memory access to read the true address of operand if the address mode is indirect. (This phase is optional, called indirect phase). 4. Executing the instruction. The micro operation for the fetch & decode phase of the operation can be specified by RTL as: T0: AR PC (S0S1S2 = 010, T0 = 1) T1: IR M [AR], PC PC + 1 (S0S1S2 = 111, T1 = 1) T2: D0, D7 Decode IR (12-14), AR IR (0-11), I IR (15) Timing signal T3 is activated after the decoding. During time T3, the control unit determines the type of instruction that was read from memory. There are three type of instruction in the basic computer. 5 Dept CE COA( ) Jitendra Karia

2 Output D7 of decoder is equal to 1 if the operation code is 111, we determine that if D7 = 1, the instruction must be a register reference or I/O type. If D7 = 0, the operation code must be Memory Reference type. D 7IT3: AR M [AR], memory reference indirect addressing mode. D 7I T3: Nothing, memory reference direct addressing mode. D7I T3: Execute a register reference instruction. D7IT3: Execute an input-output reference instruction. If I = 0, instruction will be memory reference, then not necessary to do anything, the effective address is already in AR. The sequence counter SC must be incremented when D7 T3 = 1, so that the execution of memory reference can be continued with timing signal T4. A register reference or I/O reference instruction can be executed with clock timing signal T3. After that the sequence counter SC will clear to 0 and control returns to the next fetch phase with T0=1. 5. Draw and explain Control unit of basic computer. The block diagram below shows the control unit. Control unit has two decoders, a counter, and a number of control logic gates. An instruction read from memory is placed in the instruction register (IR). IR has three parts 1 bit for mode (15 bit), operation code (14-12 bit), and 0 to 11 positions for operation or address. The 8 outputs of decoder are D0 through D7, bit 15 of the instruction is transferred to flip-flop, symbol I. 0 to 11 bits applied to control logic gates. The outputs of four-bit counter are decoded into 16 timing signals T0 through T15. 6 Dept CE COA( ) Jitendra Karia

3 The timing diagram below shows the relationship of the control signals. The sequence counter SC activated at the positive transition of the clock. Initially the CLR input of SC is active. First transition of the clock clears SC to 0, which activates the timing signal T0 for one clock cycle. SC is incremented with every clock, unless its CLR input is active. This generates the sequence of timing signals T0, T1, T2, T3, and so on. If SC is not cleared, the timing signals ill continue with T5, T6,..., T15 and back to T0. The SC can be incremented or cleared Example: T0, T1, T2, T3, T4, T0, T1,... Assume: At time T4, SC is cleared to 0 if decoder output D3 is active. D3 T4: SC < Explain memory reference instruction & ADD LDA BUN instructions in detail. Fetching of all the instruction is common and it require three t-states T0 to T2 as already discussed before. After fetching the instruction it is executed in one, two or three T-states. Below table list the seven memory reference instructions. The decoded output Di for i = 0, 1, 2, 3, 4, and 6 from the operation decoder. The effective address of the instruction is in AR and was placed there during timing signal T2 when I = 0, during timing signal T3 when I = 1. Memory cycle is assumed to be short enough to complete in a CPU cycle. The execution of MR instruction starts with T4. The actual execution of the instruction in the bus system will require a sequence of micro operations. The data stored in memory cannot process directly. The data must read from memory to register where they can be operated on wit logic circuits. ADD (add with AC): D1 T4: DR <- M [AR] Read operand 7 Dept CE COA( ) Jitendra Karia

4 D1 T5: AC <- AC + DR, E <- COUT, SC <- 0 (Add to AC and store carry in E). This instruction performs the addition of content of AC with content of memory word specified by the effective address. The sum is transferred to AC and carry to the E flip-flop. LDA (load AC): D2 T4: DR<- M [AR] D2 T5: AC <- DR, SC <- 0 This instruction transfers the memory word specified by the effective address to the AC. The adder & logic circuit receive the information from DR which can be transferred to AC. Here first read the memory word into DR & then transfer the content of DR into AC. BUN (branch unconditionally): D4 T4: PC <- AR, SC <- 0 Transfer the program to the instruction specified by the effective address. PC holds the address of the instruction to be read from memory in the next instruction cycle. PC is incremented at time T1 to prepare for the address of the next instruction in the program sequence. It allows the user to specify an instruction out of sequence & jump unconditionally. It requires only one micro operation. The address from AR is transferred through the common bus to PC. And set SC to 0 transfer control to T0 & next instruction is then fetched & executed from the memory address at new value in PC. 8 Dept CE COA( ) Jitendra Karia

5 7. List types of computer instruction. Explain any one in detail. Instruction Types: 1. Functional Instructions: Arithmetic logic & shift instructions ADD, CMA, INC, CIR, CIL, AND, CLA 2. Transfer Instructions: Data transfers between the main memory and the processor registers LDA, STA 3. Control Instructions: Program sequencing & control BUN, BSA, ISZ 4. Input / Output Instructions: Input & Output In, Out Transfer Instructions: LDA (load AC): D2 T4: DR <- M [AR] D2 T5: AC <- DR, SC <- 0 This instruction transfers the memory word specified by the effective address to the AC. The adder & logic circuit receive the information from DR which can be transferred to AC. Here first read the memory word into DR & then transfer the content of DR into AC. STA (store to AC): D3 T4: M [AR] <- AC, SC <- 0 This instruction stores the content of AC into the memory word specified by the effective address. Here output of AC is put into bus & the data input of memory is connected to the bus. 8. Draw and explain flowchart for interrupt cycle. The interrupt enable flip-flop IEN can be set and cleared with two instructions. When IEN = 0, the flag cannot interrupt the computer. When IEN = 1, the computer can be interrupted. With these two options the programmer can make a decision as to whether or not to use the interrupt. With above flowchart we can see what actually happened when interrupt occurs. An interrupt flip-flop R is included in the computer. When R=0, the system goes through an instruction cycle. During execution phase of the instruction cycle IEN is checked by the control, if it is 0, it says that the programmer does not want to use the interrupt, so control goes with the next instruction cycle. If IEN = 1, control checks the flag bits, if both are 0, it means that the input and output register are not ready for transfer of information. In that case control continues with next cycle. If flag is set to 1 while IEN = 1, flip flop R is set to 1. At end of execute phase, control checks the value of R, if R=1, it goes to an interrupt cycle instead of an instruction cycle. The interrupt cycle is a H/W implementation of a branch and save return address operation. At the beginning of the next instruction cycle, the instruction that is read from memory is in address 1. At memory address 1, the programmer must store a branch instruction that sends the control to an interrupt service routine. The instruction that returns the control to the original program is indirect BUN 0. 9 Dept CE COA( ) Jitendra Karia

6 R flag can be set to 1 in ay of T-states T3 or T4 or T5 or T6. But CPU will enter into the interrupt cycle after execution of present instruction and when SC is cleared to 0. The condition of setting flag R to 1 can be expressed as : T0 T1 T2 (IEN) (FGI + FGO) (T3 + T4 + T5 + T6) : R 1 Interrupt cycle will be executed as follows: RT0: AR 0, TR PC RT1: M [AR] TR, PC 0 RT2: PC PC + 1, IEN 0, R 0, SC 0 10 Dept CE COA( ) Jitendra Karia