Designing a Single Cycle Datapath

Transcription

1 Designing a Single Cycle Datapath CPS 14 Lecture 12 cps 14 1 Outline of Today s Lecture Homework #4 Due Thursday MIPS Simulator due April 14 Second Mid-term end of March Reading Ch Where are we with respect to the BIG picture? The Steps of Designing a Processor Datapath and timing for Reg-Reg Operations Datapath for Logical Operations with Immediate Datapath for Load and Store Operations Datapath for Branch and Jump Operations cps 14 2

2 Review: Integer Multiplication & Division Multiplication Series of Shift and Add Booth s Algorithm (Current, Previous) bits of Multiplier:,: middle of string of s; do nothing,1: end of a string of 1s; add multiplicand 1,; start of string of 1s; subtract multiplicand 1,1: middle of string of 1s; do nothing Shift Product/Multiplier right 1 bit (as before) Division Series of Shift and Subtract cps 14 3 Review: FP Addition Example: 161 x x 1 1 Step 1: Align decimal point: x x 1 1 Step 2: Add: 115 x 1 1 Step 3: Normalize: 115 x 1 2 Step 4: Round: 12 x 1 2 May need to repeat steps 3 and 4 if result not normal after rounding (renormalization) cps 14 4

3 Review: FP Multiplication 1 Add biased exponents, subtract bias 2 Multiply significands 3 Normalize product 4 Round significand 5 Compute sign of product 5 x -75 => 1x2-1 x 11x2-2 cps 14 5 Review: Rounding Rounding with Guard & Round bits Example: 256 x x 1 2, using 3 significant digits Align decimal points (exponents, shift smaller) Guard 5, Round Round: 237 x 1 Without guard & round bits, result: 236 x 1 Error of 1 Unit in the least significant position Why 2 bits? Product could have leading, so shift left when normalizing cps 14 6

4 What is Computer Architecture? Coordination of levels of abstraction Application CPU Compiler Operating System Digital Design Circuit Design Firmware I/O system Software Interface Between HW and SW Set Architecture,, I/O Hardware Under a set of rapidly changing technology Forces cps 14 7 The Big Picture: Where are We Now? The Five Classic Components of a Computer Processor Control Input Datapath Output Today s Topic: Datapath Design cps 14 8

5 Datapath Design How do we build hardware to implement the MIPS instructions? Add, LW, SW, Beq, Jump cps 14 9 The MIPS Formats All MIPS instructions are bits long The three instruction formats: R-type op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits I-type op rs rt immediate 6 bits 5 bits 5 bits J-type op target address 6 bits 26 bits The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the op field address / immediate: address offset or immediate value target address: target address of the jump instruction cps 14 1

6 The MIPS Subset (We can t implement them all!) ADD and subtract add rd, rs, rt op 6 bits rs 5 bits rt 5 bits rd 5 bits shamt 5 bits funct 6 bits sub rd, rs, rt OR Immediate: ori rt, rs, imm op 6 bits rs 5 bits rt 5 bits immediate LOAD and STORE lw rt, rs, imm sw rt, rs, imm BRANCH: beq rs, rt, imm JUMP: j target op target address 6 bits 26 bits cps The Hardware Program How do I build the hardware to implement the MIPS instructions and their sequencing? Fetch Decode Operand Fetch Execute Result Store Next cps 14 12

7 Combinational Logic Elements (Basic Building Blocks) Adder MUX A B A Select MUX Adder CarryIn Y B Sum Carry ALU OP A B ALU Result Zero cps Storage Element: Register (Basic Building Block) Write Enable Register Similar to the D Flip Flop except - N-bit input and output Data In - Write Enable input N Write Enable: - negated (): Data Out will not change - asserted (1): Data Out will become the same as Data In Data Out N cps 14 14

8 Storage Element: Register File Register File consists of registers: Two -bit output busses: busa and busb One -bit input bus: busw Register is selected by: RA selects the register to put on busa RB selects the register to put on busb RW selects the register to be written via busw when Write Enable is 1 RW RA RB Write Enable5 5 5 busw -bit Registers Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: - RA or RB valid => busa or busb valid after access time busa busb cps Storage Element: Idealized Write Enable Address (idealized) One input bus: Data In One output bus: Data Out Data In DataOut word is selected by: Write Enable = : Address selects the word to put on the Data Out bus Write Enable = 1: Address selects the memory word to be written via the Data In bus Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: - Address valid => Data Out valid after access time cps 14

9 An Abstract View of the Implementation PC Address Ideal Rd 5 Rs 5 Rt 5 Imm Rw Ra Rb -bit Registers A B ALU Data Address Data In Ideal Data DataOut cps Clocking Methodology Setup Hold Don t Care Setup Hold All storage elements are clocked by the same clock edge Cycle Time >= CLK-to-Q + Longest Delay Path + Setup + Clock Skew Longest delay path = critical path cps 14 18

10 An Abstract View of the Critical Path Register file and ideal memory: The CLK input is a factor ONLY during write operation During read operation, behave as combinational logic: - Address valid => Output valid after access time PC Address Ideal Rd 5 Rs 5 Rt 5 Imm Rw Ra Rb -bit Registers ALU Data Address Data In Ideal Data DataOut cps The Steps of Designing a Processor Set Architecture => Register Transfer Language Register Transfer Language => Datapath components Datapath interconnect Datapath components => Control signals Control signals => Control logic cps 14 2

11 Overview of the Fetch Unit The common RTL operations Fetch the : mem[pc] Update the program counter: - Sequential Code: PC <- PC Branch and Jump: PC <- something else PC Next Address Logic Address Word cps RTL: The ADD add rd, rs, rt mem[pc] Fetch the instruction from memory R[rd] <- R[rs] + R[rt] The ADD operation PC <- PC + 4 Calculate the next instruction s address cps 14 22

12 RTL: The Load lw rt, rs, imm mem[pc] Fetch the instruction from memory Addr <- R[rs] + SignExt(imm) Calculate the memory address R[rt] <- Mem[Addr] Load the data into the register PC <- PC + 4 Calculate the next instruction s address cps RTL: The ADD op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt mem[pc] Fetch the instruction from memory R[rd] <- R[rs] + R[rt] The actual operation PC <- PC + 4 Calculate the next instruction s address cps 14 24

13 RTL: The Subtract op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits sub rd, rs, rt mem[pc] Fetch the instruction from memory R[rd] <- R[rs] - R[rt] The actual operation PC <- PC + 4 Calculate the next instruction s address cps Datapath for Register-Register Operations R[rd] <- R[rs] op R[rt] Example: add rd, rs, rt Ra, Rb, and Rw comes from instruction s rs, rt, and rd fields ALUctr and RegWr: control logic after decoding the instruction fields: op and func op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits busw RegWr Rd Rs Rt Rw Ra Rb -bit Registers busa busb ALUctr ALU Result cps 14 26

14 Register-Register Timing Inst fetch Decode Opr fetch Execute Write Back PC Old Value Rs, Rt, Rd, Op, Func ALUctr RegWr busa, B busw cps busw -to-q New Value Old Value Old Value Old Value Old Value Old Value RegWr Access Time New Value Rd Rs Rt Rw Ra Rb -bit Registers Delay through Control Logic New Value busa busb New Value Register File Access Time New Value ALU Delay New Value ALUctr ALU Result Register Write Occurs Here RTL: The OR Immediate op rs rt immediate 6 bits 5 bits 5 bits ori rt, rs, imm mem[pc] Fetch the instruction from memory R[rt] <- R[rs] or ZeroExt(imm) The OR operation PC <- PC + 4 Calculate the next instruction s address immediate cps 14 28

15 Datapath for Logical Operations with Immediate R[rt] <- R[rs] op ZeroExt[imm]] Example: ori rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits Rd Rt RegDst Don t Care Rs RegWr (Rt) busw imm Rw Ra Rb -bit Registers busb ZeroExt busa ALUSrc ALUctr ALU Result cps RTL: The Load lw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits mem[pc] Fetch the instruction from memory Addr <- R[rs] + SignExt(imm) Calculate the memory address R[rt] <- Mem[Addr] Load the data into the register PC <- PC + 4 Calculate the next instruction s address immediate immediate cps 14 3

16 Datapath for Load Operations R[rt] <- Mem[R[rs] + SignExt[imm]] Example: lw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits Rd Rt RegDst Don t Care Rs RegWr (Rt) busw imm Rw Ra Rb -bit Registers busb Extender busa ALUSrc ALUctr ALU Data In MemWr WrEn Adr Data MemtoReg cps ExtOp RTL: The Store op rs rt immediate 6 bits 5 bits 5 bits sw rt, rs, imm mem[pc] Fetch the instruction from memory Addr <- R[rs] + SignExt(imm) Calculate the memory address Mem[Addr] <- R[rt] Store the register into memory PC <- PC + 4 address Calculate the next instruction s cps 14

17 Datapath for Store Operations Mem[R[rs] + SignExt[imm] <- R[rt]] Example: sw rt, rs, imm op rs rt immediate 6 bits 5 bits 5 bits RegDst busw Rd Rt RegWr 5 5 imm Rs Rt 5 Rw Ra Rb -bit Registers busb Extender busa ALUSrc ALUctr ALU Data In MemWr WrEn Adr Data MemtoReg cps ExtOp RTL: The Branch op rs rt immediate 6 bits 5 bits 5 bits beq rs, rt, imm mem[pc] Fetch the instruction from memory Cond <- R[rs] - R[rt] Calculate the branch condition if (COND eq ) Calculate the next instruction s address - PC <- PC ( SignExt(imm) x 4 ) else - PC <- PC + 4 cps 14 34

18 Datapath for Branch Operations beq rs, rt, imm We need to compare Rs and Rt! op rs rt immediate 6 bits 5 bits 5 bits Rd Rt RegDst Rs Rt RegWr busw imm Rw Ra Rb -bit Registers busb Extender busa ALUSrc ALUctr ALU imm Branch Zero PC Next Address Logic To cps ExtOp Binary Arithmetic for the Next Address In theory, the PC is a -bit byte address into the instruction memory: Sequential operation: PC<31:> = PC<31:> + 4 Branch operation: PC<31:> = PC<31:> SignExt[Imm] * 4 The magic number 4 always comes up because: The -bit PC is a byte address And all our instructions are 4 bytes ( bits) long In other words: The 2 LSBs of the -bit PC are always zeros There is no reason to have hardware to keep the 2 LSBs In practice, we can simplify the hardware by using a 3-bit PC<31:2>: Sequential operation: PC<31:2> = PC<31:2> + 1 Branch operation: PC<31:2> = PC<31:2> SignExt[Imm] In either case: --Address = PC<31:2> concat cps 14 36

19 Next Address Logic: Expensive and Fast Solution Using a 3-bit PC: Sequential operation: PC<31:2> = PC<31:2> + 1 Branch operation: PC<31:2> = PC<31:2> SignExt[Imm] In either case: --Address = PC<31:2> concat PC 3 1 imm <15:> SignExt Adder Adder 3 1 Addr<31:2> Addr<1:> <31:> Branch Zero cps Next Address Logic 3 PC imm <15:> 3 SignExt Carry In Adder 3 Addr<31:2> Addr<1:> <31:> Branch Zero cps 14 38

20 RTL: The Jump op target address 6 bits 26 bits j target mem[pc] Fetch the instruction from memory PC <- PC+4<31:28> concat target<25:> concat <> Calculate the next instruction s address cps Fetch Unit j target PC<31:2> <- PC+4<31:28> concat target<25:> 3 PC+4<31:28> 4 Target <25:> Addr<31:2> Addr<1:> PC 3 1 imm <15:> Adder SignExt 3 Adder Jump <31:> Branch Zero cps 14 4

21 Putting it All Together: A Single Cycle Datapath We have everything except control signals imm Extender Branch Jump Rd Rt RegDst 1 Rs Rt RegWr busa Rw Ra Rb busw -bit Registers busb 1 ALUSrc Fetch Unit ALUctr ALU Data In Zero <31:> Rt <21:25> Rs <:2> MemWr WrEn Adr Data Rd <11:15> <:15> Imm 1 MemtoReg cps ExtOp