Heterogeneous 3-D stacking, can we have the best of both (technology) worlds

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1 Heterogeneous 3-D stacking, can we have the best of both (technology) worlds Liam Madden Corporate Vice President March 25 th, 2013

2 The Chameleon Chip Field Programmable Gate Array (FPGA) Page 2

3 Moore s Law 1965: Transistor density doubles every year 64K devices 10x doubling (actual 9X) 64 devices 10 years Revised 1975: Transistor density doubles every two years Cramming more components onto integrated circuits Gordon Moore, Electronics, Volume 38, Number 8, April 19th 1965 Page 3

1979 1981 1983 1985 1987 1989 1991 1993 1995

4 A Career in One Graph Minimum Feature Size 1E-05 10um 1E-06 1um 100nm 1E-07 1E-08 10nm 1E-09 1nm Page 4

5 Die Cost Cost Comparison: Monolithic vs Multi-Die Moore s Law is really about economics Gordon Moore Monolithic Multi-Die Die Area Page 5

6 Why is First 3D Logic Product an FPGA? Natural partition using long lines Very low opportunity cost No 3 rd party dependence Size matters to customers Compelling value proposition next generation density in this generation technology Page 6

7 Virtex 2000T: Homogeneous Stacked Silicon Interconnect Technology (SSIT) FPGA slice FPGA Slices Side-by-Side Silicon Interposer >10K routing connections between Silicon slices ~1ns latency Interposer Page 7

connect micro bumps & TSVs Side-by-Side Package Die Layout Minimal heat flux issues New!

8 Elements of SSIT TSV C4 FPGA Interposer Microbumps 004mm Access to power / ground / IOs Microbumps Through-silicon Vias (TSV) Only bridge power / ground / IOs to C4 bumps 02mm Passive Silicon Interposer (65nm Generation) 4 conventional metal layers connect micro bumps & TSVs Side-by-Side Package Die Layout Minimal heat flux issues New! 28nm FPGA Slice 28nm FPGA Slice 28nm FPGA Slice 28nm FPGA Slice Microbumps Silicon Interposer Through-Silicon Vias Package Substrate Package Ball 1mm C4 Bumps BGA Balls Page 8

9 3D Supply Chain FPGA, Interposer, & Package Design 28nm FPGA & Interposer Package Substrate IBIDEN Bump, Die separation CoC/CoWoS, & Assembly Final Test of Packaged Part

10 Co(CoS) Process Flow Wafer with TSV u-pad/bump, Probe Dice Carrier Carrier Mount Thin & TSV Reveal UBM & C4-bump Interposer-on-Substrate Carrier De-mount to Film frame Package Page 10

11 (CoW)oS Process Flow-1 (Courtesy of TSMC) Bottom die Top-die Stacking (μbump) Wafer Molding Carrier bonding carrier B/S grinding carrier B/S C4 bumping carrier Page 11

12 (CoW)oS Process Flow-2 (Courtesy of TSMC) Transfer glass to tape carrier Tape Singulation Tape TIS (Stacking, C4) Build up Subs TIS (Ring+Lid) Thermal Interface Metal (TIM) Lid Ring Top view Bottom view Side view Page 12

13 3D Stacking: A world of difference Earth Area: ~500 Million km 2 Population: ~68 Billion People Oceans: 5 Age: ~45 Billion Years Virtex T Interposer Area: ~775 mm 2 Population: ~68 Billion Transistors Sub-chips: 5 Age: ~45 weeks

14 Heterogeneous Integration

Core L2$ DP Ctl L1 $ FPU North Bridge GPU 1983 Harris J11 4um 1989 DEC Rigel

15 3 Decades of Microprocessor Integration A Personal History Integrate or be integrated Fred Weber, former CTO AMD Year Company Product Integration Level Core L2$ DP Ctl L1 $ FPU North Bridge GPU 1983 Harris J11 4um 1989 DEC Rigel 15um 1991 DEC Alpha 075um 2005 Microsoft Xenon 3 Core 90nm 2011 AMD Fusion 2 Core 40nm Page 15

What Happened to System on a Chip? Logic Memory Analog Global Revenue 2011 $150B $68B $45B Moore Scaling Good Good Poor Technology Vintage 28nm 28nm 180nm?

16 What Happened to System on a Chip? Logic Memory Analog Global Revenue 2011 $150B $68B $45B Moore Scaling Good Good Poor Technology Vintage 28nm 28nm 180nm? Transistor Characteristics High performance/ Low leakage Low leakage/ moderate performance Stable with good voltage headroom Metallization layers >9 <5 <6 Differentiators High density logic Charge storage Passives, Optical Page 16

to chip loading issues Leads to increased area, power and complexity (SERDES) 100 Pkg via diam Pkg trace width 240 Bump Pitch Si 10 Package

17 m m What s the Problem with Multiple Packages? The packaging chasm Two orders difference in package trace/width vs silicon metallization I/O also isn t scaling due to bump pitch and chip to chip loading issues Leads to increased area, power and complexity (SERDES) 100 Pkg via diam Pkg trace width 240 Bump Pitch Si 10 Package Via Diameter Package Trace Width Chip Top Metal ~06 m 1 Chip top metal Signal Power Solder Bump Cu Pillar ~3 m ~100 m PKG To scale in X dimension Page 17

18 Chip Input/Output Bottleneck Source: ITRS 15x drop in I/O-to-logic ratio by 2020 Page 18

19 Crossing the Packaging Chasm Logic Process Memory Process Analog Process up Wide bus Wide bus DRAM Memory Analog FPGA Mem Analog Package Page 19

Virtex-7 HT: Heterogeneous SerDes Top View Cross Section TSVs 28G SerDes Fabric Interface 28G FPGA FPGA FPGA 28G 13G FPGA 13G Passive Interposer 13G FPGA 13G Yield optimized 13G FPGA 13G Noise

20 Virtex-7 HT: Heterogeneous SerDes Top View Cross Section TSVs 28G SerDes Fabric Interface 28G FPGA FPGA FPGA 28G 13G FPGA 13G Passive Interposer 13G FPGA 13G Yield optimized 13G FPGA 13G Noise isolation 28G SerDes 28G process optimized for performance Passive Interposer 28Tb/s ~3X Monolithic FPGA process optimized for power 16 x 28G Transceivers 72 x 13G Transceivers 650 GPIO Page 20

21 7V580T Dual FPGA Slice with 8x28Gb/s SerDes Die Virtex-7 28Gbps Page 21

22 Interposer Routing and DCAP Wire coupling, no shielding Wire coupling, with shielding 3mm SSN, no DCAP SSN, with DCAP 6mm Page 22

23 TSV Capacitance as Function of Substrate Resistivity Measured 20ohm-cm Silicon interposer Simulated 20ohm-cm Silicon interposer Measured 10ohm-cm Silicon interposer Simulated 10ohm-cm Silicon interposer Page 23

24 Insertion Loss as a Function of Interposer Resistivity Measured 20ohm-cm Silicon interposer Simulated 20ohm-cm Silicon interposer Measured 10ohm-cm Silicon interposer Simulated 10ohm-cm Silicon interposer Page 24

Simulated Eye Diagram and Measured Eye Diagram Comparison @ 28Gb/s Simulation Measurement Measured Amplitude:

25 Simulated Eye Diagram and Measured Eye Diagram 28Gb/s Simulation Measurement Measured Amplitude: 923mVp-p Measured Total Jitter: 625 BER 10E-12 Measured Random Jitter: 230 fs (0175UI of total jitter) Page 25

26 3D Thermo-Mechanical Simulations at 25C Warpage Logic die Serdes die S33 Peel Stress Von Mises Stress S13 Shear Stress Page 26

27 SSIT Enables Scalable FPGAs XC7VH290T XC7VH580T XC7VH870T GTZ-IC GTZ-IC GTH FPGA GTH GTH GTZ-IC FPGA GTH GTH FPGA GTH GTH FPGA GTH GTH FPGA GTH GTH FPGA GTH GTZ-IC Network 2 x 100G 2 x 100G 1 x 400G or 4 x 100G GTZ (28G) GTH (13G) Logic Cells 284K 580K 876K Page 27

28 High Bandwidth Integrated Memory Higher memory bandwidth at lower power 1Tbps 2Tbps ~1Gb/s per interposer wire Simple extension of existing work FPGA FPGA Die PKG Page 28

29 3D Active on Active: The Next Frontier Who s on top? Top die Package lid Microbumps Bottom die Package substrate High performance chip on top for thermal and TSV process availability Bottom die supports power TSV s for top die TSVs C4 balls BGA package balls TSV-Induced Device Stress Floor-planning critical Thermal concerns TSV keep out zones Page 29

Challenges Cost Wafer backside processing is complicated Device quality wafers used for interposers KGD methodologies still emerging Scalability Micro-bump scaling is limited

30 Challenges Cost Wafer backside processing is complicated Device quality wafers used for interposers KGD methodologies still emerging Scalability Micro-bump scaling is limited Super-sized interposers (>30mm x 30mm) Improve TSV aspect ratio Design Support Multi-die analysis without Multi-mode Multi-corner explosion Thermal modeling based on vertical hotspots Page 30

31 Summary Economic and technology forces are aligned to enable 3-D stacking The end game will see three distinct technologies: Logic, Memory, Analog Analog Logic Mem Package Heterogeneous integration is already here Page 31

32 Thank You Questions? Page 32

33 Follow Xilinx facebookcom/xilinxinc twittercom/#!/xilinxinc youtubecom/xilinxinc Page 33

Dual Integration - Verschmelzung von Wafer und Panel Level Technologien

ERÖFFNUNG DES INNOVATIONSZENTRUMS ADAPTSYS Dual Integration - Verschmelzung von Wafer und Panel Level Technologien Dr. Michael Töpper BDT Introduction Introduction Why do we need such large machines to