LTC Channel, 12-Bit, 1.5Msps Simultaneous Sampling ADC With Shutdown DESCRIPTION FEATURES APPLICATIONS BLOCK DIAGRAM

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1 FEATURES n 1.5Msps ADC with 6 Simutaneousy Samped Differentia Inputs n 25ksps Throughput per Channe n 72dB SINAD n Low Power Dissipation: 16.5mW n 3V Singe Suppy Operation n 2.5V Interna Bandgap Reference, Can be Overdriven With Externa Reference n 3-Wire SPI-Compatibe Seria Interface n Interna Conversion Triggered by CONV n SLEEP (12μW) Shutdown Mode n NAP (4.5mW) Shutdown Mode n V to 2.5V Unipoar, or ±1.25V Bipoar Differentia Input Range n 83dB Common Mode Rejection n Tiny 32-Pin (5mm 5mm) QFN Package APPLICATIONS n Mutiphase Power Measurement n Mutiphase Motor Contro n Data Acquisition Systems n Uninterruptabe Power Suppies L, LT, LTC and LTM are registered trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Protected by U.S. Patents incuding 68444, LTC Channe, 12-Bit, 1.5Msps Simutaneous Samping ADC With Shutdown DESCRIPTION The LTC is a 12-bit, 1.5Msps ADC with six simutaneousy samped differentia inputs. The device draws ony 5.5mA from a singe 3V suppy, and comes in a tiny 32-pin (5mm 5mm) QFN package. A Seep shutdown mode further reduces power consumption to 12μW. The combination of ow power and tiny package makes the LTC suitabe for portabe appications. The LTC contains six separate differentia inputs that are samped simutaneousy on the rising edge of the CONV signa. These six samped inputs are then converted at a rate of 25ksps per channe. The 83dB common mode rejection aows users to eiminate ground oops and common mode noise by measuring signas differentiay from the source. The device converts V to 2.5V unipoar inputs differentiay, or ±1.25V bipoar inputs aso differentiay, depending on the state of the BIP pin. Any anaog input may swing rai-to-rai as ong as the differentia input range is maintained. The conversion sequence can be abbreviated to convert fewer than six channes, depending on the ogic state of the SEL2, SEL1 and SEL inputs. The seria interface sends out the six conversion resuts in 96 cocks for compatibiity with standard seria interfaces. BLOCK DIAGRAM 1μF 3V CH5 CH5 CH4 CH4 CH3 CH3 CH2 CH2 CH1 CH S AND H S AND H S AND H S AND H S AND H S AND H MUX CH CH V CC V DD Msps 12-BIT ADC 12-BIT LATCH 12-BIT LATCH 1 12-BIT LATCH 2 12-BIT LATCH 3 12-BIT LATCH 4 12-BIT LATCH 5 THREE- STATE SERIAL OUTPUT PORT 3 OV DD 3V 1 SD.1μF OGND 2 2.5V REFERENCE TIMING LOGIC 3 CONV 32 SCK 31 DGND μF GND V REF BIP SEL2 SEL1 SEL TA1 1

2 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Suppy Votage (V DD, V CC, OV DD )...4V Anaog and V REF Input Votages (Note 3)....3V to (V DD.3V) Digita Input Votages....3V to (V DD.3V) Digita Output Votage....3V to (V DD.3V) Power Dissipation...1mW Operation Temperature Range LTC2351C C to 7 C LTC2351I C to 85 C LTC2351H C to 125 C Storage Temperature Range...65 C to 15 C PIN CONFIGURATION CH4 17 CH4 18 GND 19 CH5 2 CH5 21 GND 22 V REF 23 V CC TOP VIEW GND CH3 CH3 GND GND CH2 CH2 GND VDD SEL2 SEL1 SEL BIP CONV DGND SCK QFN PACKAGE 32-PIN (5mm 5mm) PLASTIC QFN T JMAX = 15 C, θ JA = 34 C/W EXPOSED PAD (PIN 33) IS GND, MUST BE SOLDERED TO PCB CH1 CH1 GND CH CH OV DD OGND SDO ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2351CUH-12#PBF LTC2351CUH-12#TRPBF Pin (5mm 5mm) Pastic QFN C to 7 C LTC2351IUH-12#PBF LTC2351IUH-12#TRPBF Pin (5mm 5mm) Pastic QFN 4 C to 85 C LTC2351HUH-12#PBF LTC2351HUH-12#TRPBF Pin (5mm 5mm) Pastic QFN 4 C to 125 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. Consut LTC Marketing for information on non-standard ead based fi nish parts. For more information on ead free part marking, go to: For more information on tape and ree specifi cations, go to: CONVERTER CHARACTERISTICS The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. With interna reference, V DD = V CC = 3V. PARAMETER CONDITIONS MIN TYP MAX UNITS Resoution (No Missing Codes) 12 Bits Integra Linearity Error (Note 5) 1 ±.25 1 LSB Offset Error (Note 4) LTC2351H-12 Offset Match from CH to CH5 3 ±.5 3 mv Range Error (Note 4) 12 ±2 12 mv Range Match from CH to CH5 5 ±1 5 mv Range Tempco Interna Reference (Note 4) Externa Reference ±1 ±1 ±15 ± mv mv ppm/ C ppm/ C 2

3 ANALOG INPUT The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. With interna reference, V DD = V CC = 3V. LTC SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IN Anaog Differentia Input Range (Notes 3, 8, 9) 2.7V V DD 3.6V, Unipoar 2.7V V DD 3.6V, Bipoar V CM Anaog Common Mode Differentia Input Range (Note 8) to V DD V I IN Anaog Input Leakage Current 1 μa C IN Anaog Input Capacitance 13 pf t ACQ Sampe-and-Hod Acquisition Time (Note 6) 39 ns t AP Sampe-and-Hod Aperture Deay Time 1 ns t JITTER Sampe-and-Hod Aperture Deay Time Jitter.3 ps t SK Channe to Channe Aperture Skew 2 ps CMRR Anaog Input Common Mode Rejection Ratio f IN = 1kHz, V IN = V to 3V f IN = 1MHz, V IN = V to 3V to 2.5 ± V V db db DYNAMIC ACCURACY The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. With interna reference, V DD = V CC = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SINAD Signa-to-Noise Pus Distortion Ratio 1kHz Input Signa 3kHz Input Signa 1kHz Input Signa (LTC2351H-12) db db db THD Tota Harmonic Distortion 1kHz First 5 Harmonics 3kHz First 5 Harmonics 1kHz First 5 Harmonics (LTC2351H-12) SFDR Spurious Free Dynamic Range 1kHz Input Signa 3kHz Input Signa IMD Intermoduation Distortion.625V P-P, 833kHz into CH,.625V P-P, 841kHz into CH Bipoar Mode. Aso Appicabe to Other Channes db db db db db 8 db Code-to-Code Transition Noise V REF = 2.5V (Note 17).2 LSB RMS Fu Power Bandwidth V IN = 2.5V P-P, SDO = 11585LSB P-P (3dBFS) (Note 15) 5 MHz Fu Linear Bandwidth S/(N D) 68dB, Bipoar Differentia Input 5 MHz INTERNAL REFERENCE CHARACTERISTICS T A = 25 C. V DD = V CC = 3V. PARAMETER CONDITIONS MIN TYP MAX UNITS V REF Output Votage I OUT = 2.5 V V REF Output Tempco 15 ppm/ C V REF Line Reguation V DD = 2.7V to 3.6V, V REF = 2.5V 6 μv/v V REF Output Resistance Load Current =.5mA.2 Ω V REF Setting Time Ext C REF = 1μF 2 ms Externa V REF Input Range 2.55 V DD V 3

4 DIGITAL INPUTS AND DIGITAL OUTPUTS The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. V DD = V CC = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IH High Leve Input Votage V DD = 3.3V 2.4 V V IL Low Leve Input Votage V DD = 2.7V.6 V I IN Digita Input Current V IN = V to V DD ±1 μa C IN Digita Input Capacitance 5 pf V OH High Leve Output Votage V DD = 3V, I OUT = 2μA V V OL Low Leve Output Votage V DD = 2.7V, I OUT = 16μA.5 V V DD = 2.7V, I OUT = 1.6mA.4 V I OZ Hi-Z Output Leakage D OUT V OUT = V and V DD ±1 μa C OZ Hi-Z Output Capacitance D OUT 1 pf I SOURCE Output Short-Circuit Source Current V OUT = V, V DD = 3V 2 ma I SINK Output Short-Circuit Sink Current V OUT = V DD = 3V 15 ma POWER REQUIREMENTS The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. With interna reference, V DD = V CC = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V DD, V CC Suppy Votage V I DD I CC Suppy Current Active Mode, f SAMPLE = 1.5Msps Active Mode, f SAMPLE = 1.5Msps (LTC2351H-12) Nap Mode Nap Mode (LTC2351H-12) Seep Mode P D Power Dissipation Active Mode with SCK, f SAMPLE = 1.5Msps 16.5 mw ma ma ma ma μa TIMING CHARACTERISTICS The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. V DD = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f SAMPLE(MAX) Maximum Samping Rate per Channe (Conversion Rate) 25 khz t THROUGHPUT Minimum Samping Period (Conversion Acquisiton Period) 4 μs t SCK Cock Period (Note 16) 4 1 ns t CONV Conversion Time (Notes 6, 17) 96 SCLK cyces t 1 Minimum High or Low SCLK Puse Width (Note 6) 2 ns t 2 CONV to SCK Setup Time (Notes 6, 1) 3 1 ns t 3 SCK Before CONV (Note 6) ns t 4 Minimum High or Low CONV Puse Width (Note 6) 4 ns t 5 SCK to Sampe Mode (Note 6) 4 ns t 6 CONV to Hod Mode (Notes 6, 11) 1.2 ns t 7 96th SCK to CONV Interva (Affects Acquisition Period) (Notes 6, 7, 13) 45 ns t 8 Minimum Deay from SCK to Vaid Bits Through 11 (Notes 6, 12) 8 ns 4

5 TIMING CHARACTERISTICS The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. V DD = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t 9 SCK to Hi-Z at SDO (Notes 6, 12) 6 ns t 1 Previous SDO Bit Remains Vaid After SCK (Notes 6, 12) 2 ns t 11 V REF Setting Time After Seep-to-Wake Transition (Notes 6, 14) 2 ms Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabity and ifetime. Note 2: A votage vaues are with respect to ground GND. Note 3: When these pins are taken beow GND or above V DD, they wi be camped by interna diodes. This product can hande input currents greater than 1mA beow GND or greater than V DD without atchup. Note 4: Offset and range specifi cations appy for a singe-ended CH CH5 input with CH CH5 grounded and using the interna 2.5V reference. Note 5: Integra inearity is tested with an externa 2.55V reference and is defined as the deviation of a code from the straight ine passing through the actua endpoints of a transfer curve. The deviation is measured from the center of quantization band. Linearity is tested for CH ony. Note 6: Guaranteed by design, not subject to test. Note 7: Recommended operating conditions. Note 8: The anaog input range is defi ned for the votage difference between CHx and CHx, x = to 5. Note 9: The absoute votage at CHx and CHx must be within this range. Note 1: If ess than 3ns is aowed, the output data wi appear one cock cyce ater. It is best for CONV to rise haf a cock before SCK, when running the cock at rated speed. Note 11: Not the same as aperture deay. Aperture deay (1ns) is the difference between the 2.2ns deay through the sampe-and-hod and the 1.2ns CONV to Hod mode deay. Note 12: The rising edge of SCK is guaranteed to catch the data coming out into a storage atch. Note 13: The time period for acquiring the input signa is started by the 96th rising cock and it is ended by the rising edge of CONV. Note 14: The interna reference settes in 2ms after it wakes up from Seep mode with one or more cyces at SCK and a 1μF capacitive oad. Note 15: The fu power bandwidth is the frequency where the output code swing drops by 3dB with a 2.5V P-P input sine wave. Note 16: Maximum cock period guarantees anaog performance during conversion. Output data can be read with an arbitrariy ong cock period. Note 17: The conversion process takes 16 cocks for each channe that is enabed, up to 96 cocks for a 6 channes. 5

6 TYPICAL PERFORMANCE CHARACTERISTICS V DD = 3V, T A = 25 C SINAD (db) SINAD vs Input Frequency THD, 2nd, 3rd (db) THD, 2nd and 3rd vs Input Frequency UNIPOLAR SINGLE-ENDED THD 2nd 3rd THD, 2nd, 3rd (db) THD, 2nd and 3rd vs Input Frequency BIPOLAR SINGLE-ENDED THD 2nd 3rd FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) G G G SFDR vs Input Frequency SNR vs Input Frequency 1 2 1kHz Unipoar Sine Wave 8192 Point FFT Pot SFDR (db) FREQUENCY (MHz) SNR (db) FREQUENCY (MHz) MAGNITUDE (db) FREQUENCY (khz) G G G6 MAGNITUDE (db) kHz Bipoar Sine Wave 8192 Point FFT Pot FREQUENCY (khz) G7 DIFFERENTIAL LINEARITY (LSB) Differentia Linearity vs Output Code, Unipoar Mode OUTPUT CODE G8 INTEGRAL LINEARITY (LSB) Integra Linearity vs Output Code, Unipoar Mode OUTPUT CODE G9 6

7 TYPICAL PERFORMANCE CHARACTERISTICS V DD = 3V, T A = 25 C LTC MAGNITUDE (db) Fu Scae Signa Response 1 1 FREQUENCY (MHz) G1 CMRR (db) CMRR vs Frequency k 1k 1k 1M 1M 1M 1G FREQUENCY (Hz) G11 Crosstak vs Frequency PSRR vs Frequency 2 2 CROSSTALK (db) PSRR (db) k 1k 1k 1M 1M 1M 1G FREQUENCY (Hz) k 1k 1k 1M 1M 1M 1G FREQUENCY (Hz) G G13 7

8 PIN FUNCTIONS SDO (Pin 1): Three-State Seria Data Output. Each set of six output data words represent the six anaog input channes at the start of the previous conversion. Data for CH comes out first and data for CH5 comes out ast. Each data word comes out MSB fi rst. OGND (Pin 2): Ground Return for SDO Currents. Connect to the soid ground pane. OV DD (Pin 3): Power Suppy for the SDO Pin. OV DD must be no more than 3mV higher than V DD and can be brought to a ower votage to interface to ow votage ogic famiies. The unoaded high state at SDO is at the potentia of OV DD. CH (Pin 4): Non-Inverting Channe. CH operates fuy differentiay with respect to CH with a V to 2.5V, or ±1.25V differentia swing and a V to V DD absoute input range. CH (Pin 5): Inverting Channe. CH operates fuy differentiay with respect to CH with a 2.5V to V, or ±1.25V differentia swing and a V to V DD absoute input range. GND (Pins 6, 9, 12, 13, 16, 19): Anaog Grounds. These ground pins must be tied directy to the soid ground pane under the part. Anaog signa currents fow through these connections. CH1 (Pin 7): Non-Inverting Channe 1. CH1 operates fuy differentiay with respect to CH1 with a V to 2.5V, or ±1.25V differentia swing and a V to V DD absoute input range. CH1 (Pin 8): Inverting Channe 1. CH1 operates fuy differentiay with respect to CH1 with a 2.5V to V, or ±1.25V differentia swing and a V to V DD absoute input range. CH2 (Pin 1): Non-Inverting Channe 2. CH2 operates fuy differentiay with respect to CH2 with a V to 2.5V, or ±1.25V differentia swing and a V to V DD absoute input range. CH2 (Pin 11): Inverting Channe 2. CH2 operates fuy differentiay with respect to CH2 with a 2.5V to V, or ±1.25V differentia swing and a V to V DD absoute input range. 8 CH3 (Pin 14): Non-Inverting Channe 3. CH3 operates fuy differentiay with respect to CH3 with a V to 2.5V, or ±1.25V differentia swing and a V to V DD absoute input range. CH3 (Pin 15): Inverting Channe 3. CH3 operates fuy differentiay with respect to CH3 with a 2.5V to V, or ±1.25V differentia swing and a V to V DD absoute input range. CH4 (Pin 17): Non-Inverting Channe 4. CH4 operates fuy differentiay with respect to CH4 with a V to 2.5V, or ±1.25V differentia swing and a V to V DD absoute input range. CH4 (Pin 18): Inverting Channe 4. CH4 operates fuy differentiay with respect to CH4 with a 2.5V to V, or ±1.25V differentia swing and a V to V DD absoute input range. CH5 (Pin 2): Non-Inverting Channe 5. CH5 operates fuy differentiay with respect to CH5 with a V to 2.5V, or ±1.25V differentia swing and a V to V DD absoute input range. CH5 (Pin 21): Inverting Channe 5. CH5 operates fuy differentiay with respect to CH5 with a 2.5V to V, or ±1.25V differentia swing and a V to V DD absoute input range. GND (PIN 22): Anaog Ground for Reference. Anaog ground must be tied directy to the soid ground pane under the part. Anaog signa currents fow through this connection. The 1μF reference bypass capacitor shoud be returned to this pad. V REF (Pin 23): 2.5V Interna Reference. Bypass to GND and a soid anaog ground pane with a 1μF ceramic capacitor (or 1μF tantaum in parae with.1μf ceramic). Can be overdriven by an externa reference votage between 2.55V and V DD, V CC. V CC (Pin 24): 3V Positive Anaog Suppy. This pin suppies 3V to the anaog section. Bypass to the soid anaog ground pane with a 1μF ceramic capacitor (or 1μF tantaum) in parae with.1μf ceramic. Care shoud be taken to pace the.1μf bypass capacitor as cose to Pin 24 as possibe. Pin 24 must be tied to Pin 25.

9 PIN FUNCTIONS V DD (Pin 25): 3V Positive Digita Suppy. This pin suppies 3V to the ogic section. Bypass to DGND pin and soid anaog ground pane with a 1μF ceramic capacitor (or 1μF tantaum in parae with.1μf ceramic). Keep in mind that interna digita output signa currents fow through this pin. Care shoud be taken to pace the.1μf bypass capacitor as cose to Pin 25 as possibe. Pin 25 must be tied to Pin 24. SEL2 (Pin 26): Most Signifi cant Bit Controing the Number of Channes Being Converted. In combination with SEL1 and SEL, seects just the first channe (CH) for conversion. Incrementing SELx seects additiona channes(chch5) for conversion. 11, 11 or 111 seect a 6 channes for conversion. Must be kept in a fixed state during conversion and during the subsequent conversion to read data. SEL1 (Pin 27): Midde Significance Bit Controing the Number of Channes Being Converted. In combination with SEL and SEL2, seects just the first channe (CH) for conversion. Incrementing SELx seects additiona channes for conversion. 11, 11 or 111 seect a 6 channes (CHCH5) for conversion. Must be kept in a fixed state during conversion and during the subsequent conversion to read data. SEL (Pin 28): Least Signifi cant Bit Controing the Number of Channes Being Converted. In combination with SEL1 and SEL2, seects just the first channe (CH) for conversion. Incrementing SELx seects additiona channes for conversion. 11, 11 or 111 seect a 6 channes (CHCH5) for conversion. Must be kept in a fixed state during conversion and during the subsequent conversion to read data. LTC BIP (Pin 29): Bipoar/Unipoar Mode. The input differentia range is V 2.5V when BIP is LOW, and it is ±1.25V when BIP is HIGH. Must be kept in fi xed state during conversion and during subsequent conversion to read data. When changing BIP between conversions the fu acquisition time must be aowed before starting the next conversion. The output data is in 2 s compement format for bipoar mode and straight binary format for unipoar mode. CONV (Pin 3): Convert Start. Hods the six anaog input signas and starts the conversion on the rising edge. Two CONV puses with SCK in fi xed high or fixed ow state starts Nap mode. Four or more CONV puses with SCK in fixed high or fixed ow state starts Seep mode. DGND (Pin 31): Digita Ground. This ground pin must be tied directy to the soid ground pane. Digita input signa currents fow through this pin. SCK (Pin 32): Externa Cock Input. Advances the conversion process and sequences the output data at SD (Pin1) on the rising edge. One or more SCK puses wake from seep or nap power saving modes. 16 cock cyces are needed for each of the channes that are activated by SELx (Pins 26, 27, 28), up to a tota of 96 cock cyces needed to convert and read out a 6 channes. EXPOSED PAD (Pin 33): GND. Must be tied directy to the soid ground pane. 9

10 BLOCK DIAGRAM.1μF 1μF 3V 4 CH V CC V DD 5 CH S & H 6 7 CH1 8 CH1 S & H 9 1 CH2 CH CH3 14 CH3 15 S & H S & H MUX 1.5Msps 12-BIT ADC 12-BIT LATCH 12-BIT LATCH 1 12-BIT LATCH 2 12-BIT LATCH 3 12-BIT LATCH 4 12-BIT LATCH 5 THREE- STATE SERIAL OUTPUT PORT OV DD 3V SD OGND μF CH4 CH4 S & H TIMING LOGIC CONV 3 SCK CH5 21 CH5 S & H 2.5V REFERENCE EXPOSED PAD GND V REF μF BIP SEL2 SEL1 SEL DGND BD 1

11 TIMING DIAGRAMS LTC Timing Diagram t 2 t3 t SCK t 4 CONV t 6 Back to Back to SAMPLE mode if SELx = SAMPLE HOLD INTERNAL S/H STATUS t 8 t 1 t 9 t 8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH1 Hi-Z Hi-Z D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D X X D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D X X SDO t CONV 12-BIT DATA WORD 12-BIT DATA WORD t THROUGHPUT Back to SAMPLE mode if SELx = 1 to SAMPLE mode if SELx = 1 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH3 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH2 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D X X D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D X X 12-BIT DATA WORD 12-BIT DATA WORD tconv tthroughput t 6 t 4 t 6 SAMPLE Back to SAMPLE mode if SELx = 11 Back to SAMPLE mode if SELx = 1 t 8 t8 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH5 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION AT CH4 Hi-Z D1 D9 D8 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D X X D11 D11 D1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D X X TD1 t CONV 12-BIT DATA WORD 12-BIT DATA WORD t THROUGHPUT 11

12 TIMING DIAGRAMS Nap Mode and Seep Mode Waveforms SCK t 1 t 1 CONV NAP SLEEP t 11 V REF NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS TD2 SCK to SDO Deay SCK V IH SCK V IH t 8 t 1 t 9 SDO V OH V OL SDO TD3 Hi-Z 12

13 APPLICATIONS INFORMATION SELECTING THE NUMBER OF CONVERTED CHANNELS (SEL2, SEL1, SEL) These three contro pins seect the number of channes being converted. seects ony the first channe (CH) for conversion. Incrementing SELx seects additiona channes for conversion, up to 6 channes. 11, 11 or 111 seect a 6 channes for conversion. These pins must be kept in a fixed state during conversion and during the subsequent conversion to read data. When changing modes between conversions, keep in mind that the output data of a particuar channe wi remain unchanged unti after that channe is converted again. For exampe: convert a sequence of 4 channes (CH, CH1, CH2, CH3) with SELx = 11, then, after these channes are converted change SELx to 1 to convert just CH and CH1. See Tabe 1. During the conversion of the first set of two channes you wi be abe to read the data from the same two channes converted as part of the previous group of 4 channes. Later, you coud convert 4 or more channes to read back the unread CH2 and CH3 data that was converted in the first set of 4 channes. These pins are often hardwired to enabe the right number of channes for a particuar appication. Choosing to convert fewer channes per conversion resuts in faster throughput of those channes. For exampe, 6 channes can be converted at 25ksps/ch, whie 3 channes can be converted at 5ksps/ch. BIPOLAR/UNIPOLAR MODE The input votage range for each of the CHx input differentia pairs is UNIPOLAR V 2.5V when BIP is LOW, and BIPOLAR ±1.25V when BIP is HIGH. This pin must be kept in fi xed state during conversion and during subsequent conversion to read data. When changing BIP between conversions the fu acquisition time must be aowed before starting the next conversion. After changing modes from BIPOLAR to UNIPOLAR, or from UNIPOLAR to BIPOLAR, you can sti read the first set of channes in the new mode, by inverting the MSB to read these channes in the mode that they were converted in. DRIVING THE ANALOG INPUT The differentia anaog inputs of the LTC may be driven differentiay or as a singe-ended input (i.e., the CH input is grounded). A tweve anaog inputs of a six differentia anaog input pairs, CH and CH, CH1 and CH1, CH2 and CH2, CH3 and CH3, CH4 and CH4 and CH5 and CH5, are samped at the same instant. Any unwanted signa that is common to both inputs of each input pair wi be reduced by the common mode rejection of the sampe-and-hod circuit. The inputs draw ony one sma current spike whie charging the sampeand-hod capacitors at the end of conversion. During conversion, the anaog inputs draw ony a sma eakage Tabe 1. Conversion Sequence Contro ( acquire represents simutaneous samping of a channes; CHx represents conversion of channes) SEL2 SEL1 SEL CHANNEL ACQUISITION AND CONVERSION SEQUENCE acquire, CH, acquire, CH... 1 acquire, CH, CH1, acquire, CH, CH acquire, CH, CH1, CH2, acquire, CH, CH1, CH acquire, CH, CH1, CH2, CH3, acquire, CH, CH1, CH2, CH acquire, CH, CH1, CH2, CH3, CH4, acquire, CH,CH1,CH2, CH3, CH acquire, CH, CH1, CH2, CH3, CH4, CH5, acquire, CH, CH1, CH2, CH3, CH4, CH acquire, CH, CH1, CH2, CH3, CH4, CH5, acquire, CH, CH1, CH2, CH3, CH4, CH acquire, CH, CH1, CH2, CH3, CH4, CH5, acquire, CH, CH1, CH2, CH3, CH4, CH

14 APPLICATIONS INFORMATION current. If the source impedance of the driving circuit is ow, then the LTC inputs can be driven directy. As source impedance increases, so wi acquisition time. For minimum acquisition time with high source impedance, a buffer ampifier must be used. The main requirement is that the ampifier driving the anaog input(s) must sette after the sma current spike before the next conversion starts (the time aowed for setting must be at east 39ns for fu throughput rate). Aso keep in mind whie choosing an input ampifier the amount of noise and harmonic distortion added by the ampifi er. CHOOSING AN INPUT AMPLIFIER Choosing an input ampifier is easy if a few requirements are taken into consideration. First, to imit the magnitude of the votage spike seen by the ampifi er from charging the samping capacitor, choose an ampifi er that has a ow output impedance (< 1Ω) at the cosed-oop bandwidth frequency. For exampe, if an ampifi er is used in a gain of 1 and has a unity-gain bandwidth of 5MHz, then the output impedance at 5MHz must be ess than 1Ω. The second requirement is that the cosed-oop bandwidth must be greater than 4MHz to ensure adequate sma-signa setting for fu throughput rate. If sower op amps are used, more time for setting can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC depends on the appication. Generay, appications fa into two categories: AC appications where dynamic specifications are most critica and time domain appications where DC accuracy and setting time are most critica. The foowing ist is a summary of the op amps that are suitabe for driving the LTC (More detaied information is avaiabe in the Linear Technoogy Databooks and on the website at LTC1566-1: Low Noise 2.3MHz Continuous Time Lowpass Fiter. LT 163: Dua 3MHz Rai-to-Rai Votage FB Ampifi er. 2.7V to ±15V suppies. Very high A VOL, 5μV offset and 52ns setting to.5lsb for a 4V swing. THD and noise are 93dB to 4kHz and beow 1LSB to 32kHz (A V = 1, 2V P-P into 1kΩ, V S = 5V), making the part exceent for AC 14 appications (to 1/3 Nyquist) where rai-to-rai performance is desired. Quad version is avaiabe as LT1631. LT1632: Dua 45MHz Rai-to-Rai Votage FB Ampifier. 2.7V to ±15V suppies. Very high A VOL, 1.5mV offset and 4ns setting to.5lsb for a 4V swing. It is suitabe for appications with a singe 5V suppy. THD and noise are 93dB to 4kHz and beow 1LSB to 8kHz (A V = 1, 2V P-P into 1kΩ, V S = 5V), making the part exceent for AC appications where rai-to-rai performance is desired. Quad version is avaiabe as LT1633. LT181: 8MHz GBWP, 75dBc at 5kHz, 2mA/ampifier, 8.5nV/ Hz. LT186/LT187: 325MHz GBWP, 8dBc distortion at 5MHz, unity gain stabe, rai-to-rai in and out, 1mA/ampifier, 3.5nV/ Hz. LT181: 18MHz GBWP, 9dBc distortion at 5MHz, unity gain stabe, rai-to-rai in and out, 15mA/ampifier, 16nV/ Hz. LT1818/LT1819: 4MHz, 25V/μs, 9mA, Singe/Dua Votage Mode Operationa Ampifier. LT62: 165MHz GBWP, 85dBc distortion at 1MHz, unity gain stabe, rai-to-rai in and out, 15mA/ampifier,.95nV/ Hz. LT623: 1MHz GBWP, 8dBc distortion at 1MHz, unity gain stabe, rai-to-rai in and out, 3mA/ampifier, 1.9nV/ Hz. LT66: Ampifier/Fiter Differentia In/Out with 1MHz Cutoff Frequency. INPUT FILTERING AND SOURCE IMPEDANCE The noise and the distortion of the input ampifier and other circuitry must be considered since they wi add to the LTC noise and distortion. The sma-signa bandwidth of the sampe-and-hod circuit is 5MHz. Any noise or distortion products that are present at the anaog inputs wi be summed over this entire bandwidth. Noisy input circuitry shoud be fitered prior to the anaog inputs. A simpe 1-poe RC fiter is sufficient for many appications. For exampe, Figure 1 shows a 47pF capacitor from CHO to ground and a 51Ω source resistor to imit the

15 APPLICATIONS INFORMATION ANALOG INPUT ANALOG INPUT 51Ω* 51Ω* 1 47pF* 2 3 1μF pF* 5 CH CH LTC V REF GND CH1 CH F1 *TIGHT TOLERANCE REQUIRED TO AVOID APERTURE SKEW DEGRADATION Figure 1. RC Input Fiter net input bandwidth to 3MHz. The 47pF capacitor aso acts as a charge reservoir for the input sampe-and-hod and isoates the ADC input from samping-gitch sensitive circuitry. High quaity capacitors and resistors shoud be used since these components can add distortion. NPO and sivermica type dieectric capacitors have exceent inearity. Carbon surface mount resistors can generate distortion from sef heating and from damage that may occur during sodering. Meta fi m surface mount resistors are much ess susceptibe to both probems. When high ampitude unwanted signas are cose in frequency to the desired signa frequency a mutipe poe fi ter is required. High externa source resistance, combined with 13pF of input capacitance, wi reduce the rated 5MHz input bandwidth and increase acquisition time beyond 39ns. INPUT RANGE The anaog inputs of the LTC may be driven fuy differentiay with a singe suppy. Either input may swing up to V CC, provided the differentia swing is no greater than 2.5V with BIP (Pin 29) Low, or ±1.25V with (BIP Pin 29) High. The V to 2.5V range is aso ideay suited for singe-ended input use with singe suppy appications. The common mode range of the inputs extend from ground to the suppy votage V CC. If the difference between the CH and CH at any input pair exceeds 2.5V (unipoar) or 1.25V (bipoar), the output code wi stay fixed at positive fu-scae, and if this difference goes beow V (unipoar) or 1.25V (bipoar), the output code wi stay fixed at negative fu-scae. 3.5V TO 18V LT179-3 LTC INTERNAL REFERENCE The LTC has an on-chip, temperature compensated, bandgap reference that is factory trimmed to 2.5V to obtain a precise 2.5V input span. The reference ampifier output V REF, (Pin 23) must be bypassed with a capacitor to ground. The reference ampifier is stabe with capacitors of 1μF or greater. For the best noise performance, a 1μF ceramic or a 1μF tantaum in parae with a.1μf ceramic is recommended. The V REF pin can be overdriven with an externa reference as shown in Figure 2. The votage of the externa reference must be higher than the 2.5V of the open-drain P-channe output of the interna reference. The recommended range for an externa reference is 2.55V to V DD. An externa reference at 2.55V wi see a DC quiescent oad of.75ma and as much as 3mA during conversion. 23 1μF 22 V REF LTC GND F2 Figure 2. Overdriving V REF Pin with an Externa Reference INPUT SPAN VERSUS REFERENCE VOLTAGE The differentia input range has a unipoar votage span that equas the difference between the votage at the reference buffer output V REF (Pin 23) and the votage at ground. The differentia input range of the ADC is V to 2.5V when using the interna reference. The interna ADC is referenced to these two nodes. This reationship aso hods true with an externa reference. DIFFERENTIAL INPUTS The ADC wi aways convert the difference of CH minus CH, independent of the common mode votage at any pair of inputs. The common mode rejection hods up at high frequencies (see Figure 3.) The ony requirement is that both inputs not go beow ground or exceed V DD. 15

16 APPLICATIONS INFORMATION STRAIGHT BINARY OUTPUT CODE 2'S COMPLEMENT OUTPUT CODE 16 CMRR (db) k FS 1k 1k 1M 1M 1M 1G FREQUENCY (Hz) Figure 3. CMRR vs Frequency INPUT VOLTAGE (V) INPUT VOLTAGE (V) F3 FS 1LSB F4 Figure 4. LTC Transfer Characteristic in Unipoar Mode (BIP = Low) FS 1LSB F5 Figure 5. LTC Transfer Characteristic in Bipoar Mode (BIP = High) Integra noninearity errors (INL) and differentia noninearity errors (DNL) are argey independent of the common mode votage. However, the offset error wi vary. DC CMRR is typicay better than 9dB. Figure 4 shows the idea input/output characteristics for the LTC in unipoar mode (BIP = Low). The code transitions occur midway between successive integer LSB vaues (i.e.,.5lsb, 1.5LSB, 2.5LSB, FS 1.5LSB). The output code is straight binary with 1LSB = 2.5V/496 = 61μV for the LTC The LTC has.2 LSB RMS of Gaussian white noise. Figure 5 shows the idea input/output characteristics for the LTC in bipoar mode (BIP = High). The code transitions occur midway between successive integer LSB vaues (i.e.,.5lsb, 1.5LSB, 2.5LSB, FS 1.5LSB). The output code is 2 s compement with 1LSB = 2.5V/496 = 61μV for the LTC The LTC has.2 LSB RMS of Gaussian white noise. POWER-DOWN MODES Upon power-up, the LTC is initiaized to the active state and is ready for conversion. The Nap and Seep mode waveforms show the power down modes for the LTC The SCK and CONV inputs contro the power down modes (see Timing Diagrams). Two rising edges at CONV, without any intervening rising edges at SCK, put the LTC in Nap mode and the power consumption drops from 16.5mW to 4.5mW. The interna reference remains powered in Nap mode. One or more rising edges at SCK wake up the LTC very quicky and CONV can start an accurate conversion within a cock cyce. Four rising edges at CONV, without any intervening rising edges at SCK, put the LTC in Seep mode and the power consumption drops from 16.5mW to 12μW. One or more rising edges at SCK wake up the LTC for operation. The interna reference (V REF ) takes 2ms to sew and sette with a 1μF oad. Using seep mode more frequenty compromises the accuracy of the output data. Note that for sower conversion rates, the Nap and Seep modes can be used for substantia reductions in power consumption.

17 APPLICATIONS INFORMATION DIGITAL INTERFACE The LTC has a 3-wire SPI (Seria Periphera Interface) interface. The SCK and CONV inputs and SDO output impement this interface. The SCK and CONV inputs accept swings from 3V ogic and are TTL compatibe, if the ogic swing does not exceed V DD. A detaied description of the three seria port signas foows: Conversion Start Input (CONV) The rising edge of CONV starts a conversion, but subsequent rising edges at CONV are ignored by the LTC unti the foowing 96 SCK rising edges have occurred. The duty cyce of CONV can be arbitrariy chosen to be used as a frame sync signa for the processor seria port. A simpe approach to generate CONV is to create a puse that is one SCK wide to drive the LTC and then buffer this signa to drive the frame sync input of the processor seria port. It is good practice to drive the LTC CONV input first to avoid digita noise interference during the sampe-to-hod transition triggered by CONV at the start of conversion. It is aso good practice to keep the width of the ow portion of the CONV signa greater than 15ns to avoid introducing gitches in the front end of the ADC just before the sampe-and-hod goes into Hod mode at the rising edge of CONV. Minimizing Jitter on the CONV Input In high speed appications where high ampitude sine waves above 1kHz are samped, the CONV signa must have as itte jitter as possibe (1ps or ess). The square wave output of a common crysta cock modue usuay meets this requirement. The chaenge is to generate a CONV signa from this crysta cock without jitter corruption from other digita circuits in the system. A cock divider and any gates in the signa path from the crysta cock to the CONV input shoud not share the same integrated circuit with other parts of the system. The SCK and CONV inputs shoud be driven fi rst, with digita buffers used to drive the seria port interface. Aso note that the master cock in the DSP may aready be corrupted with jitter, even if it comes directy from the DSP crysta. Another probem with high speed processor cocks is that they often use a ow cost, ow speed crysta (i.e., 1MHz) to generate a fast, LTC but jittery, phase-ocked-oop system cock (i.e., 4MHz). The jitter in these PLL-generated high speed cocks can be severa nanoseconds. Note that if you choose to use the frame sync signa generated by the DSP port, this signa wi have the same jitter of the DSP s master cock. The Typica Appication fi gure on page 2 shows a circuit for eve-shifting and squaring the output from an RF signa generator or other ow-jitter source. A singe D-type fip fop is used to generate the CONV signa to the LTC Re-timing the master cock signa eiminates cock jitter introduced by the controing device (DSP, FPGA, etc.) Both the inverter and fip fop must be treated as anaog components and shoud be powered from a cean anaog suppy. Seria Cock Input (SCK) The rising edge of SCK advances the conversion process and aso udpates each bit in the SDO data stream. After CONV rises, the third rising edge of SCK sends out up to six sets of 12 data bits, with the MSB sent first. A simpe approach is to generate SCK to drive the LTC first and then buffer this signa with the appropriate number of inverters to drive the seria cock input of the processor seria port. Use the faing edge of the cock to atch data from the seria data output (SDO) into your processor seria port. The 12-bit seria data wi be received in six 16-bit words with 96 or more cocks per frame sync. If fewer than 6 channes are seected by SELSEL2 for conversion, then 16 cocks are needed per channe to convert the anaog inputs and read out the resuting data after the next convert puse. It is good practice to drive the LTC SCK input first to avoid digita noise interference during the interna bit comparison decision by the interna high speed comparator. Unike the CONV input, the SCK input is not sensitive to jitter because the input signa is aready samped and hed constant. Seria Data Output (SDO) Upon power-up, the SDO output is automaticay reset to the high impedance state. The SDO output remains in high impedance unti a new conversion is started. SDO sends out up to six sets of 12 bits in the output data stream after the third rising edge of SCK after the start of conversion with 17

18 APPLICATIONS INFORMATION the rising edge of CONV. The six or fewer 12-bit words are separated by two don t care bits and two cock cyces in high impedance mode. Pease note the deay specification from SCK to a vaid SDO. SDO is aways guaranteed to be vaid by the next rising edge of SCK. The bit output data stream is compatibe with the 16-bit or 32-bit seria port of most processors. BOARD LAYOUT AND BYPASSING Wire wrap boards are not recommended for high resoution and/or high speed A/D converters. To obtain the best performance from the LTC , a printed circuit board with ground pane is required. Layout for the printed circuit board shoud ensure that digita and anaog signa ines are separated as much as possibe. In particuar, care shoud be taken not to run any digita track aongside an anaog signa track. If optimum phase match between the inputs is desired, the ength of the tweve input wires of the six input channes shoud be kept matched. But each pair of input wires to the six input channes shoud be kept separated by a ground trace to avoid high frequency crosstak between channes. High quaity tantaum and ceramic bypass capacitors shoud be used at the V CC, V DD and V REF pins as shown in the Bock Diagram on the first page of this data sheet. OV DD BYPASS,.1μF, 42 For optimum performance, a 1μF surface mount tantaum capacitor with a.1μf ceramic is recommended for the V CC, V DD and V REF pins. Aternativey, 1μF ceramic chip capacitors such as X5R or X7R may be used. The capacitors must be ocated as cose to the pins as possibe. The traces connecting the pins and the bypass capacitors must be kept short and shoud be made as wide as possibe. The V CC and V DD bypass capacitor returns to the ground pane and the V REF bypass capacitor returns to the Pin 22. Care shoud be taken to pace the.1μf V CC and V DD bypass capacitor as cose to Pins 24 and 25 as possibe. Figure 6 shows the recommended system ground connections. A anaog circuitry grounds shoud be terminated at the LTC Exposed Pad. The ground return from the LTC to the power suppy shoud be ow impedance for noise-free operation. The Exposed Pad of the 32-pin QFN package is aso internay tied to the ground pads. The Exposed Pad shoud be sodered on the PC board to reduce ground connection inductance. A ground pins (GND, DGND, OGND) must be connected directy to the same ground pane under the LTC HARDWARE INTERFACE TO TMS32C54x The LTC is a seria output ADC whose interface has been designed for high speed buffered seria ports in fast digita signa processors (DSPs). Figure 7 shows an exampe of this interface using a TMS32C54X. LTC V 5V TMS32C54x OV DD 3 V CC CONV 3 BFSR V DD BYPASS,.1μF, 42 SCK 32 BCLKR V REF BYPASS, 1μF, 85 V CC BYPASS,.1μF, 42 AND 1μF, 85 SDO OGND DGND CONV CLK 3-WIRE SERIAL INTERFACE LINK V TO 3V LOGIC SWING B11 B1 BDR F7 Figure 6. Recommended Layout Figure 7. DSP Seria Interface to TMS32C54x 18

19 APPLICATIONS INFORMATION The buffered seria port in the TMS32C54x has direct access to a 2kB segment of memory. The ADC s seria data can be coected in two aternating 1kB segments, in rea time, at the fu 1.5Msps conversion rate of the LTC The DSP assemby code sets frame sync mode at the BFSR pin to accept an externa positive going puse and the seria cock at the BCLKR pin to accept an externa positive edge cock. Buffers near the LTC may be added to drive ong tracks to the DSP to prevent LTC corruption of the signa to LTC This configuration is adequate to traverse a typica system board, but source resistors at the buffer outputs and termination resistors at the DSP, may be needed to match the characteristic impedance of very ong transmission ines. If you need to terminate the SDO transmission ine, buffer it first with one or two 74ACxx gates. The TTL threshod inputs of the DSP port respond propery to the 3V swing used with the LTC PACKAGE DESCRIPTION UH Package 32-Lead Pastic QFN (5mm 5mm) (Reference LTC DWG # ).7 ± ± ± REF (4 SIDES) 3.45 ± ±.5 PACKAGE OUTLINE PIN 1 TOP MARK (NOTE 6) 5. ±.1 (4 SIDES).25 ±.5.5 BSC RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED BOTTOM VIEW EXPOSED PAD.75 ±.5 R =.5 R =.115 TYP TYP PIN 1 NOTCH R =.3 TYP OR CHAMFER.4 ± REF (4-SIDES) 3.45 ± ±.1.2 REF NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M-22 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.2mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE.25 ±.5.5 BSC (UH32) QFN 46 REV D Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights. 19

20 TYPICAL APPLICATION Low-Jitter Cock Timing with RF Sine Generator Using Cock Squaring/Leve Shifting Circuit and Re-Timing Fip-Fop V CC.1μF 1k NC7SVU4P5X MASTER CLOCK 5Ω 1k D V CC PRE CLR Q Q CONV CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) NL17SZ74 CONVERT ENABLE 148 TA2 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS ADCs LTC Bit, 2.2Msps Seria ADC 5V or ±5V Suppy, 4.96V or ±2.5V Span LTC143/LTC143A 12-/14-Bit, 2.8Msps Seria ADC 3V, 15mW, Unipoar Inputs, MSOP Package LTC143-1/LTC143A-1 12-/14-Bit, 2.8Msps Seria ADC 3V, 15mW, Bipoar Inputs, MSOP Package LTC Bit, 5Msps Parae ADC 5V, Seectabe Spans, 115mW LTC147/LTC147A 12-/14-Bit, 3Msps Simutaneous Samping ADC 3V, 14mW, 2-Channe Unipoar Input Range LTC147-1/LTC147A-1 12-/14-Bit, 3Msps Simutaneous Samping ADC 3V, 14mW, 2-Channe Bipoar Input Range LTC Bit, 2.5Msps Parae ADC 5V, Seectabe Spans, 8dB SINAD LTC Bit, 3Msps Parae ADC ±5V Suppy, ±2.5V Span, 72dB SINAD LTC Bit, 1Msps Parae ADC 5V, Seectabe Spans, 72dB SINAD LTC Bit, 5ksps Parae ADC ±5V Suppy, ±2.5V Span, 9dB SINAD LTC Bit, 25ksps Seria ADC 5V Confi gurabe Bipoar/Unipoar Inputs LTC1864/LTC Bit, 25ksps 1-/2-Channe Seria ADCs 5V or 3V (L-Version), Micropower, MSOP Package LTC1864L/LTC1865L DACs LTC Bit, Seria SoftSpan I OUT DAC ±1LSB INL/DNL, Software Seectabe Spans LTC1666/LTC1667/ 12-/14-/16-Bit, 5Msps DAC 87dB SFDR, 2ns Setting Time LTC1668 References LT Micropower Series Votage Reference.1% Initia Accuracy, 1ppm Drift LT Precision Votage Reference.4% Initia Accuracy, 3ppm Drift LT Micropower Series Reference in SOT-23.5% Initia Accuracy, 1ppm Drift SoftSpan is a trademark of Linear Technoogy Corporation. 2 LT 29 REV A PRINTED IN USA Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA (48) FAX: (48) LINEAR TECHNOLOGY CORPORATION 26