LTM9001-Ax/LTM9001-Bx. 16-Bit IF/Baseband Receiver Subsystem FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION

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1 FEATURES n Integrated 16-Bit, High-Speed ADC, Passive Fiter and Fixed Gain Differentia Ampifi er n Up to 3MHz IF Range Lowpass and Bandpass Fiter Versions n Low Noise, Low Distortion Ampifi ers Fixed Gain: 8dB, 14dB, 2dB or 26dB 5Ω, 2Ω or 4Ω Input Impedance n 75dB SNR, 83dB SFDR (LTM91-AD) n Integrated Bypass Capacitance, No Externa Components Required n Optiona Interna Dither n Optiona Data Output Randomizer n LVDS or CMOS Outputs n 3.3V Singe Suppy n Power Dissipation: 1.65W n Cock Duty Cyce Stabiizer n 11.25mm 11.25mm 2.32mm LGA Package APPLICATIONS n Teecommunications n High Sensitivity Receivers n Ceuar Base Stations n Spectrum Anayzers L, LT, LTC, LTM, Burst Mode, Linear Technoogy and the Linear ogo are registered trademarks and ThinSOT is a trademark of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. LTM91-Ax/LTM91-Bx DESCRIPTION 16-Bit IF/Baseband Receiver Subsystem The LTM 91 is an integrated system in a package (SiP) that incudes a high-speed 16-bit A/D converter, matching network, anti-aiasing fiter and a ow noise, differentia ampifier with fi xed gain. It is designed for digitizing wide dynamic range signas with an intermediate frequency (IF) range up to 3MHz. The ampifier aows either ACor DC-couped input drive. A owpass or bandpass fiter network can be impemented with various bandwidths. Contact Linear Technoogy regarding semi-custom configurations. The LTM91 is perfect for IF receivers in demanding communications appications, with AC performance that incudes 72 noise foor and 82dB spurious free dynamic range (SFDR) at 162.5MHz (LTM91-AA). The digita outputs can be either differentia LVDS or singeended CMOS. There are two format options for the CMOS outputs: a singe bus running at the fu data rate or two demutipexed buses running at haf data rate. A separate output power suppy aows the CMOS output swing to range from.5v to 3.3V. The differentia ENC + and ENC inputs may be driven with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optiona cock duty cyce stabiizer aows high performance at fu speed with a wide range of cock duty cyces. TYPICAL APPLICATION Simpifi ed IF Receiver Channe V CC V DD = 3.3V SENSE LTM91 V DD =.5V TO 3.6V 64k Point FFT, f IN = 162.4MHz, 1, PGA = 1 2 LTM91-AA RF LO SAW IN IN + DIFFERENTIAL FIXED GAIN AMPLIFIER ANTI-ALIAS FILTER GND ENC + ENC 16-BIT 13Msps ADC ADC CONTROL PINS CLKOUT OF 91 TA1 D15 D OGND CMOS OR LVDS AMPLITUDE () HD3 HD TA1b 91fc 1

2 LTM91-Ax/LTM91-Bx ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Suppy Votage (V CC )....3V to 3.6V Suppy Votage (V DD )....3V to 4V Digita Output Suppy Votage (OV DD )....3V to 4V Anaog Input Current (IN +, IN )...±1mA Digita Input Votage (Except AMPSHDN)....3V to (V DD +.3V) Digita Input Votage (AMPSHDN)....3V to (V CC +.3V) Digita Output Votage....3V to (OV DD +.3V) Operating Temperature Range LTM91C... C to 7 C LTM91I... 4 C to 85 C Storage Temperature Range C to 125 C Maximum Junction Temperature C PIN CONFIGURATION ALL ELSE = GND J IN H IN + G F V CC E DNC D ENC + C ENC B A TOP VIEW CONTROL DATA CONTROL V DD OGND OV DD OGND OV DD OGND LGA PACKAGE T JMAX = 125 C, JA = 15 C/W, JCtop = 19 C/W JA DERIVED FROM 6mm 7mm PCB WITH 4 LAYERS WEIGHT =.71g ORDER INFORMATION LEAD FREE FINISH PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM91CV-AA#PBF LTM91V-AA 81-Lead (11.25mm 11.25mm 2.3mm) LGA C to 7 C LTM91IV-AA#PBF LTM91V-AA 81-Lead (11.25mm 11.25mm 2.3mm) LGA 4 C to 85 C LTM91CV-AD#PBF LTM91V-AD 81-Lead (11.25mm 11.25mm 2.3mm) LGA C to 7 C LTM91IV-AD#PBF LTM91V-AD 81-Lead (11.25mm 11.25mm 2.3mm) LGA 4 C to 85 C LTM91CV-BA#PBF LTM91V-BA 81-Lead (11.25mm 11.25mm 2.3mm) LGA C to 7 C LTM91IV-BA#PBF LTM91V-BA 81-Lead (11.25mm 11.25mm 2.3mm) LGA 4 C to 85 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. Consut LTC Marketing for information on non-standard ead based fi nish parts. For more information on ead free part marking, go to: This product is ony offered in trays. For more information go to: ELECTRICAL CHARACTERISTICS The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS G DIFF Gain DC, LTM91-AA f IN = 162.5MHz (Note 3) DC, LTM91-AD f IN = 7MHz (Note 3) DC, LTM91-BA f IN = 14MHz (Note 3) db db 14.7 db db 9.4 db db G TEMP Gain Temperature Drift V IN = Maximum, (Note 3) 2 mdb/ C 2 91fc

3 ELECTRICAL CHARACTERISTICS LTM91-Ax/LTM91-Bx The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V INCM Input Common Mode Votage Range (IN + + IN )/ V V IN Input Votage Range at 1 LTM91-AA at 162.5MHz LTM91-AD at 7MHz LTM91-BA at 14MHz R INDIFF Differentia Input Impedance LTM91-AA LTM91-AD LTM91-BA C INDIFF Differentia Input Capacitance Incudes Parasitic 1 pf V OS Offset Error (Note 6) Incuding Ampifi er and ADC (LTM91-AA) Incuding Ampifi er and ADC (LTM91-AD) Incuding Ampifi er and ADC (LTM91-BA) mv P-P mv P-P mv P-P Ω Ω Ω Offset Drift Incuding Ampifi er and ADC ±1 μv/ C Fu-Scae Drift Interna Reference Externa Reference ±3 ±15 ppm/ C ppm/ C CMRR Common Mode Rejection Ratio 6 db I SENSE SENSE Input Leakage Current V < SENSE < V DD 3 3 μa I MODE MODE Pin Pu-Down Current to GND 1 μa I LVDS LVDS Pin Pu-Down Current to GND 1 μa t AP Sampe-and-Hod Acquisition Deay Time 1 ns t JITTER Sampe-and-Hod Acquisition Deay Time Jitter 7 fs RMS mv mv mv CONVERTER CHARACTERISTICS The indicates specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. PARAMETER CONDITIONS MIN TYP MAX UNITS Resoution (No Missing Codes) 16 Bits Integra Linearity Error Differentia Input LTM91-Ax (Notes 5, 7) Differentia Input LTM91-BA (Notes 5, 7) ±2.4 ±8 ±1 Differentia Linearity Error Differentia Input (Notes 5, 7) ±.3 ±1 LSB Transition Noise Externa Reference 1 LSB RMS LSB LSB DYNAMIC ACCURACY The indicates specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. A IN = 1. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SNR Signa-to-Noise Ratio 162.5MHz Input (PGA = ) LTM91-AA 162.5MHz Input (PGA = 1) LTM91-AA MHz Input (PGA = ) LTM91-AD 7MHz Input (PGA = 1) LTM91-AD 14MHz Input (PGA = ) LTM91-BA 14MHz Input (PGA = 1) LTM91-BA fc 3

4 LTM91-Ax/LTM91-Bx DYNAMIC ACCURACY The indicates specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. A IN = 1. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SFDR Spurious Free Dynamic Range, 2nd or 3rd 162.5MHz Input (PGA = ) LTM91-AA 78 dbc Harmonic 162.5MHz Input (PGA = 1) LTM91-AA dbc 7MHz Input (PGA = ) LTM91-AD 7MHz Input (PGA = 1) LTM91-AD 14MHz Input (PGA = ) LTM91-BA 14MHz Input (PGA = 1) LTM91-BA SFDR Spurious Free Dynamic Range 4th or Higher 162.5MHz Input (PGA = ) LTM91-AA 162.5MHz Input (PGA = 1) LTM91-AA 86 7MHz Input (PGA = ) LTM91-AD 7MHz Input (PGA = 1) LTM91-AD 14MHz Input (PGA = ) LTM91-BA 14MHz Input (PGA = 1) LTM91-BA S/(N+D) Signa-to-Noise Pus Distortion Ratio 162.5MHz Input (PGA = ) LTM91-AA 162.5MHz Input (PGA = 1) LTM91-AA 67 SFDR SFDR IMD 3 IIP 3 Spurious Free Dynamic Range at 25, Dither OFF Spurious Free Dynamic Range at 15, Dither OFF Spurious Free Dynamic Range at 15, Dither OFF Spurious Free Dynamic Range at 25, Dither ON Spurious Free Dynamic Range at 15, Dither ON Spurious Free Dynamic Range at 15, Dither ON Third Order Intermoduation Distortion; 1MHz Tone Spacing, 2 Tones at 7 Equivaent Third Order Input Intercept Point, 2 Tone 7MHz Input (PGA = ) LTM91-AD 7MHz Input (PGA = 1) LTM91-AD 14MHz Input (PGA = ) LTM91-BA 14MHz Input (PGA = 1) LTM91-BA 162.5MHz Input (PGA = ) LTM91-AA 162.5MHz Input (PGA = 1) LTM91-AA 7MHz Input (PGA = ) LTM91-AD 7MHz Input (PGA = 1) LTM91-AD 14MHz Input (PGA = ) LTM91-BA 14MHz Input (PGA = 1) LTM91-BA 162.5MHz Input (PGA = ) LTM91-AA 162.5MHz Input (PGA = 1) LTM91-AA 9 7MHz Input (PGA = ) LTM91-AD 7MHz Input (PGA = 1) LTM91-AD 14MHz Input (PGA = ) LTM91-BA 14MHz Input (PGA = 1) LTM91-BA f IN = 162.5MHz LTM91-AA f IN = 7MHz LTM91-AD f IN = 14MHz LTM91-BA f IN = 162.5MHz LTM91-AA f IN = 7MHz LTM91-AD f IN = 14MHz LTM91-BA dbc dbc dbc dbc dbc dbc dbc dbc dbc dbc db db db dbm dbm dbm DIGITAL INPUTS AND OUTPUTS The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Encode Inputs (ENC +, ENC ) V ID Differentia Input Votage.2 V V ICM Common Mode Input Votage Internay Set 1.6 V Externay Set V R IN Input Resistance 1 Ω C IN Input Capacitance (Note 7) 3 pf 4 91fc

5 LTM91-Ax/LTM91-Bx DIGITAL INPUTS AND OUTPUTS The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Logic Inputs (DITH, PGA, ADCSHDN, RAND) V IH High Leve Input Votage V DD = 3.3V 2 V V IL Low Leve Input Votage V DD = 3.3V.8 V I IN Input Current V IN = V to V DD ±1 μa C IN Input Capacitance (Note 7) 1.5 pf Logic Inputs (AMPSHDN) V IH High Leve Input Votage V CC = 3.3V 2 V V IL Low Leve Input Votage V CC = 3.3V.8 V I IH Input High Current V IN = 2V 1.3 μa I IL Input Low Current V IN =.8V.1 μa C IN Input Capacitance (Note 7) 1.5 pf Logic Outputs (CMOS Mode) OV DD = 3.3V V OH High Leve Output Votage V DD = 3.3V, I O = 1μA V DD = 3.3V, I O = 2μA 3.1 V OL Low Leve Output Votage V DD = 3.3V, I O = 1μA V DD = 3.3V, I O = 1.6mA I SOURCE Output Source Current V OUT = V 5 ma I SINK Output Sink Current V OUT = 3.3V 5 ma OV DD = 2.5V V OH High Leve Output Votage V DD = 3.3V, I O = 2μA 2.49 V V OL Low Leve Output Votage V DD = 3.3V, I O = 1.6mA.1 V OV DD = 1.8V V OH High Leve Output Votage V DD = 3.3V, I O = 2μA 1.79 V V OL Low Leve Output Votage V DD = 3.3V, I O = 1.6μA.1 V Logic Outputs (LVDS Mode) Standard LVDS V OD Differentia Output Votage 1Ω Differentia Load mv V OS Output Common Mode Votage 1Ω Differentia Load V Low Power LVDS V OD Differentia Output Votage 1Ω Differentia Load mv V OS Output Common Mode Votage 1Ω Differentia Load V V V V V POWER REQUIREMENTS The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V DD ADC Anaog Suppy Votage (Note 8) V V CC Ampifi er Suppy Votage V I CC Ampifi er Suppy Current ma P SHDN Tota Shutdown Power AMPSHDN = ADCSHDN = 3.3V 1 mw 91fc 5

6 LTM91-Ax/LTM91-Bx POWER REQUIREMENTS The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Standard LVDS Output Mode OV DD Output Suppy Votage (Note 8) V I VDD Anaog Suppy Current LTM91-Ax LTM91-BA I OVDD Output Suppy Current 74 9 ma P DISS Power Dissipation LTM91-Ax LTM91-BA Low Power LVDS Output Mode OV DD Output Suppy Votage (Note 8) V I VDD Anaog Suppy Current LTM91-Ax LTM91-BA I OVDD Output Suppy Current 41 5 ma P DISS Power Dissipation LTM91-Ax LTM91-BA CMOS Output Mode OV DD Output Suppy Votage (Note 8) V I VDD Anaog Suppy Current LTM91-Ax LTM91-BA P DISS ADC Power Dissipation LTM91-Ax LTM91-BA P DISS(TOTAL) Tota Power Dissipation LTM91-Ax LTM91-BA ma ma mw mw ma ma mw mw ma ma mw mw mw mw TIMING CHARACTERISTICS The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f S Samping Frequency (Note 8) LTM91-Ax LTM91-BA t L ENC Low Time (Note 7) Duty Cyce Stabiizer Off (LTM91-Ax) Duty Cyce Stabiizer Off (LTM91-BA) Duty Cyce Stabiizer On (LTM91-Ax) Duty Cyce Stabiizer On (LTM91-BA) t H ENC High Time (Note 7) Duty Cyce Stabiizer Off (LTM91-Ax) Duty Cyce Stabiizer Off (LTM91-BA) Duty Cyce Stabiizer On (LTM91-Ax) Duty Cyce Stabiizer On (LTM91-BA) LVDS Output Mode (Standard and Low Power) t D ENC to DATA Deay (Note 7) ns t C ENC to CLKOUT Deay (Note 7) ns t SKEW DATA to CLKOUT Skew (t C t D ) (Note 7).6.6 ns t RISE Output Rise Time.5 ns t FALL Output Fa Time.5 ns Data Latency 7 Cyces MHz MHz ns ns ns ns ns ns ns ns 6 91fc

7 TIMING CHARACTERISTICS Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: A votage vaues are with respect to ground with GND and OGND wired together (uness otherwise noted). Note 3: Gain is measured from IN + /IN through the ADC. The ampifi er gain is attenuated by the fi ter, (See the typica performance characteristics section for IF Frequency Response ). Note 4: V CC = V DD = 3.3V, f SAMPLE = maximum sampe frequency, LVDS outputs, differentia ENC + /ENC = 2V P-P with 1.6V common mode, input LTM91-Ax/LTM91-Bx The denotes the specifi cations which appy over the fu operating temperature range, otherwise specifi cations are at T A = 25 C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CMOS Output Mode t D ENC to DATA Deay (Note 7) ns t C ENC to CLKOUT Deay (Note 7) ns t SKEW DATA to CLKOUT Skew (t C t D ) (Note 7).6.6 ns Data Latency Fu Rate CMOS Demuxed 7 7 Cyces Cyces range = 1 with PGA = with differentia drive, AC-couped inputs, uness otherwise noted. Note 5: Integra noninearity is defi ned as the deviation of a code from a best fi t straight ine to the transfer curve. The deviation is measured from the center of the quantization band. Note 6: Offset error is the votage appied between the IN + and IN pins required to make the output code f icker between and Note 7: Guaranteed by design, not subject to test. Note 8: Recommended operating conditions. 91fc 7

8 LTM91-Ax/LTM91-Bx TIMING DIAGRAM LVDS Output Mode Timing A Outputs are Differentia and Have LVDS Leves ANALOG INPUT N t H t AP N + 1 N + 2 N + 3 N + 4 t L ENC ENC + t D D-D15, OF N 7 N 6 N 5 N 4 N 3 CLKOUT + t C CLKOUT 91 TD1 Fu-Rate CMOS Output Mode Timing A Outputs are Singe-Ended and Have CMOS Leves t AP N + 1 N + 4 ANALOG INPUT N t H N + 2 N + 3 t L ENC ENC + t D DA-DA15, OFA N 7 N 6 N 5 N 4 N 3 CLKOUTA t C CLKOUTB DB-DB15, OFB HIGH IMPEDANCE 91 TD2 8 91fc

9 TIMING DIAGRAM Demutipexed CMOS Output Mode Timing A Outputs are Singe-Ended and Have CMOS Leves LTM91-Ax/LTM91-Bx t AP N + 1 N + 4 ANALOG INPUT N N + 2 N + 3 t H t L ENC ENC + t D DA-DA15, OFA N 8 N 6 N 4 t D DB-DB15, OFB N 7 N 5 N 3 CLKOUTA t C CLKOUTB 91 TD3 91fc 9

10 LTM91-Ax/LTM91-Bx TYPICAL PERFORMANCE CHARACTERISTICS (LTM91-AA).5 Differentia Non-Linearity (DNL) vs Output Code 5 Best Fit Integra Non-Linearity (INL) vs Output Code 9 Shorted Inputs Histogram with 13k Sampes DNL ERROR (LSB) INL ERROR (LSB) COUNT ADC OUTPUT CODE ADC OUTPUT CODE ADC OUTPUT CODE 91 G1 91 G2 91 G3 IMPEDANCE MAGNITUDE (Ω) Input Impedance vs Frequency 25 MAGNITUDE PHASE 45 IMPEDANCE PHASE (deg) FILTER GAIN (db) IF Frequency Response k Point FFT, f IN = 162.4MHz, 1, PGA =, RAND Off, Dither Off 91 G4 64k Point FFT, f IN = 162.4MHz, 1, PGA = 1, RAND Off, Dither Off G5 64k Point 2-Tone FFT, f IN = 161.5MHz, and 163.5MHz, 7, PGA =, RAND Off, Dither Off AMPLITUDE () HD3 HD2 AMPLITUDE () HD3 HD2 AMPLITUDE () G G G8 1 91fc

11 TYPICAL PERFORMANCE CHARACTERISTICS 64k Point 2-Tone FFT, f IN = 161.5MHz, and 163.5MHz, 15, PGA =, RAND Off, Dither Off 64k Point FFT, f IN = 162.4MHz, 15, PGA =, RAND Off, Dither Off LTM91-Ax/LTM91-Bx (LTM91-AA) 64k Point FFT, f IN = 162.4MHz, 15, PGA =, RAND Off, Dither On AMPLITUDE () AMPLITUDE () AMPLITUDE () SFDR (dbc AND ) G9 SFDR vs Input Leve, f IN = 162.4MHz, PGA =, RAND Off, Dither = Off SFDR dbc SFDR SFDR (dbc AND ) G1 SFDR vs Input Leve, f IN = 162.4MHz, PGA =, RAND Off, Dither = On SFDR dbc SFDR SFDR (dbc) AND SNR () G11 SFDR and SNR vs Sampe Rate, f IN = 162.4MHz, 1, PGA =, RAND Off, Dither Off SNR SFDR INPUT LEVEL () INPUT LEVEL () ADC SAMPLE RATE (Msps) G12 SFDR vs Input Common Mode Votage, f IN = 162.4MHz, 1, PGA = 91 G SFDR vs V CC Suppy Votage, f IN = 162.4MHz, 1, PGA = 91 G14 SFDR (dbc) SFDR (dbc) INPUT COMMON MODE VOLTAGE (V) V CC SUPPLY VOLTAGE (V) 91 G15 91 G16 91fc 11

12 LTM91-Ax/LTM91-Bx TYPICAL PERFORMANCE CHARACTERISTICS (LTM91-AD) DNL ERROR (LSB) Differentia Non-Linearity (DNL) vs Output Code OUTPUT CODE 91 G25 INL ERROR (LSB) Best Fit Integra Non-Linearity (INL) vs Output Code OUTPUT CODE 91 G26 SNR (db) SNR vs Frequency G27 IMPEDANCE MAGNITUDE (Ω) AMPLITUDE () Input Impedance vs Frequency MAGNITUDE PHASE k Point FFT, f IN = 7MHz, 1, PGA =, RAND Off, Dither Off HD2 HD3 91 G G IMPEDANCE PHASE (DEG) AMPLITUDE () AMPLITUDE () IF Frequency Response G29 64k Point 2-Tone FFT, f IN = 7MHz, and fi n = 74MHz, 7 Per Tone, PGA =, RAND Off, Dither Off G fc

13 TYPICAL PERFORMANCE CHARACTERISTICS (LTM91-BA) LTM91-Ax/LTM91-Bx DNL ERROR (LSB) Differentia Non-Linearity (DNL) vs Output Code OUTPUT CODE 91 G17 INL ERROR (LSB) Best Fit Integra Non-Linearity (INL) vs Output Code OUTPUT CODE 91 G18 SNR (db) SNR vs Frequency G19 IMPEDANCE MAGNITUDE (Ω) Input Impedance vs Frequency 4 MAGNITUDE 35 3 PHASE IMPEDANCE PHASE ( C) AMPLITUDE () IF Frequency Response G G21 AMPLITUDE () k Point FFT, f IN = 14MHz, 1, PGA =, RAND Off, Dither Off HD HD G22 AMPLITUDE () k Point FFT, f IN = 25MHz, 1, PGA =, RAND Off, Dither Off HD2 HD G23 AMPLITUDE () k Point 2-Tone FFT, f IN = 136MHz, 7 Per Tone, PGA =, RAND Off, Dither Off G24 91fc 13

14 LTM91-Ax/LTM91-Bx PIN FUNCTIONS Suppy Pins V CC (Pins E1, E2): 3.3V Anaog Suppy Pin for Ampifi er. The votage on this pin provides power for the ampifier stage ony and is internay bypassed to GND. V DD (Pins E5, D5): 3.3V Anaog Suppy Pin for ADC. This suppy is internay bypassed to GND. OV DD (Pins A6, G9): Positive Suppy for the ADC Output Drivers. This suppy is internay bypassed to OGND. GND (Pins A1, A2, A4, B2, B4, C2, C4, D1, D2, D4, E4, F1, F2, F4, G2, G4, H2, H4, J1, J2, J4): Anaog Ground. OGND (Pins A5, A9, G8, J9): ADC Output Driver Ground. Anaog Inputs IN + (Pin G1): Positive (Non-Inverting) Ampifi er Input. IN (Pin H1): Negative (Inverting) Ampifi er Input. DNC (Pins C3, D3): Do Not Connect. These pins are used for testing and shoud not be connected on the PCB. They may be sodered to unconnected pads and shoud be we isoated. The DNC pins connect to the signa path prior to the ADC inputs; therefore, care shoud be taken to keep other signas away from these sensitive nodes. ENC + (Pin C1): Positive Differentia Encode Input. The samped anaog input is hed on the rising edge of ENC +. This input is internay biased to 1.6V through a 6.2k resistor. Output data can be atched on the rising edge of ENC +. The Encode pins have a differentia 1Ω input impedance. ENC (Pin B1): Negative Differentia Encode Input. The samped anaog input is hed on the faing edge of ENC. This input is internay biased to 1.6V through a 6.2k resistor. Bypass to ground with a.1μf capacitor for a singe-ended encode signa. The encode pins have a differentia 1Ω input impedance. Contro Inputs SENSE (Pin J3): Reference Mode Seect and Externa Reference Input. Tie SENSE to V DD to seect the interna 2.5V bandgap reference. An externa reference of 2.5V or 1.25V may be used; both reference vaues wi set the maximum fu-scae input range. 14 AMPSHDN (Pin H3): Power Shutdown Pin for Ampifier. This pin is a ogic input referenced to anaog ground. AMPSHDN = ow resuts in norma operation. AMPSHDN = high resuts in powered down ampifier with typicay 3mA ampifier suppy current. MODE (Pin G3): Output Format and Cock Duty Cyce Stabiizer Seection Pin. Connecting MODE to V seects offset binary output format and disabes the cock duty cyce stabiizer. Connecting MODE to 1/3V DD seects offset binary output format and enabes the cock duty cyce stabiizer. Connecting MODE to 2/3V DD seects 2 s compement output format and enabes the cock duty cyce stabiizer. Connecting MODE to V DD seects 2 s compement output format and disabes the cock duty cyce stabiizer. RAND (Pin F3): Digita Output Randomization Seection Pin. RAND = ow resuts in norma operation. RAND = high seects D1 to D15 to be EXCLUSIVE-ORed with D (the LSB). The output can be decoded by again appying an XOR operation between the LSB and a other bits. This mode of operation reduces the effects of digita output interference. PGA (Pin E3): Programmabe Gain Ampifier Contro Pin. PGA = ow seects the norma (maximum) input votage range. PGA = high seects a 3.5dB reduced input range for sighty better distortion performance at the expense of SNR. ADCSHDN (Pin B3): Power Shutdown Pin for ADC. ADCSHDN = ow resuts in norma operation. ADCSHDN = high resuts in powered down anaog circuitry and the digita outputs are paced in a high impedance state. DITH (Pin A3): Interna Dither Enabe Pin. DITH = ow disabes interna dither. DITH = high enabes interna dither. Refer to Interna Dither section of this data sheet for detais on dither operation. LVDS (Pin F5): Data Output Mode Seect Pin. Connecting LVDS to V seects fu rate CMOS mode. Connecting LVDS to 1/3V DD seects demutipexed CMOS mode. Connecting LVDS to 2/3V DD seects ow power LVDS mode. Connecting LVDS to V DD seects standard LVDS mode. 91fc

15 PIN FUNCTIONS Digita Outputs For CMOS Mode, Fu Rate or Demutipexed DA to DA15 (Pins E9 to H5): Digita Outputs, A Bus. DA15 is the MSB. Output bus for fu rate CMOS mode and demutipexed mode. CLKOUTA (Pin E8): Inverted Data Vaid Output. CLKOUTA wi togge at the sampe rate in fu rate CMOS mode or at 1/2 the sampe rate in demutipexed mode. Latch the data on the rising edge of CLKOUTA. OFB (Pin E6): Overf ow/underf ow Digita Output for the B Bus. OFB is high when an overfow or underfow has occurred on the B bus. OFB is in a high impedance state in fu rate CMOS mode. DB to DB15 (Pins B5 to D9): Digita Outputs, B Bus. DB15 is the MSB. Active in demutipexed mode. The B bus is in a high impedance state in fu rate CMOS mode. LTM91-Ax/LTM91-Bx CLKOUTB (Pin E7): Data Vaid Output. CLKOUTB wi togge at the sampe rate in fu rate CMOS mode or at 1/2 the sampe rate in demutipexed mode. Latch the data on the faing edge of CLKOUTB. OFA (Pin G5): Overfow/Underfow Digita Output for the A Bus. OFA is high when an overfow or underf ow has occurred on the A bus. For LVDS Mode, Standard or Low Power D /D + to D15 /D15 + (Pins B5 to G6): LVDS Digita Outputs. A LVDS outputs require differentia 1Ω termination resistors at the LVDS receiver. D15 + /D15 is the MSB. CLKOUT /CLKOUT + (Pins E6, E7): LVDS Data Vaid Output. Latch data on the rising edge of CLKOUT +, faing edge of CLKOUT. OF /OF + (Pins H5, G5): Overfow/Underfow Digita Output. OF is high when an over or under fow has occurred. Pin Confi guration (LVDS Outputs/CMOS Outputs) J GND GND SENSE GND D14 + /DA12 D14 /DA11 D12 + /DA8 D12 /DA7 OGND H IN GND AMPSHDN GND OF /DA15 D15 /DA13 D13 /DA9 D11 /DA5 D11 + /DA6 G IN + GND MODE GND OF + /OFA D15 + /DA14 D13 + /DA1 OGND OV DD F GND GND RAND GND LVDS D9 /DA1 D9 + /DA2 D1 /DA3 D1 + /DA4 E V CC V CC PGA GND V DD CLKOUT /OFB CLKOUT + /CLKOUTB D8 /CLKOUTA D8 + /DA D GND GND DNC GND V DD D6 /DB12 D6 + /DB13 D7 /DB14 D7 + /DB15 C ENC + GND DNC GND D + /DB1 D4 /DB8 D4 + /DB9 D5 /DB1 D5 + /DB11 B ENC GND ADCSHDN GND D /DB D1 /DB2 D1 + /DB3 D3 + /DB7 D3 /DB6 A GND GND DITH GND OGND OV DD D2 /DB4 D2+/DB5 OGND Top View of LGA Pinout (Looking Through Component) ALL ELSE = GND CONTROL 1 TOP VIEW DATA J IN H IN + G F V CC E DNC D ENC + C ENC B A OGND OV DD OGND CONTROL V DD OGND OV DD 91 LGA1 91fc 15

16 LTM91-Ax/LTM91-Bx FUNCTIONAL BLOCK DIAGRAM V CC IN + IN AMPSHDN SENSE INPUT AMPLIFIER ANTI-ALIAS FILTER INPUT S/H DITHER SIGNAL GENERATOR VOLTAGE REFERENCE PGA ADC REFERENCE RANGE SELECT PGA GND FIRST PIPELINED ADC STAGE SECOND PIPELINED ADC STAGE THIRD PIPELINED ADC STAGE FOURTH PIPELINED ADC STAGE FIFTH PIPELINED ADC STAGE SHIFT REGISTER AND ERROR CORRECTION INTERNAL CLOCK SIGNALS DIFFERENTIAL INPUT LOW JITTER CLOCK DRIVER CONTROL LOGIC OUTPUT DRIVERS 1Ω ENC + ENC ADC- SHDN RAND MODE LVDS DITH OGND 91 BD V DD OV DD D15± D± CLKOUT + CLKOUT OF + OF 16 91fc

17 OPERATION DYNAMIC PERFORMANCE DEFINITIONS Signa-to-Noise Pus Distortion Ratio The signa-to-noise pus distortion ratio [S/(N+D)] is the ratio between the RMS ampitude of the fundamenta input frequency and the RMS ampitude of a other frequency components at the ADC output. Signa-to-Noise Ratio The signa-to-noise (SNR) is the ratio between the RMS ampitude of the fundamenta input frequency and the RMS ampitude of a other frequency components, except the first fi ve harmonics. Tota Harmonic Distortion Tota harmonic distortion is the ratio of the RMS sum of a harmonics of the input signa to the fundamenta itsef. The out-of-band harmonics aias into the frequency band between DC and haf the samping frequency. THD is expressed as: THD= 2Log (V2 2 + V3 2 + V Vn 2 )/V1 where V1 is the RMS ampitude of the fundamenta frequency and V2 through Vn are the ampitudes of the second through nth harmonics. Intermoduation Distortion If the input signa consists of more than one spectra component, the transfer function noninearity can produce intermoduation distortion (IMD) in addition to THD. IMD is the change in one sinusoida input caused by the presence of another sinusoida input at a different frequency. If two pure sine waves of frequencies fa and fb are appied to the input, noninearities in the transfer function can create LTM91-Ax/LTM91-Bx distortion products at the sum and difference frequencies of mfa ± nfb, where m and n =, 1, 2, 3, etc. For exampe, the 3rd order IMD terms incude (2fa + fb), (fa + 2fb), (2fa fb) and (fa 2fb). The 3rd order IMD is defined as the ration of the RMS vaue of either input tone to the RMS vaue of the argest 3rd order IMD product. Spurious Free Dynamic Range (SFDR) The ratio of the RMS input signa ampitude to the RMS vaue of the peak spurious spectra component expressed in dbc. SFDR may aso be cacuated reative to fu-scae and expressed in. Aperture Deay Time Aperture deay is the time from when a rising ENC + equas the ENC votage to the instant that the input signa is hed by the sampe and-hod circuit. Aperture Deay Jitter The variation in the aperture deay time from conversion to conversion. This random variation wi resut in noise when samping an AC input. The signa to noise ratio due to the jitter aone wi be: SNR JITTER = 2og (2π f IN t JITTER ) DESCRIPTION The LTM91 is an integrated system in a package (SiP) μmodue receiver that incudes a high-speed, samping 16-bit A/D converter, matching network, anti-aiasing fiter and a ow noise, differentia ampifier with fixed gain. It is designed for digitizing high frequency, wide dynamic range signas with an intermediate frequency (IF) range up to 3MHz. 91fc 17

18 LTM91-Ax/LTM91-Bx OPERATION The foowing sections describe in further detai the functiona operation of the LTM91. The SiP technoogy aows the LTM91 to be customized and this is described in the fi rst section. The remaining outine foows the basic functiona eements as shown in Figure AMPLIFIER ADC INPUT NETWORK ADC Figure 1. Basic Functiona Eements Tabe 1. Semi-Custom Options AMPLIFIER IF RANGE 91 F1 SEMI-CUSTOM OPTIONS The μmodue construction affords a new eve of fexibiity in appication-specific standard products. Standard ADC and ampifier components can be integrated regardess of their process technoogy and matched with passive components to a particuar appication. The LTM91-AA, as the first exampe, is configured with a 16-bit ADC samping at rates up to 13Msps. The ampifier gain is 2dB with an input impedance of 2Ω and an input range of 233mV P-P. The matching network is designed to optimize the interface between the ampifier output and the ADC under these conditions. Additionay, there is a 2-poe bandpass fi ter designed for 162.5MHz ±25MHz. However, other options are possibe through Linear Technoogy s semi-custom deveopment program. Linear AMPLIFIER INPUT IMPEDANCE AMPLIFIER GAIN FILTER Technoogy has in pace a program to deiver other speed, resoution, IF range, gain and fi ter configurations for a wide range of appications. See Tabe 1 for the LTM91-AA configuration and potentia options. These semi-custom designs are based on existing ADCs and ampifiers with an appropriatey modified matching network. The fi na subsystem is then tested to the exact parameters defined for the appication. The fina resut is a fuy integrated, accuratey tested and reiabe soution. For more detais on the semi-custom receiver subsystem program, contact Linear Technoogy. Note that not a combinations of options in Tabe 1 are possibe at this time and specified performance may differ significanty from existing vaues. This data sheet discusses devices with LVDS and CMOS outputs. The ower speed options that ony support CMOS outputs are avaiabe on a separate data sheet. The CMOS-ony options have a different pin assignment. AMPLIFIER INFORMATION The ampifiers used in the LTM91 are ow noise and ow distortion fuy differentia ADC drivers. The ampifiers are very fexibe in terms of I/O couping. They can be AC- or DC-couped at the inputs. Users are advised to keep the input common mode votage between 1V and 1.6V for proper operation. If the inputs are AC-couped, the input common mode votage is automaticay biased. The input signa can be either singe-ended or differentia with amost no difference in distortion performance. ADC SAMPLE RATE ADC RESOLUTION OUTPUT PART NUMBER 3MHz 2Ω 2dB 162.5MHz BPF, 5MHz BW 13Msps 16-bit LVDS/CMOS LTM91-AA 3MHz 2Ω 14dB 7MHz BPF, 25MHz BW 13Msps 16-bit LVDS/CMOS LTM91-AD 3MHz 4Ω 8dB DC-3MHz LPF 16Msps 16-bit LVDS/CMOS LTM91-BA Seect Combination of Options from Coumns Beow DC-3MHz 5Ω 26dB LPF TBD 16Msps 16-bit LVDS/CMOS DC-14MHz 2Ω 2dB BPF TBD 13Msps 14-bit LVDS/CMOS DC-7MHz 2Ω 14dB 15Msps CMOS DC-35MHz 4Ω 8dB 8Msps CMOS 2Ω 6dB 65Msps CMOS 4Msps CMOS 25Msps CMOS 1Msps CMOS 91fc

19 LTM91-Ax/LTM91-Bx OPERATION ADC INPUT NETWORK The passive network between the ampifier output stage and the ADC input stage can be confi gured for bandpass or owpass response with different cutoff frequencies and bandwidths. The LTM91-AA, for exampe, impements a 2-poe bandpass fi ter centered at 162.5MHz with 5MHz bandwidth. Note that the fiter attenuates the signa at 162.5MHz by 1dB, making the overa gain of the subsystem 19dB. For production test purposes the fiter is designed to aow DC inputs into the ADC. CONVERTER INFORMATION The anaog-to-digita converter (ADC) is a CMOS pipeined mutistep converter with a front-end PGA. As shown in the Functiona Bock Diagram, the converter has five pipeined ADC stages; a samped anaog input wi resut in a digitized vaue seven cyces ater (see the Timing Diagram section). The encode input is differentia for improved common mode noise immunity. APPLICATIONS INFORMATION INPUT SPAN The LTM91 is confi gured with a fixed input span and input impedance. With the ampifier gain and the ADC input network described above for LTM91-AA, the fuscae input range of the driver circuit is 233mV P-P. The recommended ADC input span is achieved by tying the SENSE pin to V DD. However, the ADC input span can be changed by appying a DC votage to the SENSE pin. Input Impedance and Matching The differentia input impedance of the LTM91 can be 5Ω, 2Ω or 4Ω. In some appications the differentia inputs may need to be terminated to a ower vaue impedance, e.g. 5Ω, in order to provide an impedance match for the source. Severa choices are avaiabe. One approach is to use a differentia shunt resistor (Figure 2). Another approach is to empoy a wide band transformer (Figure 3). Both methods provide a wide band match. The termination resistor or the transformer must be paced cose to the input pins in order to minimize the refection due to input mismatch. Tabe 2. Differentia Ampifi er Input Termination Vaues Z IN R T FIG 2 4Ω 57Ω 2Ω 66.5Ω 5Ω None Ω V IN 25Ω 25Ω V IN 25Ω IN + R T IN IN + IN Z IN /2 Z IN /2 R F R F LTM91 91 F2 Figure 2. Input Termination for Differentia 5Ω Input Impedance Using Shunt Resistor (See Tabe 2 for R T Vaues) Z IN /2 R F LTM91 Z IN /2 R F 91 F3 Figure 3. Input Termination for Differentia 5Ω Input Impedance Using a Wideband Transformer 91fc 19

20 LTM91-Ax/LTM91-Bx APPLICATIONS INFORMATION Aternativey, one coud appy a narrowband impedance match at the inputs for frequency seection and/or noise reduction. R S 5Ω.1μF IN + Z IN /2 R F LTM91 Referring to Figure 4, ampifi er inputs can be easiy confi gured for singe-ended input without a baun. The signa is fed to one of the inputs through a matching network whie the other input is connected to the same impedance. In genera, the singe-ended input impedance and termination resistor R T are determined by the combination of R S, Z IN /2 and R F. + V IN.1μF R T R S /R T.1μF IN Z IN /2 R F 91 F4 Tabe 3. Singe-Ended Ampifi er Input Termination Vaues Z IN R T FIG 4 4Ω 59Ω 2Ω 68.5Ω 5Ω 15Ω The LTM91 ampifier is stabe with a source impedances. The overa differentia gain is affected by the source impedance in Figure 5: A V = V OUT /V IN = (1/(R S + Z IN /2)) The noise performance of the ampifier aso depends upon the source impedance and termination. For exampe, an input 1:4 transformer in Figure 3 improves the input noise figure by adding 6dB votage gain at the inputs. Reference and SENSE Pin Operation Figure 6 shows the converter reference circuitry consisting of a 2.5V bandgap reference, a programmabe gain ampifier and contro circuit. There are three modes of reference operation: interna reference, 1.25V externa reference or 2.5V externa reference. To use the interna reference, + Figure 4. Input Termination for Differentia 5Ω Input Impedance Using Shunt Resistor R s /2 V IN R s /2 IN + R T IN Z IN /2 Z IN /2 91 F5 Figure 5. Cacuate Differentia Gain R F R F LTM91 tie the SENSE pin to V DD. To use an externa reference, simpy appy either a 1.25V or 2.5V reference votage to the SENSE input pin. Both 1.25V and 2.5V appied to SENSE wi resut in the maximum fu-scae range. TIE TO V DD TO USE INTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 2.5V REFERENCE OR INPUT FOR EXTERNAL 1.25V REFERENCE SENSE RANGE SELECT AND GAIN CONTROL PGA INTERNAL ADC REFERENCE 2.5V BANDGAP REFERENCE 91 F6 2 Figure 6. Reference Circuit 91fc

21 LTM91-Ax/LTM91-Bx APPLICATIONS INFORMATION PGA Pin The PGA pin seects between two gain settings for the ADC front-end. PGA = ow seects the maximum input span; PGA = high seects a 3.5dB ower input span. The high input range has the best SNR. For appications with high inearity requirements, the ow input range wi have improved distortion; however, the SNR wi be 1.8dB worse. See the Typica Performance Characteristics section. Driving the Encode Inputs The noise performance of the converter can depend on the encode signa quaity as much as the anaog input. The encode inputs are intended to be driven differentiay, primariy for noise immunity from common mode noise sources. Each input is biased through a 6k resistor to a 1.6V bias. The bias resistors set the DC operating point for transformer couped drive circuits and can set the ogic threshod for singe-ended drive circuits. Any noise present on the encode signa wi resut in additiona aperture jitter that wi be RMS summed with the inherent ADC aperture jitter. In appications where jitter is critica (high input frequencies), take the foowing into consideration: 1. Differentia drive shoud be used. 2. Use the argest ampitude possibe. If using transformer couping, use a higher turns ratio to increase the ampitude. 3. If the ADC is cocked with a fixed frequency sinusoida signa, fiter the encode signa to reduce wideband noise. 4. Baance the capacitance and series resistance at both encode inputs such that any couped noise wi appear at both inputs as common mode noise. The encode inputs have a common mode range of 1.2V to V DD. Each input may be driven from ground to V DD for singe-ended drive. The encode cock inputs have a differentia 1Ω input impedance. For 5Ω inputs e.g. signa generators, an additiona 1Ω impedance wi provide an impedance match, as shown in Figure 7b. Maximum and Minimum Encode Rates The maximum encode rate for the LTM91-Ax is 13Msps and 16Msps for LTM91-BA. For the ADC to operate propery the encode signa shoud have a 5% (±5%) duty cyce. Each haf cyce must have at east 3.65ns (LTM91-Ax, or 2.97ns for LTM91-BA) for the ADC interna circuitry to have enough setting time for proper operation. Achieving a precise 5% duty cyce is easy with differentia sinusoida drive using a transformer or using symmetric differentia ogic such as PECL or LVDS. When using a singe-ended encode signa asymmetric rise and fa times can resut in duty cyces that are far from 5%. LTM91 V DD V DD 1.6V TO INTERNAL ADC CLOCK DRIVERS.1μF LTM91 ENC + ENC + 6k T1 5Ω 8.2pF 1Ω 1Ω V DD 1.6V.1μF 5Ω ENC 6k.1μF ENC 91 F7b T1 = M/A-COM ETC F7a Figure 7a. Equivaent Encode Input Circuit Figure 7b. Transformer Driven Encode 91fc 21

22 LTM91-Ax/LTM91-Bx APPLICATIONS INFORMATION An optiona cock duty cyce stabiizer can be used if the input cock does not have a 5% duty cyce. This circuit uses the rising edge of ENC to sampe the anaog input. The faing edge of ENC is ignored and an interna faing edge is generated by a phase-ocked oop. The input cock duty cyce can vary from 3% to 7% and the cock duty cyce stabiizer wi maintain a constant 5% interna duty cyce. If the cock is turned off for a ong period of time, the duty cyce stabiizer circuit wi require one hundred cock cyces for the PLL to ock onto the input cock. To use the cock duty cyce stabiizer, the MODE pin must be connected to 1/3V DD or 2/3V DD using externa resistors. The ower imit of the sampe rate is determined by the droop of the sampe and hod circuits. The pipeined architecture of this ADC reies on storing anaog signas on sma vaued capacitors. Junction eakage wi discharge the capacitors. The specified minimum operating frequency for the LTM91 is 1Msps. V THRESHOLD = 1.6V.1μF ENC + 1.6V ENC LTM91 91F8 Figure 8. Singe-Ended ENC Drive, Not Recommended for Low Jitter DIGITAL OUTPUTS Digita Output Modes The LTM91 can operate in four digita output modes: standard LVDS, ow power LVDS, fu rate CMOS, and demutipexed CMOS. The LVDS pin seects the mode of operation. This pin has a four eve ogic input, centered at, 1/3V DD, 2/3V DD and V DD. An externa resistive divider can be used to set the 1/3V DD and 2/3V DD ogic eves. Tabe 4 shows the ogic states for the LVDS pin. Tabe 4. LVDS Pin Function LVDS DIGITAL OUTPUT MODE V(GND) Fu-Rate CMOS 1/3V DD Demutipexed CMOS 2/3V DD Low Power LVDS LVDS V DD Digita Output Buffers (CMOS Modes) Figure 1 shows an equivaent circuit for a singe output buffer in CMOS mode, fu-rate or demutipexed. Each buffer is powered by OV DD and OGND, isoated from the ADC power and ground. The additiona N-channe transistor in the output driver aows operation down to ow votages. The interna resistor in series with the output makes the output appear as 5Ω to externa circuitry and eiminates the need for externa damping resistors. LTM91 3.3V V DD V DD OV DD.5V TO 3.6V MC1LVELT22 D 3.3V 261Ω Q 261Ω ENC + ENC LTM91 1Ω DATA FROM LATCH PREDRIVER LOGIC OV DD 43Ω TYPICAL DATA OUTPUT Q 165Ω 165Ω OGND 91 F9 91 F1 Figure 9. ENC Drive Using a CMOS to PECL Transator Figure 1. Equivaent Circuit for a Digita Output Buffer 22 91fc

23 LTM91-Ax/LTM91-Bx APPLICATIONS INFORMATION As with a high speed/high resoution converters, the digita output oading can affect the performance. The digita outputs of the LTM91 shoud drive a minimum capacitive oad to avoid possibe interaction between the digita outputs and sensitive input circuitry. The output shoud be buffered with a device such as an ALVCH16373 CMOS atch. For fu speed operation the capacitive oad shoud be kept under 1pF. A resistor in series with the output may be used but is not required since the ADC has a series resistor of 43Ω on chip. Lower OV DD votages wi aso hep reduce interference from the digita outputs. Digita Output Buffers (LVDS Modes) Figure 11 shows an equivaent circuit for an LVDS output pair. A 3.5mA current is steered from OUT + to OUT or vice versa, which creates a ±35mV differentia votage across the 1Ω termination resistor at the LVDS receiver. A feedback oop reguates the common mode output votage to 1.2V. For proper operation each LVDS output pair must be terminated with an externa 1Ω termination resistor, even if the signa is not used (such as OF + /OF or CLKOUT + /CLKOUT ). To minimize noise the PC board traces for each LVDS output pair shoud be routed cose together. To minimize cock skew a LVDS PC board traces shoud have about the same ength. In ow power LVDS mode 1.75mA is steered between the differentia outputs, resuting in ±175mV at the LVDS receiver s 1Ω termination resistor. The output common mode votage is 1.2V, the same as standard LVDS mode. Data Format The LTM91 parae digita output can be seected for offset binary or 2 s compement format. The format is seected with the MODE pin. This pin has a four eve ogic input, centered at, 1/3V DD, 2/3V DD and V DD. An externa resistive divider can be used to set the 1/3V DD and 2/3V DD ogic eves. Tabe 5 shows the ogic states for the MODE pin. Tabe 5. MODE Pin Function MODE OUTPUT FORMAT CLOCK DUTY CYCLE STABILIZER V(GND) Offset Binary Off 1/3V DD Offset Binary On 2/3V DD 2 s Compement On V DD 2 s Compement Off Overfow Bit An overfow output bit (OF) indicates when the converter is overranged or underranged. In CMOS mode, a ogic high on the OFA pin indicates an overfow or underfow on the A data bus, whie a ogic high on the OFB pin indicates an overfow on the B data bus. In LVDS mode, a differentia ogic high on OF + /OF pins indicates an overfow or underfow. LTM91 3.5mA OV DD 3.3V V DD V DD OV DD 43Ω DATA FROM LATCH PREDRIVER LOGIC 1k 1k OV DD 1Ω LVDS RECEIVER 43Ω 1.2V + OGND 91 F11 Figure 11. Equivaent Output Buffer in LVDS Mode 91fc 23

24 LTM91-Ax/LTM91-Bx APPLICATIONS INFORMATION Output Cock LTM91 The ADC has a deayed version of the encode input avaiabe as a digita output, CLKOUT. The CLKOUT pin can be used to synchronize the converter data to the digita system. This is necessary when using a sinusoida encode. CLKOUT OF CLKOUT OF In both CMOS modes, A bus data wi be updated as CLK- OUTA fas and CLKOUTB rises. In demutipexed CMOS mode the B bus data wi be updated as CLKOUTA fas and CLKOUTB rises. In fu rate CMOS mode, ony the A data bus is active; data may be atched on the rising edge of CLKOUTA or the faing edge of CLKOUTB. In demutipexed CMOS mode CLKOUTA and CLKOUTB wi togge at 1/2 the frequency of the encode signa. Both the A bus and the B bus may be atched on the rising edge of CLKOUTA or the faing edge of CLKOUTB. RAND = HIGH, RANDOMIZER ENABLED RAND D D15 D14 D2 D1 D15/D D14/D D2/D D1/D D Digita Output Randomizer Interference from the ADC digita outputs is sometimes unavoidabe. Interference from the digita outputs may be from capacitive or inductive couping or couping through the ground pane. Even a tiny couping factor can resut in discernibe unwanted tones in the ADC output spectrum. By randomizing the digita output before it is transmitted off chip, these unwanted tones can be randomized, trading a sight increase in the noise foor for a arge reduction in unwanted tone ampitude. The digita output is randomized by appying an excusive- OR ogic operation between the LSB and a other data output bits. To decode, the reverse operation is appied; that is, an excusive-or operation is appied between the LSB and a other bits. The LSB, OF and CLKOUT output are not affected. The output randomizer function is active when the RAND pin is high. Output Driver Power Separate output power and ground pins aow the output drivers to be isoated from the anaog circuitry. The power suppy for the digita output buffers, OV DD, shoud be tied to the same power suppy as for the ogic being driven. For 24 Figure 12. Functiona Equivaent of Digita Output Randomizer PC BOARD LTM91 CLKOUT OF D15 D D14 D D2 D D1 D D FPGA 91 F12 Figure 13. Derandomizing a Randomized Digita Output D15 D14 D2 D1 D 91 F13 91fc

25 LTM91-Ax/LTM91-Bx APPLICATIONS INFORMATION exampe, if the converter is driving a DSP powered by a 1.8V suppy, then OV DD shoud be tied to that same 1.8V suppy. OV DD can be powered with any ogic votage up to the 3.6V. OGND can be powered with any votage from ground up to 1V and must be ess than OV DD. The ogic outputs wi swing between OGND and OV DD. Interna Dither The LTM91 is a 16-bit receiver subsystem with a very inear transfer function; however, at ow input eves even sight imperfections in the transfer function wi resut in unwanted tones. Sma errors in the transfer function are usuay a resut of ADC eement mismatches. An optiona interna dither mode can be enabed to randomize the input ocation on the ADC transfer curve, resuting in improved SFDR for ow signa eves. As shown in Figure 14, the output of the sampe-and-hod ampifi er is summed with the output of a dither DAC. The dither DAC is driven by a ong sequence pseudo-random number generator; the random number fed to the dither DAC is aso subtracted from the ADC resut. If the dither DAC is precisey caibrated to the ADC, very itte of the dither signa wi be seen at the output. The dither signa that does eak through wi appear as white noise. The dither DAC wi cause a sma eevation in the noise foor of the ADC, as compared to the noise foor with dither off. For best noise performance with the dither signa on, the driving impedance connected across pins IN + /IN shoud cosey match that of the modue (see Tabe 1). A source impedance that is resistive and matches that of the modue within 1% wi give the best resuts. Suppy Sequencing The V CC pin provides the suppy to the ampifier and the V DD pin provides the suppy to the ADC. The ampifier and the ADC are separate integrated circuits within the LTM91; however, there are no suppy sequencing considerations beyond standard practice. It is recommended that the ampifier and ADC both use the same ow noise, 3.3V suppy, but the ampifi er may be operated from a ower votage eve if desired. Both devices can operate from the same 3.3V inear reguator but pace a ferrite bead between the V CC and V DD pins. Separate inear reguators can be used without additiona suppy sequencing circuitry if they have common input suppies. LTM91 IN + IN S/H AMP 16-BIT PIPELINED ADC CORE DIGITAL SUMMATION OUTPUT DRIVERS CLKOUT OF D15 D CLOCK/DUTY CYCLE CONTROL PRECISION DAC MULTIBIT DEEP PSEUDO-RANDOM NUMBER GENERATOR 91 F14 ENC + ENC DITH DITHER ENABLE HIGH = DITHER ON LOW = DITHER OFF Figure 14. Functiona Equivaent Bock Diagram of Interna Dither Circuit 91fc 25

26 LTM91-Ax/LTM91-Bx APPLICATIONS INFORMATION Grounding and Bypassing The LTM91 requires a printed circuit board with a cean unbroken ground pane; a mutiayer board with an interna ground pane is recommended. The pinout of the LTM91 has been optimized for a f ow-through ayout so that the interaction between inputs and digita outputs is minimized. A continuous row of ground pads faciitate a ayout that ensures that digita and anaog signa ines are separated as much as possibe. The LTM91 is internay bypassed with the ampifier (V CC ) and ADC (V DD ) suppies returning to a common ground (GND). The digita output suppy (V DD ) is returned to OGND. Additiona bypass capacitance is optiona and may be required if power suppy noise is signifi cant. The differentia inputs shoud run parae and cose to each other. The input traces shoud be as short as possibe to minimize capacitance and to minimize noise pickup. Heat Transfer Most of the heat generated by the LTM91 is transferred through the bottom-side ground pads. For good eectrica and therma performance, it is critica that a ground pins are connected to a ground pane of sufficient area with as many vias as possibe. Recommended Layout The high integration of the LTM91 makes the PC board ayout very simpe and easy. However, to optimize its eectrica and therma performance, some ayout considerations are sti necessary, see Figures Use arge PCB copper areas for ground. This heps to dissipate heat in the package through the board and aso heps to shied sensitive on-board anaog signas. Common ground (GND) and output ground (OGND) are eectricay isoated on the LTM91, but can be connected on the PCB underneath the part to provide a common return path. Use mutipe ground vias. Using as many vias as possibe heps to improve the therma performance of the board and creates necessary barriers separating anaog and digita traces on the board at high frequencies. Separate anaog and digita traces as much as possibe, using vias to create high-frequency barriers. This wi reduce digita feedback that can reduce the signa-to-noise ratio (SNR) and dynamic range of the LTM91. The quaity of the paste print is an important factor in producing high yied assembies. It is recommended to use a type 3 or 4 printing no-cean soder paste. The soder stenci design shoud foow the guideines outined in Appication Note 1. The LTM91 empoys god-finished pads for use with Pb-based or tin-based soder paste. It is inherenty Pb-free and compies with the JEDEC (e4) standard. The materias decaration is avaiabe onine at com/designtoos/eadfree/mat_dec.jsp fc

27 APPLICATIONS INFORMATION LTM91-Ax/LTM91-Bx Figure 15. Layer 1 Figure 16. Layer 2 Figure 17. Layer 3 Figure 18. Layer 4 91fc 27

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