LTC Bit Σ ADC with Easy Drive Input Current Cancellation and I 2 C Interface. Applications. Typical Application

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1 Features n Easy Drive Technoogy Enabes Rai-to-Rai Inputs with Zero Differentia Input Current n Directy Digitizes High Impedance Sensors with Fu Accuracy n Programmabe Gain from to 256 n GND to V CC Input/Reference Common Mode Range n 2-Wire I 2 C Interface n Programmabe 5Hz, 6Hz or Simutaneous 5Hz/6Hz Rejection Mode n 2ppm (.25LSB) INL, No Missing Codes n ppm Offset and 5ppm Fu-Scae Error n Seectabe 2x Speed Mode n No Latency: Digita Fiter Settes in a Singe Cyce n Singe Suppy 2.7V to 5.5V Operation n Interna Osciator n Six Addresses Avaiabe and One Goba Address for Synchronization n Avaiabe in a Tiny (3mm 3mm) -Lead DFN Package Appications n Direct Sensor Digitizer n Weight Scaes n Direct Temperature Measurement n Strain Gauge Transducers n Instrumentation n Industria Process Contro n DVMs and Meters LTC248 6-Bit Σ ADC with Easy Drive Input Current Canceation and I 2 C Interface Description The LTC 248 combines a 6-bit pus sign No Latency Σ anaog-to-digita converter with patented Easy Drive technoogy and I 2 C digita interface. The patented samping scheme eiminates dynamic input current errors and the shortcomings of on-chip buffering through automatic canceation of differentia input current. This aows arge externa source impedances and input signas, with rai-torai input range to be directy digitized whie maintaining exceptiona DC accuracy. The LTC248 incudes on-chip programmabe gain and an osciator. The LTC248 can be configured through an I 2 C interface to provide a programmabe gain from to 256 in 8 steps, to digitize an externa signa or interna temperature sensor, reject ine frequencies (5Hz, 6Hz or simutaneous 5Hz/6Hz) as we as a 2x speed-up mode. The LTC248 aows a wide common mode input range (V to V CC ) independent of the reference votage. The reference can be as ow as mv or can be tied directy to V CC. The LTC248 incudes an on-chip trimmed osciator eiminating the need for externa crystas or osciators. Absoute accuracy and ow drift are automaticay maintained through continuous, transparent, offset and fu-scae caibration. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks and No Latency and Easy Drive are trademarks of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Patents Pending. Typica Appication +FS Error vs R SOURCE at IN + and IN 8 VCC = 5V SENSE.µF k I DIFF = k.µf V IN + V IN V CC REF + V CC LTC248 GND REF µf SCL SDA CA/f CA 248 TAa 2-WIRE I 2 C INTERFACE 6 ADDRESSES +FS ERROR (ppm) V IN + = 3.75V V IN =.25V f O = GND C IN = µf 8 For more information k k k R SOURCE (Ω) 248 TAb 248fd

2 LTC248 Absoute Maximum Ratings (Notes, 2) Suppy Votage (V CC ) to GND....3V to 6V Anaog Input Votage to GND....3V to (V CC +.3V) Reference Input Votage to GND....3V to (V CC +.3V) Digita Input Votage to GND....3V to (V CC +.3V) Digita Output Votage to GND....3V to (V CC +.3V) Operating Temperature Range LTC248C... C to 7 C LTC248I... 4 C to 85 C LTC248H... 4 C to 25 C Storage Temperature Range C to 25 C Pin Configuration REF + V CC REF IN + IN TOP VIEW CA/f 2 9 CA 3 8 GND 4 7 SDA 5 6 SCL DD PACKAGE -LEAD (3mm 3mm) PLASTIC DFN T JMAX = 25 C, θ JA = 43 C/W EXPOSED PAD (PIN ) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC248CDD#PBF LTC248CDD#TRPBF LBPV -Lead (3mm 3mm) Pastic DFN C to 7 C LTC248IDD#PBF LTC248IDD#TRPBF LBPV -Lead (3mm 3mm) Pastic DFN 4 C to 85 C LTC248HDD#PBF LTC248HDD#TRPBF LBPV -Lead (3mm 3mm) Pastic DFN 4 C to 25 C Consut LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a abe on the shipping container. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: Eectrica Characteristics (Norma Speed) The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at. (Notes 3, 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Resoution (No Missing Codes). V REF V CC, FS V IN +FS (Note 5) 6 Bits Integra Noninearity 5V V CC 5.5V,, V IN(CM) = 2.5V (Note 6) 2.7V V CC 5.5V, V REF = 2.5V, V IN(CM) =.25V (Note 6) 2 ppm of V REF ppm of V REF Offset Error 2.5V V REF V CC, GND IN + = IN V CC (Note 3) µv Offset Error Drift 2.5V V REF V CC, GND IN + = IN V CC nv/ C Positive Fu-Scae Error 2.5V V REF V CC, IN + =.75V REF, IN =.25V REF 2.5V V REF V CC, IN + =.75V REF, IN =.25V REF (H-Grade) 25 4 ppm of V REF ppm Positive Fu-Scae Error Drift 2.5V V REF V CC, IN + =.75V REF, IN =.25V REF. ppm of V REF / C Negative Fu-Scae Error 2.5V V REF V CC, IN =.75V REF, IN + =.25V REF 2.5V V REF V CC, IN =.75V REF, IN + =.25V REF (H-Grade) 25 4 ppm of V REF ppm Negative Fu-Scae Error Drift 2.5V V REF V CC, IN =.75V REF, IN + =.25V REF. ppm of V REF / C Tota Unadjusted Error 5V V CC 5.5V, V REF = 2.5V, V IN(CM) =.25V (Note 6) 5V V CC 5.5V,, V IN(CM) = 2.5V (Note 6) 2.7V V CC 5.5V, V REF = 2.5V, V IN(CM) =.25V (Note 6) ppm of V REF ppm of V REF ppm of V REF Output Noise 5V V CC 5.5V,, GND IN = IN + V CC (Note 2).6 µv RMS Interna PTAT Signa T A = 27 C mv Programmabe Gain See Tabe 2a For more information 248fd

3 LTC248 Eectrica Characteristics (2x Speed) The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at. (Notes 3, 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Resoution (No Missing Codes). V REF V CC, FS V IN +FS (Note 5) 6 Bits Integra Noninearity 5V V CC 5.5V,, V IN(CM) = 2.5V (Note 6) 2.7V V CC 5.5V, V REF = 2.5V, V IN(CM) =.25V (Note 6) 2 ppm of V REF Offset Error 2.5V V REF V CC, GND IN + = IN V CC (Note 3).5 2 mv Offset Error Drift 2.5V V REF V CC, GND IN + = IN V CC nv/ C Positive Fu-Scae Error 2.5V V REF V CC, IN + =.75V REF, IN =.25V REF 25 ppm of V REF Positive Fu-Scae Error Drift 2.5V V REF V CC, IN + =.75V REF, IN =.25V REF. ppm of V REF / C Negative Fu-Scae Error 2.5V V REF V CC, IN =.75V REF, IN + =.25V REF 25 ppm of V REF Negative Fu-Scae Error Drift 2.5V V REF V CC, IN =.75V REF, IN + =.25V REF. ppm of V REF / C Output Noise 5V V CC 5.5V,, GND IN = IN + V CC.84 µv RMS Programmabe Gain See Tabe 2b 28 Converter Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at. (Notes 3, 4) PARAMETER CONDITIONS MIN TYP MAX UNITS Input Common Mode Rejection DC 2.5V V REF V CC, GND IN = IN + V CC (Note 5) 4 db Input Common Mode Rejection 5Hz ±2% Input Common Mode Rejection 6Hz ±2% 2.5V V REF V CC, GND IN = IN + V CC (Note 5) 4 db 2.5V V REF V CC, GND IN = IN + V CC (Note 5) 4 db Input Norma Mode Rejection 5Hz ±2% Input Norma Mode Rejection 6Hz ±2% Input Norma Mode Rejection 5Hz/6Hz ±2% 2.5V V REF V CC, GND IN = IN + V CC (Notes 5, 7) 2.5V V REF V CC, GND IN = IN + V CC (H-Grade) 2.5V V REF V CC, GND IN = IN + V CC (Notes 5, 8) 2.5V V REF V CC, GND IN = IN + V CC (H-Grade) db db 2 db db 2.5V V REF V CC, GND IN = IN + V CC (Notes 5, 9) 87 db Reference Common Mode Rejection DC 2.5V V REF V CC, GND IN = IN + V CC (Note 5) 2 4 db Power Suppy Rejection DC V REF = 2.5V, IN = IN + = GND 2 db Power Suppy Rejection, 5Hz ±2% V REF = 2.5V, IN = IN + = GND (Notes 7, 9) 2 db Power Suppy Rejection, 6Hz ±2% V REF = 2.5V, IN = IN + = GND (Notes 8, 9) 2 db Anaog Input and Reference The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IN + Absoute/Common Mode IN + Votage GND.3V V CC +.3V V IN Absoute/Common Mode IN Votage GND.3V V CC +.3V V FS Fu Scae of the Differentia Input (IN + IN ).5V REF /GAIN V LSB Least Significant Bit of the Output Code FS/2 6 V IN Input Differentia Votage Range (IN + IN ) FS +FS V V REF Reference Votage Range (REF + REF ). V CC V C S (IN + ) IN + Samping Capacitance pf For more information 248fd 3

4 LTC248 Anaog Input and Reference The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS C S (IN ) IN Samping Capacitance pf C S (V REF ) V REF Samping Capacitance pf I DC_LEAK (IN + ) IN + DC Leakage Current Seep Mode, IN + = GND na I DC_LEAK (IN ) IN DC Leakage Current Seep Mode, IN = GND na I DC_LEAK (V REF ) REF +, REF DC Leakage Current Seep Mode, V REF = V CC na I 2 C Digita Inputs and Digita Outputs The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at. (Notes 3, 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IH High Leve Input Votage.7V CC V V IL Low Leve Input Votage.3V CC V V IL(CA) Low Leve Input Votage for Address Pin.5V CC V V IH(CA/f,CA) High Leve Input Votage for Address Pins.95V CC V R INH Resistance from CA/f, CA to V CC to Set Chip Address Bit to kω R INL Resistance from CA to GND to Set Chip kω Address Bit to R INF Resistance from CA/f, CA to V CC or 2 MΩ GND to Set Chip Address Bit to Foat I I Digita Input Current µa V HYS Hysteresis of Schmitt Trig ger Inputs (Note 5).5V CC V V OL Low Leve Output Votage SDA I = 3mA.4 V t OF Output Fa Time from V IHMIN to V ILMAX Bus Load C B pf to 4pF (Note 4) 2+.C B 25 ns t SP Input Spike Suppression 5 ns I IN Input Leakage.V CC V IN V CC µa C I Capacitance for Each I/O Pin pf C B Capacitance Load for Each Bus Line 4 pf C CAX Externa Capacitive Load On-Chip Address pf Pins (CA/f,CA) for Vaid Foat V IH(EXT,OSC) High Leve CA/f Externa Osciator 2.7V V CC < 5.5V V CC.5V V V IL(EXT,OSC) Low Leve CA/f Externa Osciator 2.7V V CC < 5.5V.5 V Power Requirements The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V CC Suppy Votage V I CC Suppy Current Conversion Mode (Note ) Seep Mode (Note ) H-Grade µa µa µa 4 For more information 248fd

5 LTC248 Timing Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f EOSC Externa Osciator Frequency Range khz t HEO Externa Osciator High Period.25 µs t LEO Externa Osciator Low Period.25 µs t CONV_ Conversion Time for x Speed Mode 5Hz Mode 5Hz Mode (H-Grade) 6Hz Mode 6Hz Mode (H-Grade) Simutaneous 5Hz/6Hz Mode Simutaneous 5Hz/6Hz Mode (H-Grade) Externa Osciator (Note ) /f EOSC ms ms ms ms ms ms ms t CONV_2 Conversion Time for 2x Speed Mode 5Hz Mode 5Hz Mode (H-Grade) 6Hz Mode 6Hz Mode (H-Grade) Simutaneous 5Hz/6Hz Mode Simutaneous 5Hz/6Hz Mode (H-Grade) Externa Osciator (Note ) /f EOSC ms ms ms ms ms ms ms I 2 C Timing Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at. (Notes 3, 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS f SCL SCL Cock Frequency 4 khz t HD(SDA) Hod Time (Repeated) START Condition.6 µs t LOW LOW Period of the SCL Cock Pin.3 µs t HIGH HIGH Period of the SCL Cock Pin.6 µs t SU(STA) Set-Up Time for a Repeated START Condition.6 µs t HD(DAT) Data Hod Time.9 µs t SU(DAT) Data Set-Up Time ns t r Rise Time for Both SDA and SCL Signas (Note 4) 2+.C B 3 ns t f Fa Time for Both SDA and SCL Signas (Note 4) 2+.C B 3 ns t SU(STO) Set-Up Time for STOP Condition.6 µs Note : Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: A votage vaues are with respect to GND. Note 3: V CC = 2.7V to 5.5V uness otherwise specified. V REF = REF + REF, V REFCM = (REF + + REF )/2, FS =.5V REF /GAIN; V IN = IN + IN, V INCM = (IN + + IN )/2. Note 4: Use interna conversion cock or externa conversion cock source with f EOSC = 37.2kHz uness otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integra noninearity is defined as the deviation of a code from a straight ine passing through the actua endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: 5Hz mode (interna osciator) or f EOSC = 256kHz ±2% (externa osciator). Note 8: 6Hz mode (interna osciator) or f EOSC = 37.2kHz ±2% (externa osciator). Note 9: Simutaneous 5Hz/6Hz mode (interna osciator) or f EOSC = 28kHz ±2% (externa osciator). Note : The externa osciator is connected to the CA/f pin. The externa osciator frequency, f EOSC, is expressed in khz. Note : The converter uses the interna osciator. Note 2: The output noise incudes the contribution of the interna caibration operations. Note 3: Guaranteed by design and test correation. Note 4: C B = capacitance of one bus ine in pf. Note 5: A vaues refer to V IH(MIN) and V IL(MAX) eves. For more information 248fd 5

6 LTC248 Typica Performance Characteristics 3 2 Integra Noninearity (, ) V IN(CM) = 2.5V 3 2 Integra Noninearity (, V REF = 2.5V) V REF = 2.5V V IN(CM) =.25V 3 2 Integra Noninearity (V CC = 2.7V, V REF = 2.5V) V CC = 2.7V V REF = 2.5V V IN(CM) =.25V INL (ppm OF V REF ) 45 C 85 C 25 C INL (ppm OF V REF ) 45 C, 25 C, 9 C INL (ppm OF V REF ) 45 C, 25 C, 9 C INPUT VOLTAGE (V) 248 G INPUT VOLTAGE (V) 248 G INPUT VOLTAGE (V) G3 TUE (ppm OF V REF ) Tota Unadjusted Error (, ) V IN(CM) = 2.5V 25 C 85 C 45 C TUE (ppm OF V REF ) Tota Unadjusted Error (, V REF = 2.5V) V REF = 2.5V V IN(CM) =.25V 25 C 85 C 45 C TUE (ppm OF V REF ) Tota Unadjusted Error (V CC = 2.7V, V REF = 2.5V) V CC = 2.7V V REF = 2.5V V IN(CM) =.25V 25 C 85 C 45 C INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) G4 248 G5 248 G6 NUMBER OF READINGS (%) Noise Histogram (6.8sps) Noise Histogram (7.5sps) Long-Term ADC Readings 4, CONSECUTIVE READINGS 2 RMS =.6µV AVERAGE =.69µV V IN = V GAIN = OUTPUT READING (µv) NUMBER OF READINGS (%) 4, CONSECUTIVE READINGS 2 V CC = 2.7V V REF = 2.5V V IN = V GAIN = RMS =.59µV AVERAGE =.9µV OUTPUT READING (µv) ADC READING (µv) ,, V IN = V, V IN(CM) = 2.5V GAIN = 256,, RMS NOISE =.6µV TIME (HOURS) G7 248 G8 248 G9 6 For more information 248fd

7 Typica Performance Characteristics LTC248 RMS NOISE (ppm OF V REF ) RMS Noise vs Input Differentia Votage RMS Noise vs V IN(CM) RMS Noise vs Temperature (T A ) V IN(CM) = 2.5V RMS NOISE (µv) V IN = V V IN(CM) = GND GAIN = 256 RMS NOISE (µv) V IN = V V IN(CM) = GND GAIN = INPUT DIFFERENTIAL VOLTAGE (V) V IN(CM) (V) TEMPERATURE ( C) G 248 G 248 G2 RMS NOISE (µv) RMS Noise vs V CC RMS Noise vs V REF Offset Error vs V IN(CM) V REF = 2.5V V IN = V V IN(CM) = GND GAIN = 256 RMS NOISE (µv) V IN = V V IN(CM) = GND GAIN = 256 OFFSET ERROR (ppm OF V REF ) V IN = V V CC (V) V REF (V) V IN(CM) (V) 248 G3 248 G4 248 G5 OFFSET ERROR (ppm OF V REF ) Offset Error vs Temperature Offset Error vs V CC Offset Error vs V REF V IN = V V IN(CM) = GND OFFSET ERROR (ppm OF V REF ) REF + = 2.5V REF = GND V IN = V V IN(CM) = GND OFFSET ERROR (ppm OF V REF ) REF = GND V IN = V V IN(CM) = GND TEMPERATURE ( C) V CC (V) V REF (V) G6 248 G7 248 G8 For more information 248fd 7

8 LTC248 Typica Performance Characteristics FREQUENCY (khz) On-Chip Osciator Frequency vs Temperature V CC = 4.V V REF = 2.5V V IN = V V IN(CM) = GND TEMPERATURE ( C) 248 G2 FREQUENCY (khz) On-Chip Osciator Frequency vs V CC V CC (V) V REF = 2.5V V IN = V V IN(CM) = GND G22 REJECTION (db) PSRR vs Frequency at V CC V CC = 4.V DC V REF = 2.5V IN + = GND IN = GND k k k M FREQUENCY AT V CC (Hz) 248 G23 REJECTION (db) PSRR vs Frequency at V CC PSRR vs Frequency at V CC vs Temperature Conversion Current V CC = 4.V DC ±.4V V REF = 2.5V IN + = GND IN = GND REJECTION (db) V CC = 4.V DC ±.7V V REF = 2.5V IN + = GND IN = GND CONVERSION CURRENT (µa) V CC = 2.7V FREQUENCY AT V CC (Hz) FREQUENCY AT V CC (Hz) TEMPERATURE ( C) 248 G G G26 SLEEP MODE CURRENT (µa) Seep Mode Current vs Temperature 45 V CC = 2.7V TEMPERATURE ( C) 248 G27 SUPPLY CURRENT (µa) Conversion Current vs Output Data Rate V REF = V CC IN + = GND IN = GND CA/f = EXT OSC V CC = 3V 2 3 OUTPUT DATA RATE (READINGS/SEC) 248 G28 8 For more information 248fd

9 Typica Performance Characteristics LTC Integra Noninearity (2x Speed Mode;, ) V IN(CM) = 2.5V 3 2 Integra Noninearity (2x Speed Mode;, V REF = 2.5V) V REF = 2.5V V IN(CM) =.25V 3 2 Integra Noninearity (2x Speed Mode; V CC = 2.7V, V REF = 2.5V) V CC = 2.7V V REF = 2.5V V IN(CM) =.25V INL (ppm OF V REF ) 25 C, 9 C INL (ppm OF V REF ) 9 C 45 C, 25 C INL (ppm OF V REF ) 9 C 45 C, 25 C 2 45 C INPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT VOLTAGE (V) G G3 248 G3 NUMBER OF READINGS (%) Noise Histogram (2x Speed Mode) 79, CONSECUTIVE READINGS V IN = V GAIN = OUTPUT READING (µv) RMS =.86µV AVERAGE =.84mV RMS NOISE (µv) RMS Noise vs V REF (2x Speed Mode) V IN = V V IN(CM) = GND V REF (V) OFFSET ERROR (µv) Offset Error vs V IN(CM) (2x Speed Mode) V IN = V V IN(CM) (V) 248 G G G34 OFFSET ERROR (µv) Offset Error vs Temperature (2x Speed Mode) V IN = V V IN(CM) = GND OFFSET ERROR (µv) Offset Error vs V CC (2x Speed Mode) V REF = 2.5V V IN = V V IN(CM) = GND TEMPERATURE ( C) V CC (V) 248 G G36 For more information 248fd 9

10 LTC248 Typica Performance Characteristics OFFSET ERROR (µv) Offset Error vs V REF (2x Speed Mode) V IN = V V IN(CM) = GND REJECTION (db) PSRR vs Frequency at V CC (2x Speed Mode) V CC = 4.V DC REF + = 2.5V REF = GND IN + = GND IN = GND V REF (V) 4 k k k M FREQUENCY AT V CC (Hz) 248 G G38 RREJECTION (db) PSRR vs Frequency at V CC (2x Speed Mode) V CC = 4.V DC ±.4V REF + = 2.5V REF = GND IN + = GND IN = GND REJECTION (db) PSRR vs Frequency at V CC (2x Speed Mode) V CC = 4.V DC ±.7V REF + = 2.5V REF = GND IN + = GND IN = GND FREQUENCY AT V CC (Hz) FREQUENCY AT V CC (Hz) 248 G G4 Pin Functions REF + (Pin ), REF (Pin 3): Differentia Reference Input. The votage on these pins can have any vaue between GND and V CC as ong as the reference positive input, REF +, is more positive than the reference negative input, REF, by at east.v. V CC (Pin 2): Positive Suppy Votage. Bypass to GND (Pin 8) with a µf tantaum capacitor in parae with.µf ceramic capacitor as cose to the part as possibe. IN + (Pin 4), IN (Pin 5): Differentia Anaog Input. The votage on these pins can have any vaue between GND.3V and V CC +.3V. Within these imits the converter bipoar input range (V IN = IN + IN ) extends from.5 V REF /GAIN to.5 V REF /GAIN. Outside this input range the converter produces unique overrange and underrange output codes. For more information 248fd

11 LTC248 Pin Functions SCL (Pin 6): Seria Cock Pin of the I 2 C Interface. The LTC248 can ony act as a save and the SCL pin ony accepts externa seria cock. Data is shifted into the SDA pin on the rising edges of the SCL cock and output through the SDA pin on the faing edges of the SCL cock. SDA (Pin 7): Bidirectiona Seria Data Line of the I 2 C Interface. In the transmitter mode (Read), the conversion resut is output through the SDA pin, whie in the receiver mode (Write), the device configuration bits are input through the SDA pin. At data input mode, the pin is high impedance; whie at data output mode, it is an open-drain N-channe driver and therefore an externa pu-up resistor or current source to V CC is needed. GND (Pin 8): Ground. Connect this pin to a ground pane through a ow impedance connection. CA (Pin 9): Chip Address Contro Pin. The CA pin is configured as a three state (LOW, HIGH, or Foating) address contro bit for the device I 2 C address. CA/f (Pin ): Chip Address Contro Pin/Externa Cock Input Pin. When no transition is detected on the CA/f pin, it is a two state (HIGH or Foating) address contro bit for the device I 2 C address. When the pin is driven by an externa cock signa with a frequency f EOSC of at east khz, the converter uses this signa as its system cock and the fundamenta digita fiter rejection nu is ocated at a frequency f EOSC /52 and sets the Chip Address CA internay to a HIGH. Functiona Bock Diagram 2 REF+ V CC 4 5 IN + IN MUX REF + IN + 3RD ORDER Σ ADC IN REF (-256) GAIN I 2 C SERIAL INTERFACE SCL SDA CA CA/f TEMP SENSOR AUTOCALIBRATION AND CONTROL REF GND 3 8 INTERNAL OSCILLATOR 248 FD For more information 248fd

12 LTC248 Appications Information Converter Operation Converter Operation Cyce The LTC248 is a ow power, Σ anaog-to-digita converter with an I 2 C interface. After power on reset, its operation is made up of three states. The converter operating cyce begins with the conversion, foowed by the ow power seep state and ends with the data output/input (see Figure ). POWER ON RESET DEFAULT CONFIGURATION: EXTERNAL INPUT GAIN = 5/6Hz REJECTION X SPEED, AUTOCAL CONVERSION SLEEP NO ACKNOWLEDGE Initiay, the LTC248 performs a conversion. Once the conversion is compete, the device enters the seep state. Whie in this seep state, power consumption is reduced by two orders of magnitude. The part remains in the seep state as ong as it is not addressed for a read/write operation. The conversion resut is hed indefinitey in a static shift register whie the converter is in the seep state. YES DATA OUTPUT/INPUT NO STOP OR READ 24-BITS YES 248 F Figure. LTC248 State Transition Diagram The device wi not acknowedge an externa request during the conversion state. After a conversion is finished, the device is ready to accept a read/write request. Once the LTC248 is addressed for a read operation, the device begins outputting the conversion resut under contro of the seria cock (SCL). There is no atency in the conversion resut. The data output is 24 bits ong and contains a 6-bit pus sign conversion resut pus a readback of the configuration bits corresponds to the conversion just performed. This resut is shifted out on the SDA pin under the contro of the SCL. Data is updated on the faing edges of SCL aowing the user to reiaby atch data on the rising edge of SCL. In write operation, the device accepts one configuration byte and the data is shifted in on the rising edges of the SCL. A new conversion is initiated by a STOP condition foowing a vaid write operation or at the concusion of a data read operation (read out a 24 bits). I 2 C INTERFACE The LTC248 communicates through an I 2 C interface. The I 2 C interface is a 2-wire open-drain interface supporting mutipe devices and masters on a singe bus. The connected devices can ony pu the bus wires LOW and can never drive the bus HIGH. The bus wires are externay connected to a positive suppy votage via a currentsource or pu-up resistor. When the bus is free, both ines are HIGH. Data on the I 2 C-bus can be transferred at rates of up to kbit/s in the Standard-mode and up to 4kbit/s in the Fast-mode. The V CC power shoud not be removed from the device when the I 2 C bus is active to avoid oading the I 2 C bus ines through the interna ESD protection diodes. Each device on the I 2 C bus is recognized by a unique address stored in that device and can operate as either a transmitter or receiver, depending on the function of the device. In addition to transmitters and receivers, devices can aso be considered as masters or saves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the cock signas to permit that transfer. At the same time any device addressed is considered a save. 2 For more information 248fd

13 Appications Information The LTC248 can ony be addressed as a save. Once addressed, it can receive configuration bits or transmit the ast conversion resut. Therefore the seria cock ine SCL is an input ony and the data ine SDA is bidirectiona. The device supports the Standard-mode and the Fast-mode for data transfer speeds up to 4kbit/s. Figure 2 shows the definition of timing for Fast/Standard-mode devices on the I 2 C-bus. The START and STOP Conditions A START condition is generated by transitioning SDA from HIGH to LOW whie SCL is HIGH. The bus is considered to be busy after the START condition. When the data transfer is finished, a STOP condition is generated by transitioning SDA from LOW to HIGH whie SCL is HIGH. The bus is free again a certain time after the STOP condition. START and STOP conditions are aways generated by the master. When the bus is in use, it stays busy if a repeated START (Sr) is generated instead of a STOP condition. The repeated START (Sr) conditions are functionay identica to the START (S). Data Transferring After the START condition, the I 2 C bus is busy and data transfer is set between a master and a save. Data is transferred over I 2 C in groups of nine bits (one byte) foowed by an acknowedge bit, therefore each group takes nine SCL cyces. The transmitter reeases the SDA ine during the acknowedge cock puse and the receiver issues an LTC248 Acknowedge (ACK) by puing SDA LOW or eaves SDA HIGH to indicate a Not Acknowedge (NACK) condition. Change of data state can ony happen whie SCL is LOW. Accessing the Specia Features of the LTC248 The LTC248 combines a high resoution, ow noise Σ anaog-to-digita converter with an on-chip seectabe temperature sensor, programmabe gain, programmabe digita fiter and output rate contro. These specia features are seected through a singe 8-bit seria input word during the data input/output cyce (see Figure 3). The LTC248 powers up in a defaut mode commony used for most measurements. The device wi remain in this mode unti a vaid write cyce is performed. In this defaut mode, the measured input is externa, the GAIN is, the digita fiter simutaneousy rejects 5Hz and 6Hz ine frequency noise, and the speed mode is x (offset automaticay, continuousy caibrated). The I 2 C seria interface grants access to any or a specia functions contained within the LTC248. In order to change the mode of operation, a vaid write address foowed by 8 bits of data are shifted into the device (see Tabe ). The first 3 bits (GS2, GS, GS) contro the GAIN of the converter from to 256. The 4th bit is reserved and shoud be ow. The 5th bit (IM) is used to seect the interna temperature sensor as the conversion input, whie the 6th and 7th bits (FA, FB) combine to determine the ine frequency rejection mode. The 8th bit (SPD) is used to doube the output rate by disabing the offset auto caibration. SDA t f t LOW t SU;DAT t r t r t HD;STA t SP t r t BUF SCL t HD;STA t SU;STA t SU;STO S t HD;DAT t HIGH Sr P S 248 F2 Figure 2. Definition of Timing for F/S-Mode Devices on the I 2 C-Bus For more information 248fd 3

14 LTC248 Appications Information SCL SDA START BY MASTER 7-BIT ADDRESS SLEEP W ACK BY LTC248 GS2 GS GS IM FA FB SPD DATA INPUT ACK BY LTC F3 Figure 3. Timing Diagram for Writing to the LTC248 Tabe. Seecting Specia Modes Gain GS2 GS GS X X X X Any Gain X X X X X X X X IM FA FB SPD Rejection Mode Any Rejection Mode Any Speed X X X X 248 TBL Comments Externa Input, Gain =, Autocaibration Externa Input, Gain = 4, Autocaibration Externa Input, Gain = 8, Autocaibration Externa Input, Gain = 6, Autocaibration Externa Input, Gain = 32, Autocaibration Externa Input, Gain = 64, Autocaibration Externa Input, Gain = 28, Autocaibration Externa Input, Gain = 256, Autocaibration Externa Input, Gain =, 2x Speed Externa Input, Gain = 2, 2x Speed Externa Input, Gain = 4, 2x Speed Externa Input, Gain = 8, 2x Speed Externa Input, Gain = 6, 2x Speed Externa Input, Gain = 32, 2x Speed Externa Input, Gain = 64, 2x Speed Externa Input, Gain = 28, 2x Speed Externa Input, Simutaneous 5Hz/6Hz Rejection Externa Input, 5Hz Rejection Externa Input, 6Hz Rejection Reserved, Do Not Use Temperature Input, 5Hz/6Hz Rejection, Gain =, Autocaibration Temperature Input, 5Hz Rejection, Gain =, Autocaibration Temperature Input, 6Hz Rejection, Gain =, Autocaibration Reserved, Do Not Use 4 For more information 248fd

15 LTC248 Appications Information Tabe 2a. The LTC248 Performance vs GAIN in Norma Speed Mode (, ) GAIN UNIT Input Span ±2.5 ±.625 ±.32 ±.56 ±78m ±39m ±9.5m ±9.76m V LSB µv Noise Free Resoution* Counts Gain Error ppm of FS Offset Error µv Tabe 2b. The LTC248 Performance vs GAIN in 2x Speed Mode (, ) GAIN UNIT Input Span ±2.5 ±.25 ±.625 ±.32 ±.56 ±78m ±39m ±9.5m V LSB µv Noise Free Resoution* Counts Gain Error ppm of FS Offset Error µv *The resoution in counts is cacuated as the FS divided by LSB or the RMS noise vaue, whichever is arger. GAIN (GS2, GS, GS) The input referred gain of the LTC248 is adjustabe from to 256. With a gain of, the differentia input range is ±V REF /2 and the common mode input range is rai-to-rai. As the GAIN is increased, the differentia input range is reduced to ±V REF /2 GAIN but the common mode input range remains rai-to-rai. As the differentia gain is increased, ow eve votages are digitized with greater resoution. At a gain of 256, the LTC248 digitizes an input signa range of ±9.76mV with over 6, counts. Temperature Sensor (IM) The LTC248 incudes an on-chip temperature sensor. The temperature sensor is seected by setting IM = in the seria input data stream. Conversions are performed directy on the temperature sensor by the converter. Whie operating in this mode, the device behaves as a temperature to bits converter. The digita reading is proportiona to the absoute temperature of the device. This feature aows the converter to inearize temperature sensors or continuousy remove temperature effects from externa sensors. Severa appications everaging this feature are presented in more detai in the appications section. Whie operating in this mode, the gain is set to and the speed is set to norma independent of the contro bits (GS2, GS, GS and SPD). Rejection Mode (FA, FB) The LTC248 incudes a high accuracy on-chip osciator with no required externa components. Couped with a 4th order digita owpass fiter, the LTC248 rejects ine frequency noise. In the defaut mode, the LTC248 simutaneousy rejects 5Hz and 6Hz by at east 87dB. The LTC248 can aso be configured to seectivey reject 5Hz or 6Hz to better than db. Speed Mode (SPD) The LTC248 continuousy performs offset caibrations. Every conversion cyce, two conversions are automaticay performed (defaut) and the resuts combined. This resut is free from offset and drift. In appications where the offset is not critica, the autocaibration feature can be disabed with the benefit of twice the output rate. Linearity, fu-scae accuracy and fu-scae drift are identica for both 2x and x speed modes. In both the x and 2x speed there is no atency. This enabes input steps or mutipexer channe changes to sette in a singe conversion cyce easing system overhead and increasing the effective conversion rate. For more information 248fd 5

16 LTC248 Appications Information LTC248 Data Format After a START condition, the master sends a 7-bit address foowed by a R/W bit. The bit R/W is for a Read request and for a Write request. If the 7-bit address agrees with an LTC248 s address, that device is seected. When the device is in the conversion state, it does not accept the request and issues a Not-Acknowedge (NACK) by eaving SDA HIGH. If the conversion is compete, it issues an acknowedge (ACK) by puing SDA LOW. The LTC248 has two registers. The output register contains the resut of the ast conversion and a user programmabe configuration register that sets the converter operation mode. The output register contains the ast conversion resut. After each conversion is competed, the device automaticay enters the seep state where the suppy current is reduced to µa. When the LTC248 is addressed for a Read operation, it acknowedges (by puing SDA LOW) and acts as a transmitter. The master and receiver can read up to three bytes from the LTC248. After a compete Read operation (3 bytes), the output register is emptied, a new conversion is initiated, and a foowing Read request in the same input/output phase wi be NACKed. The LTC248 output data stream is 24 bits ong, shifted out on the faing edges of SCL. The first bit is the conversion resut sign bit (SIG), see Tabes 3 and 4. This bit is HIGH if V IN. It is LOW if V IN <. The second bit is the most significant bit (MSB) of the resut. The first two bits (SIG and MSB) can be used to indicate over range conditions. If both bits are HIGH, the differentia input votage is above +FS and the foowing 6 bits are set to LOW to indicate an overrange condition. If both bits are LOW, the input votage is beow FS and the foowing 6 bits are set to HIGH to indicate an underrange condition. The function of these two bits is summarized in Tabe 3. The next 6 bits contain the conversion resuts in binary two s compement format. The remaining six bits are a readback of the configuration register. Tabe 3. LTC248 Status Bits INPUT RANGE BIT 23 SIG BIT 22 MSB V IN.5 V REF V V IN <.5 V REF /.5 V REF V IN < V V IN <.5 V REF As ong as the votage on the IN + and IN pins is maintained within the.3v to (V CC +.3V) absoute maximum operating range, a conversion resut is generated for any differentia input votage V IN from FS =.5 V REF /GAIN to +FS =.5 V REF /GAIN. For differentia input votages greater than +FS, the conversion resut is camped to the vaue corresponding to the +FS + LSB. For differentia input votages beow FS, the conversion resut is camped to the vaue corresponding to FS LSB. Tabe 4. LTC248 Output Data Format DIFFERENTIAL INPUT VOLTAGE VIN * BIT 23 SIG BIT 22 MSB BIT 2 BIT 2 BIT 9 BIT 6 V IN * FS** FS** LSB.5 FS**.5 FS** LSB /*** LSB.5 FS**.5 FS** LSB FS** V IN * < FS** * The differentia input votage V IN = IN + IN. ** The fu-scae votage FS =.5 V REF /GAIN. *** The sign bit changes state during the output code when the device is operating in the 2x speed mode. 6 For more information 248fd

17 LTC248 Appications Information BIT ADDRESS R SGN MSB D5 LSB PG2 PG PG X IM SPD START BY MASTER ACK BY LTC248 ACK BY MASTER NAK BY MASTER SLEEP DATA OUTPUT Figure 4. Timing Diagram for Reading from the LTC F4 Initiating a New Conversion When the LTC248 finishes a conversion, it automaticay enters the seep state. Once in the seep state, the device is ready for Read/Write operations. After the device acknowedges a Read or Write request, the device exits the seep state and enters the data input/output state. The data input/output state concudes and the LTC248 starts a new conversion once a STOP condition is issued by the master or a 24 bits of data are read out of the device. During the data read cyce, a stop command may be issued by the master controer in order to start a new conversion and abort the data transfer. This stop command must be issued during the 9th cock cyce of a byte read when the bus is free (the ACK/NACK cyce). LTC248 Address The LTC248 has two address pins, enabing one in 6 possibe addresses, as shown in Tabe 5. Tabe 5. LTC248 Address Assignment CA CA/f * Address LOW HIGH LOW Foating Foating HIGH Foating Foating HIGH HIGH HIGH Foating * CA/f is treated as HIGH when driven by a vaid externa cock. In addition to the configurabe addresses isted in Tabe 5, the LTC248 aso contains a goba address () which may be used for synchronizing mutipe LTC248s. For more information Operation Sequence The LTC248 acts as a transmitter or receiver. The device may be programmed to perform severa functions. These incude measuring an externa differentia input signa or an integrated temperature sensor, setting a programmabe gain (from to 256), seecting ine frequency rejection (5Hz, 6Hz, or simutaneous 5Hz and 6Hz), and a 2x speed up mode. Continuous Read In appications where the configuration does not need to change for each conversion cyce, the conversion resut can be continuousy read. The configuration remains unchanged from the ast vaue written into the device. If the device has not been written to since power up, the configuration is set to the defaut vaue (Input Externa, GAIN=, simutaneous 5Hz/6Hz rejection, and x speed mode). The operation sequence is shown in Figure 6. When the conversion is finished, the device may be addressed for a read operation. At the end of a read operation, a new conversion begins. At the concusion of the conversion cyce, the next resut may be read using the method described above. If the conversion cyce is not concuded and a vaid address seects the device, the LTC248 generates a NACK signa indicating the conversion cyce is in progress. 248fd 7

18 LTC248 Appications Information S 7-BIT ADDRESS R/W ACK DATA Sr DATA TRANSFERRING P CONVERSION SLEEP DATA INPUT/OUTPUT CONVERSION 248 F5 Figure 5. The LTC248 Conversion Sequence S 7-BIT ADDRESS R ACK READ P S 7-BIT ADDRESS R ACK READ P CONVERSION SLEEP DATA OUTPUT CONVERSION SLEEP DATA OUTPUT CONVERSION 248 F6 Figure 6. Consecutive Reading at the Same Configuration S 7-BIT ADDRESS W ACK WRITE Sr 7-BIT ADDRESS R ACK READ P CONVERSION SLEEP DATA INPUT ADDRESS DATA OUTPUT CONVERSION 248 F8 Figure 7. Write, Read, Start Conversion Continuous Read/Write Once the conversion cyce is concuded, the LTC248 can be written to then read from, using the repeated Start (Sr) command. Figure 7 shows a cyce which begins with a data Write, a repeated start, foowed by a read, and concuded with a stop command. The foowing conversion begins after a 24 bits are read out of the device or after the STOP command and uses the newy programmed configuration data. Discarding a Conversion Resut and Initiating a New Conversion with Optiona Configuration Updating At the concusion of a conversion cyce, a Write cyce can be initiated. Once the Write cyce is acknowedged, a stop (P) command initiates a new conversion. If a new configuration is required, this data can be written into the device and a stop command initiates a new conversion, see Figure 8. Synchronizing Mutipe LTC248s with the Goba Address Ca In appications where severa LTC248s are used on the same I 2 C bus, a LTC248s can be synchronized with the goba address ca. To achieve this, first a the LTC248s must have competed the conversion cyce. The master issues a Start, foowed by the LTC248 goba address and a Write request. A LTC248s wi be seected and acknowedge the request. The master then sends the write byte (Optiona) and ends the Write operation with a STOP. This wi update the configuration registers (if a write byte was sent) and initiate a new conversion simutaneousy on a the LTC248s, as shown in Figure 9. In order to synchronize the start of conversion without affecting the configuration registers, the Write operation can be aborted with a STOP. This initiates a new conversion on a the LTC248s without changing the configuration registers. 8 For more information 248fd

19 Appications Information LTC248 S 7-BIT ADDRESS W ACK WRITE (OPTIONAL) P CONVERSION SLEEP DATA INPUT CONVERSION Figure 8. Start a New Conversion without Reading Od Conversion Resut 248 F8 SCL SDA LTC248 LTC248 LTC248 S GLOBAL ADDRESS W ACK WRITE (OPTIONAL) P ALL LTC248s IN SLEEP Easy Drive Input Current Canceation The LTC248 combines a high precision deta-sigma ADC with an automatic differentia input current canceation front end. A proprietary front-end passive samping network transparenty removes the differentia input current. This enabes externa RC networks and high impedance sensors to directy interface to the LTC248 without externa ampifiers. The remaining common mode input current is eiminated by either baancing the differentia input impedances or setting the common mode input equa to the common mode reference (see Automatic Input Current Canceation section). This unique architecture does not require on-chip buffers enabing input signas to swing a the way to ground and up to V CC. Furthermore, the canceation does not interfere with the transparent offset and fu-scae auto-caibration and the absoute accuracy (fu-scae + offset + inearity) is maintained even with externa RC networks. Conversion Cock A major advantage the deta-sigma converter offers over conventiona type converters is an on-chip digita fiter (commony impemented as a SINC or Comb fiter). For high resoution, ow frequency appications, this fiter is typicay designed to reject ine frequencies of 5Hz or 6Hz pus their harmonics. The fiter rejection performance is DATA INPUT Figure 9. Synchronize the LTC248s with the Goba Address Ca For more information CONVERSION OF ALL LTC248s 248 F9 directy reated to the accuracy of the converter system cock. The LTC248 incorporates a highy accurate on-chip osciator. This eiminates the need for externa frequency setting components such as crystas or osciators. Frequency Rejection Seection (CA/f ) The LTC248 interna osciator provides better than db norma mode rejection at the ine frequency and a its harmonics (up to the 255th) for 5Hz ±2% or 6Hz ±2%, or better than 87dB norma mode rejection from 48Hz to 62.4Hz. The rejection mode is seected by writing to the on-chip configuration register (the defaut mode at powerup is simutaneous 5Hz/6Hz rejection). When a fundamenta rejection frequency different from 5Hz or 6Hz is required or when the converter must be synchronized with an outside source, the LTC248 can operate with an externa conversion cock. The converter automaticay detects the presence of an externa cock signa at the CA/f pin and turns off the interna osciator. The chip address for CA is internay set HIGH. The frequency f EOSC of the externa signa must be at east khz to be detected. The externa cock signa duty cyce is not significant as ong as the minimum and maximum specifications for the high and ow periods t HEO and t LEO are observed. 248fd 9

20 LTC248 Appications Information Whie operating with an externa conversion cock of a frequency f EOSC, the LTC248 provides better than db norma mode rejection in a frequency range of f EOSC /52 ±4% and its harmonics. The norma mode rejection as a function of the input frequency deviation from f EOSC /52 is shown in Figure. Whenever an externa cock is not present at the CA/f pin, the converter automaticay activates its interna osciator and enters the Interna Conversion Cock mode. CA/f may be tied HIGH or eft foating in order to set the chip address. The LTC248 operation wi not be disturbed if the change of conversion cock source occurs during the seep state or during the data output state whie the converter uses an externa seria cock. If the change occurs during the conversion state, the resut of the conversion in progress may be outside specifications but the foowing conversions wi not be affected. Tabe 6 summarizes the duration of the conversion state of each state and the achievabe output data rate as a function of f EOSC. Ease of Use The LTC248 data output has no atency, fiter setting deay or redundant data associated with the conversion cyce. There is a one-to-one correspondence between the conversion and the output data. Therefore, mutipexing mutipe anaog votages is easy. The LTC248 performs offset and fu-scae caibrations every conversion cyce. This caibration is transparent to the user and has no effect on the cycic operation described NORMAL MODE REJECTION (db) DIFFERENTIAL INPUT SIGNAL FREQUENCY DEVIATION FROM NOTCH FREQUENCY f EOSC /52(%) 248 F Figure. LTC248 Norma Mode Rejection When Using an Externa Osciator above. The advantage of continuous caibration is extreme stabiity of offset and fu-scae readings with respect to time, suppy votage change and temperature drift. Power-Up Sequence The LTC248 automaticay enters an interna reset state when the power suppy votage V CC drops beow approximatey 2V. This feature guarantees the integrity of the conversion resut. When the V CC votage rises above this critica threshod, the converter creates an interna power-on-reset (POR) signa with a duration of approximatey 4ms. The POR signa cears a interna registers. Foowing the POR signa, the LTC248 starts a norma conversion cyce and foows the succession of states described in Figure. The first Tabe 6. LTC248 State Duration STATE OPERATING MODE DURATION CONVERSION Interna Osciator 6Hz Rejection 33ms, Output Data Rate 7.5 Readings/s for x Speed Mode 67ms, Output Data Rate 5 Readings/s for 2x Speed Mode 5Hz Rejection 6ms, Output Data Rate 6.2 Readings/s for x Speed Mode 8ms, Output Data Rate 2.5 Readings/s for 2x Speed Mode 5Hz/6Hz Rejection 47ms, Output Data Rate 6.8 Readings/s for x Speed Mode 73.6ms, Output Data Rate 3.6 Readings/s for 2x Speed Mode Externa Osciator CA/f = Externa Osciator with Frequency f EOSC Hz (f EOSC /52 Rejection) 436/f EOSC s, Output Data Rate f EOSC /436 Readings/s for x Speed Mode 2556/f EOSC s, Output Data Rate f EOSC /2556 Readings/s for 2x Speed Mode 2 For more information 248fd

21 Appications Information conversion resut foowing POR is accurate within the specifications of the device if the power suppy votage is restored within the operating range (2.7V to 5.5V) before the end of the POR time interva. On-Chip Temperature Sensor The LTC248 contains an on-chip PTAT (proportiona to absoute temperature) signa that can be used as a temperature sensor. The interna PTAT has a typica vaue of 42mV at 27 C and is proportiona to the absoute temperature vaue with a temperature coefficient of 42/( ) =.4mV/ C (SLOPE), as shown in Figure. The interna PTAT signa is used in a singe-ended mode referenced to device ground internay. The GAIN is automaticay set to one (independent of the vaues of GS, GS, GS2) in order to preserve the PTAT property at the ADC output code and avoid an out of range error. The x speed mode with automatic offset caibration is automaticay seected for the interna PTAT signa measurement as we. When using the interna temperature sensor, if the output code is normaized to R SDA = V PTAT /V REF, the temperature is cacuated using the foowing formua: T K = R SDA V REF SLOPE and in Kevin T C = R SDA V REF 273 in C SLOPE where SLOPE is nominay.4mv/ C. Since the PTAT signa can have an initia vaue variation which resuts in errors in SLOPE, to achieve absoute temperature measurements, a one-time caibration is needed to adjust the SLOPE vaue. The converter output of the PTAT signa, R SDA, is measured at a known temperature T (in C) and the SLOPE is cacuated as: SLOPE = R SDA V REF T+273 This caibrated SLOPE can be used to cacuate the temperature. LTC248 If the same V REF source is used during caibration and temperature measurement, the actua vaue of the V REF is not needed to measure the temperature as shown in the cacuation beow: T C = R SDA V REF SLOPE 273 = R SDA ( T+273) 273 R SDA V PTAT (mv) IM = SLOPE =.4mV/ C TEMPERATURE ( C) Figure. Interna PTAT Signa vs Temperature Reference Votage Range The LTC248 externa reference votage range is.v to V CC. The converter output noise is determined by the therma noise of the front-end circuits, and as such, its vaue in nanovots is neary constant with reference votage. Since the transition noise (6nV) is much ess than the quantization noise (V REF /2 7 ), a decrease in the reference votage wi increase the converter resoution. A reduced reference votage wi aso improve the converter performance when operated with an externa conversion cock (externa f O signa) at substantiay higher output data rates (see the Output Data Rate section). V REF must be.v to use the interna temperature sensor. The reference input is differentia. The differentia reference input range (V REF = REF + REF ) is mv to V CC and the common mode reference input range is V to V CC F For more information 248fd 2

22 LTC248 Appications Information Input Votage Range The anaog input is truy differentia with an absoute/ common mode range for the IN + and IN input pins extending from GND.3V to V CC +.3V. Outside these imits, the ESD protection devices begin to turn on and the errors due to input eakage current increase rapidy. Within these imits, the LTC248 converts the bipoar differentia input signa, V IN = IN + IN, from FS to +FS where FS =.5 V REF /GAIN. Beyond this range, the converter indicates the overrange or the underrange condition using distinct output codes. Since the differentia input current canceation does not rey on an on-chip buffer, current canceation as we as DC performance is maintained rai-to-rai. Input signas appied to IN + and IN pins may extend by 3mV beow ground and above V CC. In order to imit any faut current, resistors of up to 5k may be added in series with the IN + and IN pins without affecting the performance of the devices. The effect of the series resistance on the converter accuracy can be evauated from the curves presented in the Input Current/Reference Current sections. In addition, series resistors wi introduce a temperature dependent offset error due to the input eakage current. A na input eakage current wi deveop a ppm offset error on a 5k resistor if. This error has a very strong temperature dependency. I REF + V REF + I IN + V IN + I IN V IN I REF V REF 22 V CC V CC I LEAK I LEAK V CC I LEAK I LEAK V CC I LEAK I LEAK I LEAK I LEAK RSW (TYP) k RSW (TYP) k R SW (TYP) k R SW (TYP) k SWITCHING FREQUENCY f SW = 23kHz INTERNAL OSCILLATOR f SW =.4 f EOSC EXTERNAL OSCILLATOR 248 F2 C EQ 2pF (TYP) For more information Driving the Input and Reference The input and reference pins of the LTC248 converter are directy connected to a network of samping capacitors. Depending upon the reation between the differentia input votage and the differentia reference votage, these capacitors are switching between these four pins transferring sma amounts of charge in the process. A simpified equivaent circuit is shown in Figure 2. For a simpe approximation, the source impedance R S driving an anaog input pin (IN +, IN, REF + or REF ) can be considered to form, together with R SW and C EQ (see Figure 2), a first order passive network with a time constant τ = (R S + R SW ) C EQ. The converter is abe to sampe the input signa with better than ppm accuracy if the samping period is at east 4 times greater than the input circuit time constant τ. The samping process on the four input anaog pins is quasi-independent so each time constant shoud be considered by itsef and, under worst-case circumstances, the errors may add. When using the interna osciator, the LTC248 s front-end switched-capacitor network is cocked at 23kHz corresponding to an 8.µs samping period. Thus, for setting errors of ess than ppm, the driving source impedance shoud be chosen such that τ 8.µs/4 = 58ns. When an externa osciator of frequency f EOSC is used, the samping period is 2.5/f EOSC and, for a setting error of ess than ppm, τ.78/f EOSC. VIN CM V I IN+ REF CM ( ) = I IN ( ) ( ) ( ) = AVG AVG. 5 REQ V V V V V D V V V REF INCM REFCM IN REF T REF REF CM IN CM VIN I REF ( ( ) 2 ( )) ( ) = AVG. 5 REQ VREF REQ REQ. 5 REQ VREF REQ where: REF VREFCM = + + REF, VREF = REF + REF 2 VIN = IN+ IN IN+ + IN VINCM = 2 REQ = 2. 7MΩ INTERNAL OSCILLATOR 6Hz MODE REQ = 2.98MΩ INTERNAL OSCILLATOR 5Hz AND 6Hz MODE R = EQ / f EOSCEXTERNAL OSCILLATOR ( ) D T IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT WHERE REF IS INTERNALLY TIED TO GND Figure 2. LTC248 Equivaent Anaog Input Circuit 248fd