LTC6995-1/LTC TimerBlox: Long Timer, Low Frequency Oscillator. Applications. Typical Application Active Low Power-On Reset Timer

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1 Features n Period Range: 1ms to 9.5 Hours n Timing Reset by Power-On or Reset Input n Configured with 1 to 3 Resistors n <1.5% Maximum Frequency Error n Programmabe Output Poarity n 2.2 to 5. Singe Suppy Operation n 55µA to 8µA Suppy Current (2ms to 9.5hr Cock Period) n 5µs Start-Up Time n CMOS Output Driver Sources/Sinks 2mA n 55 C to 125 C Operating Temperature Range n Avaiabe in Low Profie (1mm) SOT-23 (ThinSOT ) and 2mm 3mm DFN Packages Appications n Power-On Reset Timer n Long Time One Shot n Heartbeat Timers n Watchdog Timers n Periodic Wake-Up Ca n High Vibration, High Acceeration Environments L, LT, LTC, LTM, Linear Technoogy, TimerBox and the Linear ogo are registered trademarks and ThinSOT is a trademark of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. Description /LTC TimerBox: Long Timer, Low Frequency Osciator The LTC 6995 is a siicon osciator with a programmabe period range of 1.24ms to 9.54 hours (29.1µHz to 977Hz), specificay intended for ong duration timing events. The LTC6995 is part of the TimerBox famiy of versatie siicon timing devices. A singe resistor, R, programs the LTC6995 s interna master osciator frequency. The output cock period is determined by this master osciator and an interna frequency divider, N, programmabe to eight settings from 1 to t = N R 5kΩ 1.24ms, N = 1,8,64,...,221 When osciating, the LTC6995 generates a 5% duty cyce square wave output. A reset function is provided to stop the master osciator and cear interna dividers. Removing reset initiates a fu output cock cyce which is usefu for programmabe power-on reset and watchdog timer appications. The LTC6995 has two versions of reset functionaity. The reset input is active high for the and active ow for the LTC The poarity of the output when reset is seectabe for both versions. PUT (OSCILLATOR START STATE) / POLARITY LTC Osciating (Low) (Reset) 1 (Reset) Osciating (Low) 1 Osciating (High) 1 (Reset) (Reset) Osciating (High) Typica Appication Active Low Power-On Reset Timer 5 SECONDS 1/2 t TIMER STOPPED 118k 392k POWER-ON RE (1ms TO 4.8 HOURS) TA1 1

2 /LTC Absoute Maximum Ratings (Note 1) Suppy Votage ( ) to...6v Maximum Votage on Any Pin... (.3V) V PIN ( +.3V) Operating Temperature Range (Note 2) LTC6995C... 4 C to 85 C LTC6995I... 4 C to 85 C LTC6995H... 4 C to 125 C LTC6995MP C to 125 C Specified Temperature Range (Note 3) LTC6995C... C to 7 C LTC6995I... 4 C to 85 C LTC6995H... 4 C to 125 C LTC6995MP C to 125 C Junction Temperature C Storage Temperature Range C to 15 C Lead Temperature (Sodering, 1 sec) S6 Package...3 C Pin Configuration /LTC TOP VIEW /LTC TOP VIEW / / DCB PACKAGE 6-LEAD (2mm 3mm) PLASTIC DFN T JMAX = 15 C, θ JA = 64 C/W, θ JC = 9.6 C/W EXPOSED PAD (PIN 7) CONNECTED TO, PCB CONNECTION OPTIONAL S6 PACKAGE 6-LEAD PLASTIC TSOT-23 T JMAX = 15 C, θ JA = 192 C/W, θ JC = 51 C/W Order Information Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC6995CDCB-1#TRMPBF LTC6995CDCB-1#TRPBF LGJM 6-Lead (2mm 3mm) Pastic DFN C to 7 C LTC6995IDCB-1#TRMPBF LTC6995IDCB-1#TRPBF LGJM 6-Lead (2mm 3mm) Pastic DFN 4 C to 85 C LTC6995HDCB-1#TRMPBF LTC6995HDCB-1#TRPBF LGJM 6-Lead (2mm 3mm) Pastic DFN 4 C to 125 C LTC6995CDCB-2#TRMPBF LTC6995CDCB-2#TRPBF LGJP 6-Lead (2mm 3mm) Pastic DFN C to 7 C LTC6995IDCB-2#TRMPBF LTC6995IDCB-2#TRPBF LGJP 6-Lead (2mm 3mm) Pastic DFN 4 C to 85 C LTC6995HDCB-2#TRMPBF LTC6995HDCB-2#TRPBF LGJP 6-Lead (2mm 3mm) Pastic DFN 4 C to 125 C LTC6995CS6-1#TRMPBF LTC6995CS6-1#TRPBF LTGJN 6-Lead Pastic TSOT-23 C to 7 C LTC6995IS6-1#TRMPBF LTC6995IS6-1#TRPBF LTGJN 6-Lead Pastic TSOT-23 4 C to 85 C LTC6995HS6-1#TRMPBF LTC6995HS6-1#TRPBF LTGJN 6-Lead Pastic TSOT-23 4 C to 125 C LTC6995MPS6-1#TRMPBF LTC6995MPS6-1#TRPBF LTGJN 6-Lead Pastic TSOT C to 125 C LTC6995CS6-2#TRMPBF LTC6995CS6-2#TRPBF LTGJQ 6-Lead Pastic TSOT-23 C to 7 C LTC6995IS6-2#TRMPBF LTC6995IS6-2#TRPBF LTGJQ 6-Lead Pastic TSOT-23 4 C to 85 C LTC6995HS6-2#TRMPBF LTC6995HS6-2#TRPBF LTGJQ 6-Lead Pastic TSOT-23 4 C to 125 C LTC6995MPS6-2#TRMPBF LTC6995MPS6-2#TRPBF LTGJQ 6-Lead Pastic TSOT C to 125 C TRM = 5 pieces. *Temperature grades are identified by a abe on the shipping container. Consut LTC Marketing for parts specified with wider operating temperature ranges. Consut LTC Marketing for information on ead based finish parts. For more information on ead free part marking, go to: For more information on tape and ree specifications, go to: 2

3 /LTC Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. Test conditions are = 2.2 to 5., = V for, = for LTC6995-2, CODE = to 15 (N = 1 to 2 21 ), R = 5k to 8k, R LOAD = 5k, C LOAD = 5pF uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS t Output Cock Period 1.24m 34,36 Seconds f Output Frequency 29.1µ 977 Hz f Frequency Accuracy (Note 4) 29.1µHz f 977Hz ±.8 ±1.5 % ±2.2 % f / T Frequency Drift Over Temperature ±.5 %/ C f / Frequency Drift Over Suppy = 4. to 5. = 2.2 to 4. Long-Term Frequency Stabiity (Note 11) 9 ppm/ khr Period Jitter (Note 1) N = 1 N = %/V %/V ppm RMS ppm RMS BW Frequency Moduation Bandwidth.4 f Hz t S Frequency Change Setting Time (Note 9) 1 Cyce Anaog Inputs V Votage at Pin V V / T V Drift Over Temperature ±75 µv/ C R Frequency-Setting Resistor 5 8 kω V Pin Votage V V / Pin Vaid Code Range (Note 5) Deviation from Idea ±1.5 % V / = (CODE +.5)/16 Pin Input Current ±1 na Power Suppy Operating Suppy Votage Range V Power-On Reset Votage 1.95 V I S Suppy Current R L =, R = 5k = 5. = 2.2 R L =, R = 1k = 5. = 2.2 R L =, R = 8k = 5. = 2.2 R L =, I = µa = 5. = µa µa µa µa µa µa µa µa 3

4 /LTC Eectrica Characteristics The denotes the specifications which appy over the fu operating temperature range, otherwise specifications are at T A = 25 C. Test conditions are = 2.2 to 5., = V for, = for LTC6995-2, CODE = to 15 (N = 1 to 2 21 ), R = 5k to 8k, R LOAD =, C LOAD = 5pF uness otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digita I/O Pin Input Capacitance 2.5 pf Pin Input Current = V to ±1 na V IH High Leve Pin Input Votage (Note 6).7 V V IL Low Leve Pin Input Votage (Note 6).3 V I (MAX) Output Current = 2.7V to 5. ±2 ma V OH High Leve Output Votage (Note 7) = 5. I = 1mA I = 16mA = 3.3V I = 1mA I = 1mA = 2.2 I = 1mA I = 8mA V OL Low Leve Output Votage (Note 7) = 5. I = 1mA I = 16mA = 3.3V I = 1mA I = 1mA = 2.2 I = 1mA I = 8mA t Reset Propagation Deay = 5. = 3.3V = 2.2 t WIDTH Minimum Input Puse Width = 3.3V 5 ns t r Output Rise Time (Note 8) = 5. = 3.3V = 2.2 t f Output Fa Time (Note 8) = 5. = 3.3V = V V V V V V V V V V V V ns ns ns ns ns ns ns ns ns Note 1: Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: The LTC6995C is guaranteed functiona over the operating temperature range of 4 C to 85 C. Note 3: The LTC6995C is guaranteed to meet specified performance from C to 7 C. The LTC6995C is designed, characterized and expected to meet specified performance from 4 C to 85 C but it is not tested or QA samped at these temperatures. The LTC6995I is guaranteed to meet specified performance from 4 C to 85 C. The LTC6995H is guaranteed to meet specified performance from 4 C to 125 C. The LTC6995MP is guaranteed to meet specified performance from 55 C to 125 C. Note 4: Frequency accuracy is defined as the deviation from the f equation, assuming R is used to program the frequency. Note 5: See Operation section, Tabe 1 and Figure 2 for a fu expanation of how the pin votage seects the vaue of CODE. Note 6: The pin has hysteresis to accommodate sow rising or faing signas. The threshod votages are proportiona to. Typica vaues can be estimated at any suppy votage using V (RISING) mV and V (FALLING) mV. Note 7: To conform to the Logic IC Standard, current out of a pin is arbitrariy given a negative vaue. Note 8: Output rise and fa times are measured between the 1% and the 9% power suppy eves with 5pF output oad. These specifications are based on characterization. Note 9: Setting time is the amount of time required for the output to sette within ±1% of the fina frequency after a.5 or 2 change in I. Note 1: Jitter is the ratio of the deviation of the period to the mean of the period. This specification is based on characterization and is not 1% tested. Note 11: Long-term drift of siicon osciators is primariy due to the movement of ions and impurities within the siicon and is tested at 3 C under otherwise nomina operating conditions. Long-term drift is specified as ppm/ khr due to the typicay noninear nature of the drift. To cacuate drift for a set time period, transate that time into thousands of hours, take the square root and mutipy by the typica drift number. For instance, a year is 8.77kHr and woud yied a drift of 266ppm at 9ppm/ khr. Drift without power appied to the device may be approximated as 1/1th of the drift with power, or 9ppm/ khr for a 9ppm/ khr device. 4

5 Typica Performance Characteristics = 3.3V, R = 2k, T A = 25 C uness otherwise noted. /LTC ERROR (%) Frequency Error vs Temperature Frequency Error vs Temperature Frequency Error vs Temperature GUARANTEED MAX OVER TEMPERATURE R = 5k 3 PARTS ERROR (%) GUARANTEED MAX OVER TEMPERATURE R = 2k 3 PARTS ERROR (%) GUARANTEED MAX OVER TEMPERATURE R = 8k 3 PARTS 2 GUARANTEED MIN OVER TEMPERATURE 2 GUARANTEED MIN OVER TEMPERATURE 2 GUARANTEED MIN OVER TEMPERATURE TEMPERATURE ( C) TEMPERATURE ( C) TEMPERATURE ( C) G G G3 ERROR (%) Frequency Error vs R Frequency Drift vs Suppy Votage Typica V Distribution GUARANTEED MAX OVER TEMPERATURE 3 PARTS GUARANTEED MIN OVER TEMPERATURE R (kω) DRIFT (%) REFERENCED TO = 4. R = 5k R = 2k R = 8k SUPPLY VOLTAGE (V) NUMBER OF UNITS LOTS DFN AND SOT UNITS V (V) G G G6 V (mv) V Drift vs I V Drift vs Suppy V vs Temperature 5 REFERENCED TO I = 1µA I (µa) G7 DRIFT (mv) REFERENCED TO = 4V SUPPLY (V) G8 V (V) PARTS TEMPERATURE ( C) G9 5

6 /LTC Typica Performance Characteristics = 3.3V, R = 2k, T A = 25 C uness otherwise noted. POWER SUPPLY CURRENT (µa) Suppy Current vs Suppy Votage R = 5k R = 1k R = 2k R = 8k POWER SUPPLY CURRENT (µa) Suppy Current vs Temperature , R = 1k 1 2., R = 1k 75, R = 8k 5 2., R = 8k 25 POWER SUPPLY CURRENT (µa) Suppy Current vs Pin Votage R = 8k FALLING 3.3V FALLING RISING 3.3V RISING SUPPLY VOLTAGE (V) TEMPERATURE ( C) V / (V/V) G G G12 15 Suppy Current vs R Typica I Current Limit vs 1 PIN SHORTED TO 3.5 Threshod Votage vs Suppy Votage POWER SUPPLY CURRENT (µa) = = 3.3V = 2. I (µa) PIN VOLTAGE (V) POSITIVE-GOING NEGATIVE-GOING R (kω) G SUPPLY VOLTAGE (V) G SUPPLY VOLTAGE (V) G15 PROPAGATION DELAY (ns) Reset Propagation Deay (t ) vs Suppy Votage 2 C LOAD = 5pF SUPPLY VOLTAGE (V) G16 RISE/FALL TIME (ns) Rise and Fa Time vs Suppy Votage C LOAD = 5pF t RISE t FALL SUPPLY VOLTAGE (V) G17 DELTA FREQUENCY (ppm) Typica Frequency Error vs Time (Long-Term Drift) 65 UNITS SOT-23 AND DFN PARTS T A = 3 C TIME (h) G18

7 Typica Performance Characteristics = 3.3V, R = 2k, T A = 25 C uness otherwise noted. /LTC PUT RESISTANCE (Ω) Output Resistance vs Suppy Current PUT SOURCING CURRENT PUT SINKING CURRENT SUPPLY VOLTAGE (V) G19 / / / Typica Start-Up with POL = 1 PUT RE 4ms START-UP = CODE = 15 R = 499k 5ms/ G2 RE RELEASED, 1Hz PUT CLOCK Pin Functions (DCB/S6) (Pin 1/Pin 5): Suppy Votage (2.2 to 5.). This suppy shoud be kept free from noise and rippe. It shoud be bypassed directy to the pin with a capacitor. (Pin 2/Pin 4): Programmabe Divider and Poarity Input. An interna A/D converter (referenced to ) monitors the pin votage (V ) to determine a 4-bit resut (CODE). V may be generated by a resistor divider between and. Use 1% resistors to ensure an accurate resut. The pin and resistors shoud be shieded from the pin or any other traces that have fast edges. Limit the capacitance on the pin to ess than 1pF so that V settes quicky. The MSB of CODE (POL) determines the poarity of the pin. (Pin 3/Pin 3): Frequency-Setting Input. The votage on the pin (V ) is reguated to 1V above. The amount of current sourced from the pin (I ) programs the master osciator frequency. The I current range is 1.25µA to 2µA. The output osciation wi stop if I drops beow approximatey 5nA. A resistor connected between and is the most accurate way to set the frequency. For best performance, use a precision meta or thin fim resistor of.5% or better toerance and 5ppm/ C or better temperature coefficient. For ower accuracy appications an inexpensive 1% thick fim resistor may be used. Limit the capacitance on the pin to ess than 1pF to minimize jitter and ensure stabiity. Capacitance ess than 1pF maintains the stabiity of the feedback circuit reguating the V votage. R / LTC PF C1 or (Pin 4/Pin 1): Output Reset. The reset input is used to stop the output osciator and to cear interna dividers. When reset is reeased the osciator starts with a fu haf period time interva. The output ogic state when reset is determined by the programmed CODE. The has an active high input. The LTC has an active ow input. 7

8 + /LTC Pin Functions (DCB/S6) (Pin 5/Pin 2): Ground. Tie to a ow inductance ground pane for best performance. (Pin 6/Pin 6): Osciator Output. The pin swings from to with an output resistance of approximatey 3Ω. When driving an LED or other ow impedance oad a series output resistor shoud be used to imit source/ sink current to 2mA. Bock Diagram (S6 package pin numbers shown) BIT A/D CONVERTER DIGITAL FILTER POL BIT MASTER OSCILLATOR t MASTER = 1µs V 5kΩ I MCLK FIXED IDER 124 PROGRAMMABLE IDER 1, 8, 64, , 2 15, 2 18, 2 21 PUT POLARITY 6 t HALT OSCILLATOR PUT IF I < 5nA I IDER RE V = 1V V 1 POR LTC ONLY BD I R 8

9 Operation The LTC6995 is buit around a master osciator with a Hz maximum frequency. The osciator is controed by the pin current (I ) and votage (V ), with a Hz 5k conversion factor that is accurate to ±.8% under typica conditions. f MASTER = 1 t MASTER = Hz 5kΩ I V A feedback oop maintains V at 1V ±3mV, eaving I as the primary means of controing the output frequency. The simpest way to generate I is to connect a resistor (R ) between and, such that I = V /R. The master osciator equation reduces to: f MASTER = 1 Hz 5kΩ = t MASTER R From this equation, it is cear that V drift wi not affect the output frequency when using a singe program resistor (R ). Error sources are imited to R toerance and the inherent frequency accuracy f of the LTC6995. R may range from 5k to 8k (equivaent to I between 1.25µA and 2µA). Before reaching the pin, the osciator frequency passes through a fixed 124 divider. The LTC6995 aso incudes a programmabe frequency divider which can further divide the frequency by 1, 8, 64, 512, 496, 2 15, 2 18 or The divider ratio N is set by a resistor divider attached to the pin. Hz 5kΩ f = I, or 124 N V t = 1 = N f 5kΩ V 1.24ms I with R in pace of V /I the equation reduces to: t = N R 5kΩ 1.24ms /LTC CODE The pin connects to an interna, referenced 4-bit A/D converter that determines the CODE vaue. CODE programs two settings on the LTC6995: 1. CODE determines the output frequency divider setting, N. 2. CODE determines the poarity of the and pins, via the POL bit. V may be generated by a resistor divider between and as shown in Figure 1. LTC F1 2.2 TO 5. Figure 1. Simpe Technique for Setting CODE Tabe 1 offers recommended 1% resistor vaues that accuratey produce the correct votage division as we as the corresponding N and POL vaues for the recommended resistor pairs. Other vaues may be used as ong as: 1. The V / ratio is accurate to ±1.5% (incuding resistor toerances and temperature effects) 2. The driving impedance ( ) does not exceed 5kΩ. If the votage is generated by other means (i.e., the output of a DAC) it must track the suppy votage. The ast coumn in Tabe 1 shows the idea ratio of V to the suppy votage, which can aso be cacuated as: V CODE +.5 = ±1.5% + V 16 For exampe, if the suppy is 3.3V and the desired CODE is 4, V = V = 928mV ± 5mV. Figure 2 iustrates the information in Tabe 1, showing that N is symmetric around the CODE midpoint. 9

10 /LTC Operation Tabe 1. CODE Programming CODE POL N RECOMMENDED t (kω) (kω) V / ms to ms Open Short.3125 ± ms to 131ms ± ms to 1.5sec ± ms to 8.39sec ± , sec to 67.1sec ± , sec to 537sec ± , sec to 4,295sec ± ,97,152 2,147sec to 34,36sec ± ,97,152 2,147sec to 34,36sec ± , sec to 4,295sec ± , sec to 537sec ± , sec to 67.1sec ± ms to 8.39sec ± ms to 1.5sec ± ms to 131ms ± ms to ms Short Open ±.15 POL BIT = POL BIT = t (SECONDS) V.5 V + INCREASING V F2 Figure 2. Frequency Range and POL Bit vs CODE 1

11 /LTC Operation Reset and Poarity Bit Functions The Reset input, for the and for the LTC6995-2, forces the output to a fixed state and resets the interna cock dividers. The output state when reset is determined by the poarity bit as seected by through the CODE setting. PUT (OSCILLATOR START STATE) / POLARITY LTC Osciating (Low) (Reset) 1 (Reset) Osciating (Low) 1 Osciating (High) 1 (Reset) (Reset) Osciating (High) With the POL bit programmed to be, the output wi be forced ow when reset. When reset is reeased by changing state, the osciator starts. The next rising edge at the output foows a precise haf cyce deay. With the POL bit programmed to be 1, the output wi be forced high when reset. When reset is reeased by changing state, the osciator starts. The next faing edge at the output foows a precise haf cyce deay. t WIDTH t WIDTH t t REMAINS LOW WHILE IS HIGH REMAINS LOW WHILE IS LOW t 1/2 t t LTC /2 t F3 Figure 3. Reset Timing Diagram (POL Bit = ) t WIDTH t WIDTH t t REMAINS HIGH WHILE IS HIGH REMAINS HIGH WHILE IS LOW t 1/2 t t LTC /2 t F4 Figure 4. Reset Timing Diagram (POL Bit = 1) 11

12 /LTC Operation Changing CODE After Start-Up Foowing start-up, the A/D converter wi continue monitoring V for changes. The LTC6995 wi respond to CODE changes in ess than one cyce. t CODE < 5 t MASTER < t The output may have an inaccurate puse width during the frequency transition. But the transition wi be gitch-free and no high or ow puse can be shorter than the master cock period. A digita fiter is used to guarantee the CODE has setted to a new vaue before making changes to the output. Start-Up Time When power is first appied, the power-on reset (POR) circuit wi initiate the start-up time, t START. A suppy votage of typicay 1.4V (1.2V to 1. over temperature) initiates the start-up sequence. The pin is hed ow during this time. The typica vaue for t START ranges from.5ms to 8ms depending on the master osciator frequency (independent of N ): t START(TYP) = 5 t MASTER During start-up, the pin A/D converter must determine the correct CODE before the output is enabed. The start-up time may increase if the suppy or pin votages are not stabe. For this reason, it is recommended to minimize the capacitance on the pin so it wi propery track. Less than 1pF wi not affect performance. Start-Up Behavior When first powered up, the output is hed ow. If the poarity is set for non-inversion (POL = ) and the output is enabed at the end of the start-up time, wi begin osciating. If the output is being reset ( = 1 for and = for LTC6995-2) at the end of the start-up time, it wi remain ow due to the POL bit =. When reset is reeased the osciator starts and the output remains ow for precisey one haf cyce of the programmed period. In inverted operation (POL = 1), the start-up sequence is simiar. However, the LTC6995 does not know the correct CODE setting when first powered up, so the output defauts ow. At the end of t START, the vaue of CODE is recognized and goes high (inactive) because POL = 1. If the output is being reset ( = 1 for and = for LTC6995-2) at the end of the start-up time, it wi remain high due to the POL bit = 1. When reset is reeased the osciator starts and the output remains high for precisey one haf cyce of the programmed period. Figures 7 to 1 detai the possibe start-up sequences. 2mV/ 1V/ 1V/ 1V/ 5µs = 3.3V R = 2k 1ms/ F5 = 2. CODE = 15 R = 5k 25µs/ F6 Figure 5. CODE Change from 1 to Figure 6. Typica Start-Up with = V 12

13 /LTC Operation t START 1/2 t t t START 1/2 t t LTC F7 Figure 7. Start-Up Timing Diagram (Reset =, POL Bit = ) t START 1/2 t t t START 1/2 t t LTC F8 Figure 8. Start-Up Timing Diagram (Reset = 1, POL Bit = ) t START 1/2 t t t START 1/2 t t LTC F9 Figure 9. Start-Up Timing Diagram (Reset =, POL Bit = 1) t START 1/2 t t t START 1/2 t t LTC F1 Figure 1. Start-Up Timing Diagram (Reset = 1, POL Bit = 1) 13

14 /LTC Appications Information Basic Operation The simpest and most accurate method to program the LTC6995 is to use a singe resistor, R, between the and pins. The design procedure is a 3-step process. First seect the POL bit setting and N vaue, then cacuate the vaue for the R resistor. Step 1: Seect the LTC6995 Version and POL Bit Setting Determine if the appication requires an active-high, or active-ow, LTC reset function. Otherwise the two versions share identica functionaity. The pin poarity depends on the setting of the POL bit. To force = during reset, choose POL bit =. To force = 1 during reset, choose POL bit = 1. Step 2: Seect the N Frequency Divider Vaue As expained earier, the votage on the pin sets the CODE which determines both the POL bit and the N vaue. For a given output cock period, N shoud be seected to be within the foowing range. t t ms N 1.24ms (1) To minimize suppy current, choose the owest N vaue (generay recommended). Aternativey, use Tabe 1 as a guide to seect the best N vaue for the given appication. With POL aready chosen, this competes the seection of CODE. Use Tabe 1 to seect the proper resistor divider or V / ratio to appy to the pin. Step 3: Cacuate and Seect R The fina step is to cacuate the correct vaue for R using the foowing equation. R = 5k 1.24ms t N 1 (2) Seect the standard resistor vaue cosest to the cacuated vaue. Exampe: Design a 1Hz osciator with minimum power consumption, an active-high reset input, and the pin ow during reset. Step 1: Seect the LTC6995 Version and POL Bit Setting For active-high reset seect the. For ow during reset choose POL bit =. Step 2: Seect the N Frequency Divider Vaue Choose an N vaue that meets the requirements of Equation (1), using t = 1ms: 61.4 N Potentia settings for N incude 64 and 512. N = 64 is the best choice, as it minimizes suppy current by using a arge R resistor. POL = and N = 64 requires CODE = 2. Using Tabe 1, choose = 976k and = 182k vaues to program CODE = 2. Step 3: Seect R Cacuate the correct vaue for R using Equation (2). R = 5k 1.24ms 1ms = 763k 64 Since 763k is not avaiabe as a standard 1% resistor, substitute 768k if a.7% frequency shift is acceptabe. Otherwise, seect a parae or series pair of resistors such as 576k + 187k to attain a more precise resistance. The competed design is shown in Figure 11. R 763k 2.2 TO 5. Figure 11. 1Hz Osciator 976k CODE = 2 182k F11 14

15 /LTC Appications Information Power-On Reset (POR) Function When power is appied to the LTC6995 the output is hed ow for t START, then takes on the vaue of the POL bit as the cock cyce begins. If POL = (CODE < 8) the output wi remain ow for a programmabe interva of t START + 1/2 t, assuming the pin is inactive. This makes the LTC6995 usefu as a programmabe ong-time power-on reset (POR), with the ow output used to hod a system in reset for a fixed period after power is appied. Timing begins when the suppy exceeds approximatey 1.4V. To prevent additiona output transitions after the initia POR time, the osciator can be disabed by removing the pin current. This prevents the interna master osciator output from cocking the frequency dividers or output, whie keeping it biased so it can resume operation quicky. The easiest way to impement this feature is to connect R between the and pins. Figure 12 shows the basic power-on reset function. When the haf cyce times out, the output goes high, eiminates the pin current, and stops additiona pin transitions. The output remains high unti the device is reset by driving the input or power is cyced off then back on. The POR interva is ony one haf of an osciator period so component seection is sighty different. Tabe 2 provides the component vaues required for one haf cyce time intervas. Timing starts after a short startup deay time foowing the appication of the suppy. ~1.4V STARTS TIMER POL = R 191k = FOR LTC t POR = 1 SECOND FOR VALUES SHOWN POL = CODE = 3 N = 512 t START t DELAY (1/2 t ) POWER-ON RE 28k POR TIMER STOPPED F12 Figure 12. Active Low Power-On Reset (1 Second Interva Exampe) 2.2 TO 5. Tabe 2. Power-On Reset (POR). One Shot, One Haf Cyce Deay Programming Output Low During Time Interva, POL = CODE t DELAY TIME INTERVAL (1/2 t ) (kω) (kω) ~R (kω) 512µs to 8.2ms Open Short t DELAY(MS) ms to 65.5ms t DELAY(MS) ms to 524.3ms t DELAY(MS) ms to 4.2sec 1 28 t DELAY(SEC) sec to 33.6sec t DELAY(SEC) sec to 4.5min t DELAY(MIN) min to 35.8min t DELAY(MIN) min to 4.8hrs t DELAY(HR) Note: Power-On Reset Time = t DELAY + t START 15

16 /LTC Appications Information For shorter power-on reset times (1ms to 73ms) the timer startup deay becomes a significant part of the tota POR time. To take this deay into account the vaue for R can be modified from the vaues shown in Tabe 2. For a POR time in the range from 1ms to 16ms (CODE = ), R shoud be t POR (ms) For a POR time in the range from 4.5ms to 73ms (CODE = 1), R is t POR (ms) 1.9. For onger POR times (CODE 2 through 7) the startup time is insignificant. After power on, the deay foowing a reset condition wi be in the same range as shown for t DELAY in Tabe 2 for these two CODE seections. For short POR times, a more precise estimation of the startup time can be found from the foowing: t START (µs) = ( (12 CODE) ) R (kω) 5 +8 Suppy bounce resets the interna timer so the POR circuit automaticay debounces suppy noise. POR timing starts from the time that the suppy has reached approximatey 1.4 vots. Long Timer One Shots and Deay Generators The POR circuit of Figure 12 is aso usefu when the reset inputs are driven. This creates edge triggered timing events that are active ow and can either be re-triggered or can stop after one programmed interva. The programmed time interva can range from ony 5µs to over 4 hours with just resistor vaue changes. The circuits in Figure 13 show how a POR or active ow interva can be re-started to provide a fu system reset time. The Figure 14 circuit requires an indication from the system being reset that it is ready before timing out. The LTC can accommodate an active high OK signa. By forcing a reset condition at power on the LTC6995 can be used to create a ong time deayed rising edge triggered by either a faing edge signa () or a rising edge signa (LTC6995-2) as show in Figure 15. 1k POR POR 1k LTC R R ACTIVE HIGH RE ACTIVE LOW RE RE RE POL = t START + TIMER 1/2 t 1/2 t STOPPED POL = t START + TIMER 1/2 t 1/2 t STOPPED 16 POR TIMER STOPPED POR Figure 13. System Resets On Command with Fu POR Time Interva. Reset Puse Is Debounced Automaticay POR TIMER STOPPED POR F13

17 /LTC Appications Information SYSTEM OK R POR SYSTEM POL = SYSTEM OK t START + TIMER 1/2 t 1/2 t STOPPED POR POR EXTENDED POR F14 Figure 14. Extended POR. Timer Reset During Initia POR Interva. Fu POR Interva Provided Once System Signas the OK TRIGGER PUT TRIGGER LTC PUT R R FALLING EDGE TRIGGERED POL = RISING EDGE TRIGGERED POL = TRIGGER TRIGGER PUT 1/2 t 1/2 t PUT 1/2 t 1/2 t F15 Figure 15. Long Time Deayed Rising Edge. Deay Time Can Range from 5µs to 4.8 Hours 17

18 /LTC Appications Information Watchdog Timers Using the same circuits as shown in Figure 15 with periodic pusing of the reset input can create an effective watchdog timer. A watchdog puse is required from a system within each timing interva. The watchdog timeout interva can be programmed from 5µs to 4.8 hours. If a puse is missed the output goes high to indicate that the system software may be caught in an infinite oop. This high eve can be used to initiate software diagnostic or restart procedures. The LTC6995 interna cock stops and the output remains high unti the software recovers and returns to issuing watchdog puses. Figure 16 shows the timing for this appication. Watchdog timers are used to detect if a system operating software is diverted from the designed program sequence for any reason. It is aways a possibiity that the software coud get stuck in a way that keeps the watchdog puse in the state that hods the timer in the reset so it can never time out. In this condition the watchdog timer is ineffective and wi never force corrective action. To hep to prevent this a second one shot can be used to reset the watchdog timer as shown in Figure 17. () MISSED PULSE WATCHDOG PULSES (LTC6995-2) PUT SERVICE WATCHDOG TIMER RESTARTS TIME RESUME F16 Figure 16. Watchdog Timer. Same Circuits as Shown in Figure 15 1µs ONE SHOT 5ms WATCHDOG TIMER SYSTEM POSITIVE WATCHDOG PULSE TRG LTC PUT R 619k R 64k 976k 12k RISING EDGE TRIGGERED POSITIVE PUT PULSE CODE = 1 FALLING EDGE TRIGGERED POL = CODE = 1 Figure 17. Extra-Reiabe Watchdog Timer. Aows Timeout if System Watchdog Puse Gets Stuck in the Timer Reset State. Both Timer Devices Can Share the Same CODE Setting F17 18

19 Appications Information Gated Osciators The reset input () cears a interna dividers so that, when reeased, the output wi start cocking with a fu programmed period. This edge can be used to gate the output ON and OFF at a known starting point for the cock. Circuits which count cock cyces for further timing purposes wi aways have an accurate count of fu cyces unti reset. The output cock is aways at 5% duty cyce and the period of each cyce can range from 1ms to 9.5 hours. Depending on the poarity bit seection the output cock can start high or ow as shown in Figure 18. Sef-Resetting Circuits The pin has hysteresis to accommodate sow-changing input votages. Furthermore, the trip points are proportiona to the suppy votage (see Note 6 and the Threshod Votage vs Suppy Votage curve in Typica Performance Characteristics). This aows an RC time constant at the input to generate a deay that is neary independent of the suppy votage. /LTC A simpe appication of this technique aows the LTC6995 output to reset itsef, producing a we-controed puse once each cyce. Figures 19a and 19b show circuits that produce approximatey 1µs puses once a minute. The ony difference is the version of LTC6995 used and the POL bit setting, which contros whether the puse is positive or negative. Votage Controed Frequency With one additiona resistor, the LTC6995 output frequency can be manipuated by an externa votage. As shown in Figure 2, votage V CTRL sources/sinks a current through R VCO to vary the I current, which in turn moduates the output frequency as described in Equation (3). Hz 5kΩ R V f VCO CTRL = N R R V (3) VCO ACTIVE HIGH RE FALLING EDGE STARTS THE CLOCK LTC ACTIVE LOW RE RISING EDGE STARTS THE CLOCK POL = 1/2 t POL = 1/2 t POL = 1 1/2 t POL = 1 1/2 t F18 Figure 18. Gated Osciators. First One-Haf Cyce Time Aways Accurate 19

20 /LTC Appications Information R PW 2.26k C PW 47pF R 178k 1µs PULSE WIDTH 6 SECONDS 2.2 TO k ( ) V (RISING) t PULSE = R PW C PW In 1 t PULSE 2.26kΩ 47pF In(1.61) t PULSE 1µs F19a Figure 19a. Sef-Resetting Circuit (CODE = 5) R PW 2.26k C PW 47pF R 178k LTC µs PULSE WIDTH 6 SECONDS 2.2 TO k ( ) V (FALLING) t PULSE = R PW C PW In t PULSE 2.26kΩ 47pF In(.43) t PULSE.9µs F19b Figure 19b. Sef-Resetting Circuit (CODE = 1) V CTRL R VCO R F2 Digita Frequency Contro The contro votage can be generated by a DAC (digitato-anaog converter), resuting in a digitay-controed frequency. Many DACs aow for the use of an externa reference. If such a DAC is used to provide the V CTRL votage, the V dependency can be eiminated by buffering V and using it as the DAC s reference votage, as shown in Figure 21. The DAC s output votage now tracks any V variation and eiminates it as an error source. The pin cannot be tied directy to the reference input of the DAC because the current drawn by the DAC s REF input woud affect the frequency. I Extremes (Master Osciator Frequency Extremes) When operating with I outside of the recommended 1.25µA to 2µA range, the master osciator operates outside of the 62.5kHz to Hz range in which it is most accurate. The osciator can sti function with reduced accuracy for I < 1.25µA. At approximatey 5nA, the osciator output wi be frozen in its current state. The output coud hat in a high or ow state. This avoids introducing short puses when frequency moduating a very ow frequency output. At the other extreme, it is not recommended to operate the master osciator beyond 2MHz because the accuracy of the pin ADC wi suffer. C1 Figure 2. Votage-Controed Osciator 2

21 Appications Information /LTC V CC REF D IN µp CLK LTC1659 CS/LD V 1/2 LTC678 R VCO + R C1 ( ) f Hz 5kΩ = R 1 + VCO D IN 124 N R VCO R 496 D IN = TO F21 Figure 21. Digitay-Controed Osciator Frequency Moduation and Setting Time The LTC6995 wi respond to changes in I up to a 3dB bandwidth of.4 f. Foowing a 2 or.5 step change in I, the output frequency takes ess than one cyce to sette to within 1% of the fina vaue. Power Suppy Current The power suppy current varies with frequency, suppy votage and output oading. It can be estimated under any condition using the foowing equation. This equation ignores C LOAD (vaid for C LOAD < 1nF) and assumes the output has 5% duty cyce. I S(TYP) f MASTER 7.8pF + 42kΩ I +5µA 2 R LOAD Suppy Bypassing and PCB Layout Guideines The LTC6995 is a 2.2% accurate siicon osciator when used in the appropriate manner. The part is simpe to use and by foowing a few rues, the expected performance is easiy achieved. Adequate suppy bypassing and proper PCB ayout are important to ensure this. Figure 22 shows exampe PCB ayouts for both the TSOT-23 and DFN packages using 63 sized passive components. The ayouts assume a two ayer board with a ground pane ayer beneath and around the LTC6995. These ayouts are a guide and need not be foowed exacty. 1. Connect the bypass capacitor, C1, directy to the and pins using a ow inductance path. The connection from C1 to the pin is easiy done directy on the top ayer. For the DFN package, C1 s connection to is aso simpy done on the top ayer. For the TSOT-23, can be routed through the C1 pads to aow a good C1 connection. If the PCB design rues do not aow that, C1 s connection can be accompished through mutipe vias to the ground pane. Mutipe vias for both the pin connection to the ground pane and the C1 connection to the ground pane are recommended to minimize the inductance. Capacitor C1 shoud be a ceramic capacitor. 21

22 /LTC Appications Information C1 R C1 C1 R R F22 DFN PACKAGE TSOT-23 PACKAGE Figure 22. Suppy Bypassing and PCB Layout 2. Pace a passive components on the top side of the board. This minimizes trace inductance. 3. Pace R as cose as possibe to the pin and make a direct, short connection. The pin is a current summing node and currents injected into this pin directy moduate the operating frequency. Having a short connection minimizes the exposure to signa pickup. 4. Connect R directy to the pin. Using a ong path or vias to the ground pane wi not have a significant affect on accuracy, but a direct, short connection is recommended and easy to appy. 5. Use a ground trace to shied the pin. This provides another ayer of protection from radiated signas. 6. Pace and cose to the pin. A direct, short connection to the pin minimizes the externa signa couping. 22

23 Typica Appications /LTC Timed Power Switches, Auto Shutoff After One Hour 1k PUSH TO ACTIVATE R 169k ACTIVE HIGH RE 1/2 t = 1 HOUR 887k LOW = ON HIGH = OFF 3V TO 36V 2.6V TO 5. LTC4412HV V IN SENSE GATE CTL STAT P-CHANNEL MOSFET * *DRAIN-SOURCE DIODE OF MOSFET 1µF IN LTC4411 CTL STAT C TO LOAD CURRENT DEPENDS ON PMOS SELECTION C 4.7µF TO LOAD UP TO 2.6A TA8 5 Second On/Off Timed Reay Driver 12V RUN RELAY ENABLE RE R3 118k D1 1N4148 R4 1k 392k TA2 L NO Q1 2N2219A C2 C 1 COTO 122 RELAY

24 /LTC Typica Appications 1.5ms Radio Contro Servo Reference Puse Generator R7 1k 2ms FRAME RATE GENERATOR 2ms PERIOD 1.5ms REFERENCE PULSE RE = OPEN RUN = R6 121k R4 976k R5 12k C1.1µF R3 146k TRIG LTC ms PULSE 28k C TA3 Cycing (1 Seconds On/Off) Symmetrica Power Suppies 1 IN R6 2k M2 Si4435DY 1 1 5k 1k M3 Si k R8 R9 392k C1 R3 5k M4 Si4435DY 1k 1 IN 1 M1 Si TA4 Isoated AC Load Fasher OPEN = OFF = ON R3 5 R4 1k U Ω 1 MOC R 237k SECONDS ON/OFF 392k 2 ZERO CROSSING 4 R5 5.94k R6 1k U3 NTE5642 4W LAMP R7 1Ω C2.22µF TA5 HOT 117V AC NEUTRAL AC ISOLATION BARRIER = 7 24

25 Typica Appications /LTC Interva (Wiper) Timer 5s 15s 3s 1m 2m 4m 2s + V OFF 24.9k TRIG LTC PUT 2s 178k 59k 29.4k 5s 15s 3s 1m 2m 4m 2s OFF 383k 2s 681k t INTERVAL 2 SECONDS TO 4 MINUTES TA6 9.9k 28k 113k 133k 5s 15s 3s 1m 2m 4m 2s OFF 154k Adjustabe Time Lapse Photography Intervaometer TIME LAPSE SHUTTER OPEN TIME LAPSE TRG LTC PUT SHORT LONG 66.5k 2M LONG TIMER 3s TO 3Hrs 392k 3s TO 3s 3s TO 3m 523k 3m TO 3Hrs 3m TO 3m 681k 967k SHORT LONG 56.2k 2M NON-RETRIGGERABLE ONE SHOT TIMER.3s TO 3s.3s TO 3s 3s TO 3s 681k 887k TIME LAPSE EXPOSURE TIME TA9 25

26 /LTC Package Description Pease refer to for the most recent package drawings. S6 Package 6-Lead Pastic TSOT-23 (Reference LTC DWG # ).62 MAX.95 REF 2.9 BSC (NOTE 4) 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.8 BSC (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAY PER IPC CALCULATOR.95 BSC PLCS (NOTE 3).2 BSC DATUM A 1. MAX REF NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING BSC (NOTE 3) S6 TSOT DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 DCB Package 6-Lead Pastic DFN (2mm 3mm) (Reference LTC DWG # Rev A).7 ±.5 2. ±.1 (2 SIDES) R =.115 TYP R =.5 TYP ± ± ±.5 (2 SIDES) 2.15 ±.5 PACKAGE LINE PIN 1 BAR TOP MARK (SEE NOTE 6).25 ±.5.5 BSC.2 REF 1.35 ±.5 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 3. ±.1 (2 SIDES).75 ± ±.1 (2 SIDES) PIN 1 NOTCH R.2 OR CHAMFER (DCB6) DFN ±.5.5 BSC 1.35 ±.1 (2 SIDES) BOTTOM VIEW EXPOSED PAD 26 NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE LINE M-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

27 Revision History /LTC REV DATE DESCRIPTION PAGE NUMBER A 9/13 Grammatica corrections Correction to Master Osciator, Bock Diagram Divcode changed from 4 to 5, Figure 19a Divcode changed from 11 to 1, Figure 19b LTC6995 bock identified as, Figure 21 and Figure 22 Repace with, Sentry Time schematic 1, 4, 8, , Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection For more of its information circuits as described herein wi not infringe on existing patent rights. 27

28 /LTC Typica Appication Sentry Timer Q CLK FF 1k Q CLR D PUSH BUTTON EVERY 4 HOURS OR ALARM SOUNDS LTC k 15Ω 4 HOUR TIMER CODE = 7 8Hz ALARM TONE CODE = 49.9k 6.4k 32Ω 75k 332k TA7 Reated Parts PART NUMBER DESCRIPTION COMMENTS LTC1799 Hz to 33MHz ThinSOT Siicon Osciator Wide Frequency Range LTC69 Hz to 2MHz ThinSOT Siicon Osciator Low Power, Wide Frequency Range LTC696/LTC697 1kHz to Hz or 4kHz ThinSOT Siicon Osciators Micropower, I SUPPLY = 35µA at 4kHz LTC693 Fixed Frequency Osciator, kHz to 8.192MHz.9% Accuracy, 11µs Start-Up Time, 15µA at 32kHz LTC699 TimerBox: Votage-Controed Siicon Osciator Fixed-Frequency or Votage-Controed Operation LTC6991 TimerBox: Very Low Frequency Osciator with Reset Cyce Time from 1ms to 9.5 Hours, No Capacitors, 2.2% Accurate LTC6992 TimerBox: Votage-Controed Puse Width Moduator (PWM) Simpe PWM with Wide Frequency Range LTC6993 TimerBox: Monostabe Puse Generator (One Shot) Resistor Programmabe Puse Width of 1µs to 34sec LTC6994 TimerBox: Deay Bock/Debouncer Deays Rising, Faing or Both Edges 1µs to 34sec 28 Linear Technoogy Corporation 163 McCarthy Bvd., Mipitas, CA (48) FAX: (48) LT 913 REV A PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 213