Volterra VT1195SF Synchronous Buck Voltage Regulator

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Wilfrid Terry
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1 Volterra VT1195SF Synchronous Buck Voltage Regulator Process Review with Supplementary TEM Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Process Review with Supplementary TEM Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package 3 Process Analysis 3.1 General Device Structure 3.2 Dielectrics 3.3 Metallization 3.4 Peripheral MOS Transistors 3.5 Isolation 3.6 Wells and Substrate 4 DMOS Switch Transistors 4.1 Overview and Plan-View Analysis 4.2 Cross-Sectional Analysis (Gate Length Direction) 5 Critical Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation Report Evaluation

3 Overview Overview 1.1 List of Figures 2 Device Overview Top Package View Bottom Package View Plan-View Package X-Ray Die Photograph Die Photograph DMOS Functional Layout Die Markings Annotated Die Photograph Die Corner Bond Pads Standard Logic 3 Process Analysis General Structure Die Edge and Seal Die Seal Passivation IMD 2 and IMD Pre-Metal Dielectric Metal Minimum Width Metal Minimum Width Metal Minimum Pitch Via 2s and Via 1s Minimum Pitch Contacts to Diffusion Contact to Poly Peripheral NMOS Transistor TEM Peripheral Transistor Isolation Under Poly Minimum Width Isolation SRP P-Well and Substrate SRP Capacitor N-Well SRP DMOS Transistor N-Well 4 DMOS Switch Transistors DMOS Transistors at Metal Middle of DMOS Transistor at Metal DMOS Transistors at Poly Middle of DMOS Transistor at Poly Source/Drain Areas and Interconnects P-Body and Drain Contacts Detail Source/Drain and P-Body Diffusions Source/Drain Diffusions Detail TEM DMOS Gate Oxide

4 Overview TEM DMOS Thick Oxide Silicon Etch DMOS Transistors SCM DMOS Transistor Source Diffusions and P-Body SIMS Profile

5 Overview List of Tables 1 Overview Device Identification Device Summary Process Summary 2 Device Overview Package and Die Dimensions 3 Process Analysis Dielectric Layer Thicknesses Metal and Contact Dimensions Peripheral Transistors Die Thickness and Well Depths 4 DMOS Switch Transistors DMOS Transistor Dimensions 5 Critical Dimensions Package and Die Dimensions Dielectric Layer Thicknesses Metal and Contact Dimensions Peripheral Transistors Die Thickness and Well Depths DMOS Transistor Dimensions

6 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com

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August 17, 2006 Micron MT29F2G08AAB 2 Gbit NAND Flash Memory Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor