P = P + R. Sulaiman. Diary. of a CMOS circuit can be. Where, P leak is the leakage power dissipation, P d is the. P total in the. that the a smaller

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1 International Journal of Electrical & Computer Sciences IJECS-IJENS Vol: 10 No: Complementary asss Transistor Control Unit Design for Subthreshold Current Management in Digital ortable Systems Diary R. Sulaiman Electrical Engineering Department, Engineering College, Salahaddin University, Erbil - IRAQ diariy@gmail.comm Abstract Design techniques for low ower dissipation in modern microprocessors, especially in the design of digital portable, notebook, and handheld computers are becoming increasingly important. As technology moves into deep submicron featuree sizes, the static or leakage power is expected to increase because of the exponential increase in leakage currents with technology scaling. Within die-process variation is increasing in nanometer technologies, it is observe that leakage power will become comparable to dynamic or total power dissipation in the next generation processorss in the next few years. Therefore, it is important for system designers to get an early estimate of leakage power to meet the challenging and methodologies for power dissipation reduction. This paper presents a hardware design and implementationn of the complementary pass transistor control unit for microprocessors subthreshold leakage current/power reduction based on dual supply voltage V ddl -V ddh scaling, and it can be considered as an effective mechanism for reducing processors power and energy while preserving performance by scaling the supply voltage at runtime depending on the workload variation. H-Leakage simulation program is used to verify the theoretical idea and confirm the hardware operations. Index Terms Complementary pass transistor, Subthreshold leakage current, Dual supply voltage scaling. out the sources of power dissipation, and the elements of each source with its influences. Theree are three sources of power dissipation in CMOS circuits. The total power dissipation of a CMOS circuit can be expressed as [2], = total + leak + d sc (1) Where, leak is the leakage power dissipation, d is the dynamic power dissipation, sc is the short circuit power dissipation. d is the dominant component of the total in the current manufacturing technologies which include sc also. For 0.18µm technology at 100 C, leakage power dissipation is estimated to be 7% of the total power dissipation, meaning that the rest 93% is dynamic power dissipation. As the technology scales down, for the same die in a smaller technology, at the same temperature level, leakage power dissipation percentagee is expected to go up as much as 50% in the future technology generation and become mortal to battery life of portable digital systems [3]. Figure 1 show the dynamic and leakage power of a 70nm CMOS inverter for different operating temperatures. The leakage power, which was initially 10% of the total power at room temperature, increases up to 49% as the temperature goes up to 125C I. INTRODUCTION OWER dissipation reduction, has becomee a major design concern of microprocessorss with the growth of complexity and density, especially in battery-powered digital portable devices, and emerges as a key technology in the VLSI system design. The high power dissipation results in increased packaging and cooling costs as well as potential reliability problems. Then, the low power design is required for a battery-powered device to extending the battery service life, while meeting performance requirements [1]. Today most digital circuits are constructed using CMOS circuits, especially processors, therefore the analysis of leakage power dissipation in CMOS circuits is essential to find Fig. 1. CMOS inverter dynamic and leakage power for different temperatures using the 70nm technology Leakage power ( le eak) can be expressed by the equation,

2 International Journal of Electrical & Computer Sciences IJECS-IJENS Vol: 10 No: n leak * 1 = Leakage Current SupplyVoltage (2) For the static CMOS inverter, when the transistors are off, there is still some energy dissipation occurs in the circuit because of the leakage current passing through the transistors, this leakage current can be expressed by [4], qv / KT I = i e( 1) (3) leakage s Where, i s = reverse saturation current, V = diode voltage, q = electronic charge, k = Boltzmann s constant (1.38x10 23 J/K), T = temperature [5]. Static energy dissipation is the product of the leakage current and the supply voltage from which the leakage current is drawn. - d can be expressed by the equation, d L 2 dd = C V f (4) Where, C L is the collective load capacitance, V dd is the supply voltage, and f clk is the clock frequency. When any transistor in the CMOS circuit makes a transition, the capacitances on its nodes are either charged or discharged causes dynamic power dissipation. The dynamic power dissipation directly depends on the sizes of capacitances on the terminals of the transistors. - sc can be expressed by the equation, trf scα ( Vdd 2V t ) (5) t p Where, V t is the threshold voltage, t rf is the rise time or fall time, t p is the period of the input waveform. sc is occurs when both the pull-up and pull-down transistors of a CMOS gate are simultaneously on. There are three main techniques to reduce static or leakage power dissipation in microprocessors CMOS building blocks, design and implementation of low leakage transistors, dynamic threshold modulation, and finally using dual supply voltage scaling [4,5]. The CMOS operating temperature in active mode will increase due to the switching activities of the transistors that lead to amplify leakage power, and then dual supply voltage has gained a lot of attention as an efficient method to reduce total power dissipation. During the five years ago, there are many subjects related to the topic, H. Qin in [6] presents the first analytical investigation into the voltage limit of SRAM for Low Leakage Standby Operation, M. A. Sheets in [7] presents a structured methodology and architecture for the implementation and control of power domains to form a power managed system. This paper presents a hardware design and implementation of the complementary pass transistor control unit for microprocessors subthreshold and leakage power reduction based on dual supply voltage V ddl -V ddh scaling at runtime depending on the workload variation; H-Leakage simulation program shows satisfactory results. clk II. LEAKAGE OWER ANALYSIS In high performance digital portable, handheld, and notebook computer architectures, the leakage component of total consumed power was increased with technology scaling, which exceeds 50% of the total consumed power [2,3]. There are four leakage mechanisms contribute to the total leakage current in a CMOS inverter as shown in figure 2, Fig. 2. The four main leakage components in an NMOS transistor These four leakage current components are: - Subthreshold leakage current (I SUB ) - Gate direct tunneling leakage current (I GATE ) - Reverse biased leakage current (I REV ) - Gate induced drain leakage current (I GIDL ) The subthreshold leakage current (I SUB ) is the main part in the four components above due to the diffusion current of the minority carriers in the channel for a MOS device. For a low input voltage in a CMOS inverter, the output will be high, in this case V GS is 0, but there is still a subthreshold leakage current passing in the NMOS transistor channel because of the V dd potential on the V DS. Figure 3 shows the variation of the drain current of an NMOS transistor as a function of the gate voltage in 0.18μm technology [8]. Fig. 3. The drain current of an NMOS transistor as a function of the V GS The magnitude of the subthreshold current is a function of both process, device sizing (W/L), and supply voltage V dd. The process parameter that predominantly affects the current value is V t. Reducing V t exponentially increases the subthreshold current, which is proportional to V DS, or equivalently, V dd [9]. Gate direct tunneling leakage current (I GATE ) results from the Fowler-Nordheim tunneling of electrons into the conduction band of the oxide layer under a high applied electric field across the oxide layer. I GATE depending on the tunneling probability function and the number of tunneling carriers. The magnitudes of the (I GATE ) current increases exponentially with the gate oxide thickness T ox and supply voltage V dd. As transistor length and gate oxide thickness are scaled down, supply voltage must also be reduced to maintain effective gate control over the channel region.

3 International Journal of Electrical & Computer Sciences IJECS-IJENS Vol: 10 No: Reverse biased leakage current (I REV ) occurs from the source or drain to the substrate through the reverse-biased diodes when a transistor is OFF. For an inverter with low input voltage the NMOS is OFF, the MOS is ON, and the output voltage is high. Then, the drain-to-substrate voltage of the OFF NMOS transistor is equal to the supply voltage. This cause a leakage current from the drain to the substrate through the reverse-biased diode. The magnitude of this leakage current depends on the area of the drain diffusion and the leakage current density, which is in turn determined by the doping concentration [10]. Gate induced drain leakage current (I GIDL ) is caused by high field effect in the drain junction of MOS transistors. For an NMOS transistor with grounded gate and drain potential at V dd, the I GIDL is made worse by high drain to body voltage and high drain to gate voltage. I GIDL Magnitude increases as thinner oxide and supply voltage increase. Figure 4 shows the amount leakage power prediction of the total power for the next generation CMOS technology. total power dissipation for today s processors. Then the subthreshold leakage power has become the dominant factor in the total power dissipation and battery life time due to the growing difficulty in controlling the device dimensions and characteristics. Fig. 5. Subthreshold Leakage power trends In the current CMOS technologies subthreshold leakage current is much larger than the other three leakage current components because of the lower threshold voltage and increasing short channel and drain induced barrier lowering effects, and is can be expressed by the equation, I sub = k V T V V GS t VDS 2 η VT V T e (1 e ) (6) Fig. 4. Leakage & total power Vs. CMOS technology scaling A large number of CMOS circuits stay a long time in a standby mode where the leakage power is the only source of power consumption. Respond to the continuous market demand for more functionality and high processing speed while continuing to decrease the physical size and weight of the digital portable devices offer a low cost, little volume, and light weight with minimum power dissipation technology to be a primary limitation for further advancement in portable integrated circuit technologies, enhancing the necessary of the proposed circuit for subthreshold leakage current and leakage power reduction in CMOS-VLSI designs especially in digital portable systems. III. SUBTHRESHOLD LEAKAGE CURRENT (I SUB ) Leakage power consumption has become an important factor in the design of high performance portable, handheld, and notebook processors. rocess scaling has resulted in a continual reduction in the supply voltage to reduce the total power consumption and maintain circuit performance. The subthreshold leakage power trends is shown in figure 5 [10]. The subthreshold leakage current is the current that is conducted through a transistor from its source to drain when the device is intended to be off. Because of the dramatic increase in subthreshold current as shown in figure 5, static power consumption is now one of the primary issues in deep submicron design and can account for as much as 50% of the Where, k is function of the technology, V T is the thermal voltage, V t is the threshold voltage, V GS is the gate to source voltage, V DS is the drain to source voltage, and η is the subthreshold swing coefficient [8]. It is clear from equation 6, that the reduction of threshold voltage by 100 mv increases the subthreshold leakage current by a factor of 10. Decreasing the length of transistors increases the subthreshold leakage current as well. Therefore, in a chip, transistors that have smaller threshold voltage and/or length due to process variation contribute more to the overall leakage. Although the leakage current was important in systems with both active and inactive periods. So, the subthreshold leakage current reduction is a critical design concern in any system in today s designs because it increases US or battery lifetime, reducing temperature, decreasing the production cost, and extended the IC lifetime. Dual supply voltage scaling based to complementary pass transistor control unit design is an effective technique to reduce subthreshold current, leakage power, dynamic power (equation 4), and then the total power consumption in CMOS integrated circuits, especially in portable, notebook, and handheld processors at standby and varied workload conditions. As the supply adjusted between the two values V ddl and V ddh based on the workload prediction to complete the specific task with a targeted latency. Adjusting the supply voltage restricts the operating frequency accordingly because,

4 International Journal of Electrical & Computer Sciences IJECS-IJENS Vol: 10 No: V 2 ( Vdd t ) f clk = (7) Vdd Meaning that changes in frequency are accompanied by appropriate adjustment in voltage, means that the number of transitions per unit time increases with increasing the supply voltage and clock frequency. The reduction of the leakage power, dynamic power, and total power dissipation depending on the supply voltage adjustments are shown in figure 6 [11]. will drive a high voltage gate [13]. Both of these techniques introduce additional constraints to the dual supply voltage scaling process, and reducing the obtainable energy savings. Dominoo logic, however, does not require level shifting due to the lack of the MOS tree in the domino gates, while the necessity to generate and route the additional supply voltages remains [14]. Other researchers introduced gate-level dual supply voltage assignment that requires the use of level shifters when a high voltage gate is driven by a low voltage gate. The level shifting circuitry in the optimized circuits constitutes 8% of the total energy consumption [ 15]. Battery-powered digital portable systems which are typically present in portable electronic devices such as cellular phones, notebook, and handheld computers, consist of the microprocessor, the DC/DC converter, voltage controlled oscillator (VCO), supply voltage control unit, and workload predictor as shown in the block diagram of figure 8. Fig. 6. Leakage power, dynamic power, and total power dissipation with supply voltage (V dd ) adjustment for a fixed clock frequency (f clk ) IV. COMLEMENTARY ASSS TRANSISTOR CONTROL UNIT DESIGN BASED ON ALING V DDL -V DDH SCA Microprocessors with complementary passs transistors based on dual supply voltages scaling technique have the dramatic effect on power consumption reduction when a specific computer system is in consideration; this technique can significantly reduce dissipated power withoutt degrading speed by selectively lower supply voltage (V ddl ) along non-critical delay paths or light workloads and higher supply voltage (V ddh ) among heavy workloads. This work focuses on dual supply voltage usage. However, the same technique can be used in more than two supply voltage designss as well. The main problem of designing dual supply voltage scaling in CMOS circuits is increasing leakage current in the high voltage gates when a low voltage gate is driving a high voltage gate. Figure 7 shows the case when a low voltage inverterr is driving a high voltage inverter. [12]. Fig. 8. Block diagram of A battery powered system The workload predictor unit predicts the cycles required for the next program execution tasks by calculating both the idle and event times, and then estimate the workload is it light or heavy to generate a control signal to the V dd control unit in order to select the high or low supply voltage. The control unit of the high frequency DC-DC converter applicable to dual supply voltage CMOS circuits is presented in order to provide two voltage levels with low energy consumption. The VCO (ring oscillator) converts the outputt of the DC- DC converter to a clock frequency. The DC-DC converter output with the generated clock frequency is fed to the processor. Theree are two possible methods that can be providing switching between V ddl-v ddh supply voltages and control. The first method is creating by using DC-DC buck converters for each supply voltage separately as shown in figure 9. Fig. 7. A low voltage inverter driving a high voltage inverter To solve the problem of increased leakage current additional circuit of level converter is required, but it introduced area, and energy overhead. To reduce level converter problems some researchers proposed clustered voltage scaling (CVS), in such techniques no low voltage gate Fig. 9. The supply switching control using DC-DC buck converters This method is not suitable for our proposed design because of voltage levels that produce more delay and more leakage power dissipation, and we require a change during the cycle of operation itself. Steadily a dual supply voltage can be used to provide fast and instantaneous switching between supply

5 International Journal of Electrical & Computer Sciences IJECS-IJENS Vol: 10 No: voltages. The second method is using two MOS of transistors with complementary control signals that can used to select between the two supply voltages V ddl -V ddh efficiently. The control unit calculates the workload according to the workload predictor inputs, and drives a linear feedback shift register that is used to automatically generate a lookup table. The output of the shift registers are buffered through to generate the dual enable signals to drive the two MOS transistors circuitry that can be separately controlled to select one of the V ddl -V ddh supple voltages. The complete design structure of dual supply voltage control is shown in figure 10 below, Fig. 11. A. Thomas circuit overview Using A. Thomas measurement platform circuit above is applied to 3.2GHz, V, 1GB SDRAM INTEL entium- M IV processor. The simulation results of table 1 are obtained using different Benchmark programs, TABLE I SIMULATION RESULTS OF LEAKAGE & TOTAL OWER CONSUMTION USING DIFFERENT BENCHMARK ROGRAMS. Fig. 10. The structure of the dual supply control unit This structure draws current from one of the voltage supplies to drive the output by directly connecting them to the computer system microprocessor through the DC-DC converter for a period of time depending on the workload variation. V ddl could be used to drive the circuit in an idle light workload state during the standby state, while V ddh could be adjusted during active runtime or heavy workloads to tune the circuit block so that it only operates as fast as necessary and thus reduces active leakage currents and improves process yields. So, the proposed digital circuits can actually be configured at a minimum power level during all modes of operation. Thus, the technique balances subthreshold leakage power with dynamic switching power to reduce the overall power dissipation. Standard CMOS gates were used throughout this technique because it operates at dual or multiple supply voltages efficiently and it is very robust to noise and operating temperature. So, the battery-powered portable devices are considered to employ such dual supply voltages in the design process. V. SIMULATION RESULTS The complete hardware of complementary pass transistor control based dual supply voltage scaling of figure 10 has been designed, and then simulated Using H-Leakage simulator program depending on the A. Thomas measurement platform circuitry shown in figure 11 using the best known measure key of benchmark programs [16]. A sense resistor with a value of 0.01 Ohms is used. The voltage drop is measured across the sense resistor and amplified by the LT178 current sense amplifier and sent to the pin labeled output. This voltage can be measured by placing the probes at both the output node and the ground node. Benchmarks Cycles (10 6 ) Selected ower Supply Leakage ower (W) Total ower (W) Energy Saving % VR,ROUTE V ddl GAMESS V ddh ARSER V ddl TURB3D V ddh ARMARM9E V ddl TIOMA V ddl ALU V ddh TOMCATV V ddl HYDRO2D V ddh SWIM V ddl HTELXA V ddl GTC V ddh ARATEC V ddh GZ, RG V ddl CAM V ddl The above benchmarks are used to compare the computer performance. Usually the speed of computers, in terms of the number of instructions per second, is compared using both constant supply and complementary control dual supply scaling. Benchmarks are supposed to be a standard measure of leakage power and total power for both cases. The simulation results of table 1 shows that, the leakage power consumption is about 32.48% of the total power consumption, and the saved energy is 17.78% for the used benchmark programs. The Standard erformance Evaluation Corporation (SEC) standardized set of benchmarks intends to indicate the relative performance of various machines under the same workload

6 International Journal of Electrical & Computer Sciences IJECS-IJENS Vol: 10 No: that are executed for timing purposes. The results are shown in figure 12. speeds. REFERENCES Fig. 12. Relative erformance for different Laptops and Benchmarks using V ddl -V ddh Supply voltages The simulation results of figure 12 shows enhanced effectiveness of the complementary pass transistor control based dual supply voltage V ddl -V ddh scaling of the proposed circuit, that increase the relative power/performance of the used systems for different SEC benchmarks. VI. CONCLUSION In this paper a new design technique for complementary pass transistor control unit for reducing the subthreshold leakage current of digital portable systems was proposed based on dual supply voltage scaling technique, which can be considered as an effective mechanism and critical constraint for the current and future microprocessors subthreshold current and leakage/total power consumption reduction, and can improve the energy efficiency of battery-powered processor systems, especially for portable, handheld, and notebook devices. The fully design of the proposed topology restrict the usage and problems of level converter, domino logic, and CVS circuits, and it s also area efficient. In addition, since the proposed technique does not need multi-threshold process, it is a cheaper and hence preferable. The H-Leakage simulation results yields that the leakage power consumption is about 32.48% of the total power consumption, and 17.78% of energy saving is achieved for the used benchmark programs. This technique provides significant reduction in measured system energy consumption, thus significantly extending battery life. [1] M. Horowitz, T. Indermaur, and R. Gonzalez, Low-ower Digital Design, IEEE Symposium on Low ower Electronics, pp.8-11, [2] B. H. Calhoun, and A.. Chandrakasan, Standby ower Reduction Using Dynamic Voltage Scaling and Canary Flip-Flop Structures, IEEE Journal of Solid-State Circuits, Vol. 39, No. 9, September [3] Bose., Brooks D., Irwin M., Kandemir M., Martonosi M., Vijaykrishnan N., ower-efficient Design: Modeling and Optimizations, tutorial notes, the International Symposium on Computer Architecture (ISCA-28), Goteborg, Sweden, July [4] Miyatake H., Tanaka M., Mori Y., A design for high-speed low power CMOS fully parallel content-addressable memory macros, IEEE Journal of Solid-State Circuits, Volume: 36 Issue: 6 V pp , Jun [5] N.E. Weste, K. Eshraghian, rinciples of CMOS VLSI Design, 2 nd Edition, Addison Wesley ublishers, [6] H. Qin, Deep Sub-Micron SRAM Design for Ultra-Low Leakage Standby Operation, hd thesis, University of California, Berkeley, spring [7] M. A. Sheets, Standby ower Management Architecture for Deep- Submicron Systems, hd thesis, University of California, Berkeley, spring [8] V. Kursum, Supply and Threshold Voltage Scaling Techniques in CMOS Circuits, hd Thesis, University of Rochester, New York, [9] S. Sze, hysics of Semiconductor Devices, Wiley, New York, [10] Y.Lu and V.D.Agrawal, Statistical Leakage and Timing Optimization for Submicron rocess Variation, In roceedings of 20th International Conference on VLSI Design, [11].J.M. Havinga, G.J.M. Smit, DesignTtechniques for Low ower Systems, Journal of Systems Architecture, Vol. 46, Issue 1, [12] Y. Cao, T. Sato, M. Orshansky, D. Sylvester, and C. Hu, New paradigm of redictive MOSFET and Interconnect Modeling for Early Circuit Simulation, IEEE Custom Integrated Circuits Conference roceedings (CICC 2000), pp [13] D. Chen, and J. Cong, Delay optimal low-power circuit clustering for FGAs with dual supply voltages, roceedings of the international symposium on Low power electronics and design, ISLED 04, USA, [14] S. H. Rasouli, H. Koike, K. Banerjee, High-speed low-power FinFET based domino logic, roceedings of the 2009 Asia and South acific Design Automation Conference AS-DAC 09, Japan, [15] X. Chen, Y. Wang, Y. Cao, Y. Ma, and H. Yang, roceedings of the 14 th ACM/IEEE international symposium on Low power electronics and design ISLED 09, USA, [16] A. Thomas, A Measurement latform for DVS Algorithm Development and Analysis, B.Sc. Thesis, University of Virginia, April, Therefore, the proposed technique for complementary pass transistor control based on dual supply voltage scaling is becoming commonplace in high performance portable processor systems to save power and increase processing