A High Unity Gain Bandwidth and Rail-to-Rail Operational Amplifier Design

Transcription

1 A High Unity Gain Bandwidth and Rail-to-Rail Operational Amplifier Design Department of Electrical and Computer Engineering North Carolina State University Wenxu Zhao, Zhuo Yan {wzhao2,

2 Academic Integrity Statement Academic Integrity Pledge Plagiarism is defined as copying the language, phrasing, structure, or specific ideas of others and presenting any of these as one's own, original work; it includes buying papers, having someone else write your papers, and improper citation and use of sources. When you present the words or ideas of another (either published or unpublished) in your writing, you must fully acknowledge your sources. Plagiarism is considered a violation of academic integrity whenever it occurs in written work, including drafts and homework, as well as for formal and final papers. The NCSU Policies, Regulations, and Rules on Student Discipline ( sets the standards for academic integrity at this university and in this course. Students are expected to adhere to these standards. Plagiarism and other forms of academic dishonesty will be handled through the university's judicial system and may result in failure for the project or for the course. Pledge: We have read and understood the above statement and agree to abide by the standards of academic integrity in the NCSU Policies, Regulations, and Rules on Student Discipline. Team Member: Wenxu Zhao Zhuo Yan December 5 th 2011

3 Part I Executive Summary This is an Operational Amplifier designed to achieve Rail-to-Rail input Common Mode Range and 2GHz of Unity Gain Bandwidth. With a 1.8V power supply, entire power consumption is around 4.39mW. It is able to achieve low frequency gain of 94.6dB, with a phase margin of 99 degree in unity gain feedback. The settling time for a 4pF cap load is 50ns with a slew rate of 38V/nsec. A wide swing CMFB topology is used to enable a differential output swing of 1.64V.

4 Part II Compliance Table and Design Summary Parameter Specification Our Design Low Frequency Gain 92dB 94.6dB Unity gain frequency >200MHz 2GHz Phase margin 70 deg for unity gain feedback 99 deg Settling Time <90 nsec with 4pF cap load 50 nsec Output Swing 1.6V pk-to-pk differential 1.64V Input common-mode At least 0.5V overlap Rail-to-Rail CMRR >60dB 90dB PSRR >60dB >200dB Supply Voltage 1.8V 1.8V Power dissipation <10W 4.39W Slew rate 30V/usec 38V/usec Input-referred noise voltage <10nV/ Hz 8nV/ Hz Table 1 Design Summary The Op-amp is implemented using active cascade topology with rail-to-rail input structure. Both PMOS and NMOS input differential stage provides a wider input common mode range. For the output stage, four small two stage amplifiers are used to boost the gain. Since our output common mode voltage is around mid-supply, the CMFB topology which consists of rail-to-rail source-follower buffers are used. It works pretty nice with a very wide swing outputs, which benefits us a lot. For further optimization, reducing power as well as keeping relatively enough slew rate and short settling time is needed.

5 Part III Design Discussion General Considerations We choose one stage topology instead of two stages from the very beginning, since the latter needs one more Common Mode Feedback block, which makes it less popular for our low power design goal. Even if low power is not the critical design specification in this design, we keep achieving low power in mind throughout the design phase. Before start designing, basic transistor parameters are grabbed from simulation for both PMOS and NMOS, as shown below, note the ratio is W/L = 400 nm / 180 nm. Type ucox Vth0 Ro Cgd Cgs Cdb Csb μ NMOS 0.4mA/V V 100 KΩ 140 af 480aF 45 zf 86 af 95 PMOS 0.1mA/V V 300 KΩ 120 af 520aF 41 zf 104 af 57 Table 2 Basic Parameters First of all, according to power requirement supply voltage, maximum current allowed is roughly: I MAX = P MAX Vdd = 5mA Accordingly, we set the current of per finger in current source as 50 μa. Besides, length of all current mirror transistors is set to 400 nm to reduce channel length modulation effect. Note the requirements regarding slew rate sets the minimum current we could use, especially for output stage.

6 a. Input rail-to-rail design Figure 1 Rail-to-Rail Input Common Mode Tail current first set to 100 μa for both sides. Transistors in P-Mirror and N-Mirror are set to same ratio as tail transistors. For M21 and M22, initially set to twice as wide as their corresponding input transistors. The main trick here is how to set the Vsp and Vsn. Basically, transconductance of PMOS input transistor and NMOS input transistor are plotted when input common mode voltage been swept from Gnd to Vdd, as shown in fig2. Note that the peak of two gm, actually the effective working common mode ranges of them are not overlapped. In order to achieve a better overall transconductance, Vsp and Vsn are swept from 0.5V to 1.5V to determine the optimized point. The final ratio and voltage are shown in table 3. Vsp = 900mV, Vsn = 800mV.

7 Figure 2 Transconductance of input stage Mtailp (per finger) Mtailn (per finger) Mp, Mn M11, M22 W/L Ratio 10 μm/400 nm 5 μm/400 nm 20 μm/180 nm 40 μm/180 nm Table 3 Ratio of Input Stage b. Output Stage Figure 3 Output Stage

8 For output stage, high output resistance is needed to achieve 90dB+ gain, which is roughly intrinsic gain to the fourth power. Active cascode topology is used for that purpose, with two stage amplifiers as gain boosting components. To start with, DC current is set to 300μμA for M5, M6, M7, M8 for several reasons: 1) high enough to meet slew rate requirement, 2) high enough to support rail to rail input common mode range, which need at least twice as much current as input stage, 3) relatively low to maintain considerable output resistance Then, according to output swing requirement, Vdsat of each transistor is assigned in the cascode structure, up to now, sizing ratio can be calculated, as shown in table 4 Transistor M5, M6(nmos) M3, M4 M5, M6(pmos) M7, M8 DC current 300 μa 200 μa 200 μa 300 μa Vdsat 200 mv 200 mv 200 mv 200 mv W/L 7 μm/180 nm 4.5 μm/180 nm 18 μm/180 nm 27 μm/180 nm Table 4 Ratio of Output Stage Accordingly, bias voltage of all transistors are also set as shown in table 5: Vbn1 Vbn2 Vbp1 Vbp2 700mV 900mV 1V 1.2V c. Boosting amplifier design Table 5 Bias Voltage of Output Stage For boosting amplifier used in output stage, at least 40dB gain is needed, which indicates a topology of conventional cascode or two stage amplifier. Considering that input common mode voltage for boosting amplifiers are set to 200mV (Vdsat5) and 1.6V (Vdd-Vdsat7), two stage topology is more popular, which provides wider input common mode range. d. Common Mode Feedback Several common mode feedback topologies are available, since output DC point is around mid-supply voltage, the topology which consists of rail-to-rail source-follower buffers is used. It also ensures a higher output swing. A differential compare with current mirror load is used as error amplifier, as shown in figure. Tail current here is quite important. When input common mode swing to Gnd or Vdd, M9 needs to supply twice as much current as mid-supply input common mode case, which is around 300μA. At the mean time, balance should be maintained at M7 and M8, setting the output common mode value equal to Vset.

9 To summarize, tail current should be twice as current flow through M9, which is around 600μA. e. Bias Circuit Figure 4 Common Mode Feedback Topology The bias circuit employs constant gm biasing, and using wide-swing cascode to reduce channel-length modulation. For the internal biasing voltage, diode connection is used. The start circuit use 10:1 NMOS : PMOS size inverter to ensure the low threshold, guarantee the shut off during normal operation. To achieve small current source 50 μa, the size difference between two below NMOS is small (width 10 μm versus 11 μm, length 180 nm), with resistor 886 Ω gives us exact 50 μa. The bias circuit uses diode connected transistors to provide biasing voltages for the whole circuit which are 700, 800, and 900 mv. 200 mv and 1.6V biasing are generated in the cascode current mirror structure by tuning the Voptn and Vsn voltage. f. Compensation considerations There are several internal loops needed compensation, as well as the entire Op-amp. We start with gain boosting amplifiers. 1) Gain Boosting Amplifier AC gain and phase results before compensation are plotted as following, note phase margin is around 14 degree.

10 Figure 5 AC Gain of gain boost amplifier before compensation A capacitor and resistor is added in series between outputs of two stages, creating a dominant pole as well as pushing zero to a much higher frequency, phase margin after compensation is shown in figure, phase margin is around 71 degree. Figure 6 AC Gain of gain boosting amplifer after compensation

11 2) CMFB and OTA The compensation for CMFB loop and entire Op-amp is affecting each other, they share one same first LHP pole (output), which benefits the compensation. On the other hand, when Start with entire Op-amp compensation, figure shows the phase margin before compensation. From low to high frequency, the entire Op-amp has LHP pole, LHP zero, RHP zero and LHP pole. Several rounds are being done throughout compensation, especially compromising between CMFB phase margin and entire Op-amp phase margin. Round one, start with entire Op-amp compensation. Figure 7 AC gain of Op-Amp before compensation By adding a capacitor in series with a resistor between Vout and negative input of each gain boosting amplifier, the RHP zero is pushed to much higher frequency. Two capacitors are added at Vout to ground, creating dominant pole. By doing this, unity gain bandwidth of 640MHz is achieved with a 70 degree phase margin, as shown below.

12 Figure 8 AC gain of Op-Amp after compensation However, such compensation method makes the second pole in CMFB is too close to its first pole, resulting in a phase margin less than 70 degree. It is highly possible that those capacitors across gain boosting amplifier are responsible for poor CMFB loop phase margin, since we speculate that the second pole of CMFB loop is located on drain of M7, M8. Thus, we back to the beginning and start next round of compensation. Instead of putting capacitors and resistors across gain boosting amplifier, we make use of output transistor M5, M6, M3, M4, crossing them with compensation capacitors and resistors. This time, CMFB loop phase margin is no longer badly disturbed by compensation. Plot of phase margin is appended. Last but not the least, the zero in Op-amp actually helps to reach a higher unity gain bandwidth by boosting gain at high frequency, to 2GHz.

13 Part IV Schematics a. Rail-to-Rail input stage Rail-to-Rail DC Operating Point

14 b. Output Stage Output stage parameters Output Stage DC operating point

15 c. N type Two Stage Amplifier N type Two Stage Amplifier Parameters N type Two Stage Amplifier DC Operating Point

16 d. P type Two Stage Amplifier Parameters P type Two Stage Amplifier DC Operating Point

17 e. CMFB CMFB parameters CMFB DC Operating Point

18 f. Bias Circuit Bias circuit parameters Bias circuit DC Operating Point

19 Part V Simulation Results a. AC analysis b. Output Swing

20 c. Input Common Mode Range d. Step response

21 e. CMRR f. PSRR+ PSRR-

22 g. Input-Referred Noise Voltage

23 Part VI Conclusion In this project, an operation amplifier with 2GHz unity gain bandwidth is designed using 0.18μm CMOS technology. By choosing and carefully sizing the structure of the circuit, the design performs a 94dB low frequency gain, along with 99 degree phase margin under unity gain feedback configuration. In addition, 1.64V fully differential output swing is achieved.