1. D-Type Flip-Flop or Clocked Flip-Flop

Transcription

1 INIANA UNIVESITY, EPT. OF PHYSICS, P/5 LABOATOY FALL 8 Labratry #: Cntinued Fun with Flip-Flps Gal: Learn abut and build the three main types f flip-flps and use them in useful circuits as latches, cunters, shift registers, and ne-shts.. -Type Flip-Flp r Clcked Flip-Flp The simplest f the clcked flip-flp types, the -type, simply saves at its utput () what it saw at its input () just befre the last clcking edge. The particular -type flip-flp used belw, the 7HC7, respnds t a rising edge. The -type is actually used much mre ften than the fancier J- flip-flp that we will encunter next. (a) Basic Operatin: Saving a Level; eset. Feed the input frm a breadbard slide switch. Clck the flip-flp with a "debunced" pushbuttn (the buttns n the left side f the breadbard remember that these switch terminals need pull-up resistrs, i.e., see the diagram belw...). "is-assert" ESET AN SET (smetimes called CLEA and PESET) by tying them t. "ata" frm slide switch Frm "debunced" pushbuttn S / f 7LS7 5 V cc = Gnd = 7

2 k "NO" (nrmally pen) ebuncer k "NC" (nrmally clsed) Pullup resistrs that need adding if want lgic HIGH als Cnfirm that the -type flip-flp ignres infrmatin presented t its input (, fr "data") until the flip-flp is clcked. Try asserting ESET. Yu can d this with a wire t grund; bunce is harmless here. (Why?) What happens if yu try t clck in a HIGH at while asserting ESET? Try asserting SET and ESET at the same time (smething yu wuld never d n purpse in a useful circuit!). What happens? Lk at bth utputs. What determines what state the flip-flp rests in after yu release bth? es this answer prvide a clue why yu wuld nt want t assert bth at the same time in a circuit? (b) Tggle Cnnectin: Using Feedback The feedback in the circuit belw may make yu uneasy. Hwever, the clck makes this circuit easy t analyze since it breaks the feedback path. Build this circuit and try it. S 5 First clck the circuit manually (using the pushbuttn).

3 Then clck it with a square wave frm an external functin generatr (that can g t higher frequency than the lwly breadbard functin generatr). Watch CLOC and n the scpe. What is the relatin between f clck and f? Nw yu knw why this little baby is smetimes given the fancy name "divide-by-tw". Crank up the clck rate t the functin generatrs maximum, and measure the flip-flp's prpagatin time. T d this, cnsider what vltages IN and OUT t use, as yu measure the time elapsed. Yu can settle that by asking yurself just what it is that is prpagating?. J- Type Flip-Flp (anther Clcked Flip-Flp) The J- flip-flp's strength is its versatility. It can mimic the ther imprtant flipflp types: the r T (tggle)-type. (a) Checkut: Verify the J- flip-flp's behavir (described in lecture and in yur text). is-assert SET and ESET ; drive the J and inputs frm slide switches; clck the flip-flp with a debunced signal frm the pushbuttns. Frm "debunced" pushbuttn J S 5 / f 7LS 5 V cc = Gnd = 8 Fill ut the peratin table: J n+

4 (b) Applicatins: Mimicking Others type. Try these tw variatins, and determine which is a -type and which is a T- J J In n+ In n+. J- Flip-Flp in Cunters (a) ipple Cunter The preceding J- circuit, like the earlier -type-with-feedback, can be made t tggle n every clck, r "divide-by-tw". circuit: Cascading tw such circuits allws yu t divide by fur, and s n. Build this 5 J J is-assert S and n bth as usual Watch the cunter's utput n tw LEs while clcking the circuit at a few Hz. es it "divide by fur"? If nt, yur circuit r yur understanding f this phrase may be faulty. Fix whichever ne needs fixing. Nw clck the cunter as fast as yu can, and watch CL and first and then n the scpe. Trigger n. Watch the tw 's tgether and see if yu can spt the "rippling" effect that gives the circuit its name: a lag between changes at and then.

5 (b) Synchrnus Cunter Nw alter the circuit t the frm shwn belw. This is a synchrnus cunter. 7LS 5 J J CL is-assert S and n bth as usual Nte the negatin n the CL input f the secnd flip-flp (i.e., use a inverter gate r tweaked NAN gate t get it). See if yu can use the scpe t cnfirm that the ripple delay that yu saw befre is nw gne.

6 . Shift egister The shift register belw delays the signal called "IN", and synchrnizes it t the clck. Bth effects can be useful. Yu will use this circuit in a bit as a ne-sht, that is, a circuit that generates a single pulse in respnse t a "Trigger" input (here the signal called "IN"). IN CL V cc= 7LS75 Gnd = 8 (a) Slw-mtin: first use a manual switch t drive "IN", and set the clck rate t a few Hz (using either an external functin generatr r the breadbard generatr). Watch the utputs fr each flip-flp using the breadbard LEs. Watch yur input bit "march thrugh" the flip-flps as they are clcked. (b) Nw clck the circuit with a lgic signal frm an external functin generatr, and use the breadbard's scillatr t prvide "IN". Let f clck be at least f in. Watch the utputs frm each flip-flp n the scpe.

7 Add NAN Gates: igitally-timed (synchrnus) uble-barreled One-Sht Add tw NAN gates, as shwn belw, and watch thse gates' utputs alng with TIG. Nte the effect f altering f clck. / 7LS Out B 7LS75 TIG CL V cc= Gnd = 8 Out A / 7LS (a) Slw-mtin: again, first use a manual switch t drive TIG, and set the clck rate t a few Hz. Watch the ne-sht utputs n tw f the breadbard's buffered LEs. Take TIG lw fr a secnd r s, then high. Yu shuld see first ne LE then the ther wink lw, in respnse t this lw-t-high transitin. (b) Full-speed: when yu are satisfied that the circuit wrks, drive TIG with a square wave frm ne functin generatr (the breadbard's) while clcking the device with an external functin generatr (at a higher rate). T make sure yu understand what this circuit is ding, make a timing diagram as shwn n page f yur lab manual. eep this circuit munted n yur breadbard.