Experiment EB1: FET Amplifier Frequency Response

Transcription

1 EEE106 Electronics II: : FET Amplifier Frequency Response earng Outcome O4: Analyze the operation of JFET, MOSFET and BJT amplifiers and switchg circuits 1.0 Apparatus Equipment required Components required Power Supply 1 N-channel JFET N Oscilloscope 1 Resistor 10kΩ (1/4W) igital Multimeter 1 Resistor 3.3kΩ (1/4W) 1 Breadboard 1 Resistor 3.9kΩ (1/4W) 1 Function enerator 1 Resistor kω (1/4W) 1 Mylar Capacitor 0.47µF Mylar Capacitor 0.1µF 1 Mylar Capacitor 0.01µF 1 50 kω potentiometer -- 1 Objectives: 1. Construct and test a voltage amplifier usg N-channel JFET device a common source configuration. Apply the voltage divider biasg method to set the C operatg pot (V Sq,I Sq ). Verify the estimated C operatg pot with the measured data. 3. Investigate the effect of frequency changes on the voltage ga of the amplifier, measure its frequency response and obta its operatg bandwidth. 4. Investigate the capacitance effect on the frequency response of the common source JFET amplifier Important Notes All related calculation questions that does not require experimental data must be answered before comg to the lab. You are required to show all the calculation steps when requested by the lab structor. urg the evaluation session, your lab structor may request you to demonstrate how the measurement data is obtaed and expla your experimental results. Report Submission Submit your report on the same day immediately after the experiment.

2 EEE106 Electronics II:.0 Background Theory An amplifier is a circuit that creases/decrease the put signal value and this experiment the signal to be amplified is the voltage. In this experiment you are gog to vestigate frequency response characteristic of a voltage amplifier circuit usg the N-channel JFET device Most amplifiers have relatively constant ga over a certa range of frequencies. This range of frequencies is called the bandwidth of the amplifier. The bandwidth for a given amplifier depends on the circuit component values, the type of active components and the dc operatg pot of the active component. When an amplifier is operated with its bandwidth, the current ga ( ) i A, voltage ga ( ) A, and power ga ( ) v A values are referred to as midband ga values. A simplified frequency-response curve that represents the relationship between amplifier ga and operatg frequency is shown Figure 1. p Power a A p drops at lowerfrequencies Mid-band A p drops at higher frequencies A p(mid) 0.5A p(mid) Bandwidth f c1 Frequency Figure 1: A simplified frequency response curve As the frequency-response curve shows, the power ga of an amplifier remas relatively constant across a band of frequencies. When the operatg frequency starts to go outside this frequency range, the ga begs to drop. Two frequencies of terest, fc1 and f c, are the frequencies at which power ga decreases to approximately 50% of A p(mid ). The frequencies labeled f c1 and f c are called the lower and upper cutoff frequencies of an amplifier, respectively. These frequencies are considered to be the bandwidth limits for the amplifier and thus bandwidth BW is given by BW = f c f. c1 The geometric average of f c1 and f c is called the geometric center frequency f o of an amplifier, given by f = f c f. 0 1 c When the operatg frequency is equal to f 0, the power ga of the amplifier is at its maximum value. Frequency response curves and specification sheets often list ga values that are measured decibels (db). The db power ga of an amplifier is given by f c

3 EEE106 Electronics II: A out p( db) = 10log Ap = 10log. P Positive and negative decibels of equal magnitude represent reciprocal gas and losses. A +3dB ga caused power to double while a 3dB ga caused power to be cut half. vout v Usg the basic power relationships, Pout = and P =, the power ga may be R R rewritten as Pout vout R vout R Ap( db) = 10 log = 10 log = 0 log + 10log P v R v R The voltage component of the equation is referred to as db voltage ga. When the amplifier put and out resistances are equal vout A p( db) = 0log = Av ( db). ( R = R ) v Thus, when the voltage ga of an amplifier changes by 3dB, the power ga of the amplifier also changes by 3dB. ow Frequency Response of FET Amplifier In the low frequency region of a sgle stage FET amplifier as shown Figure (a), it is the RC combations formed by the network capacitors and the network resistive parameters that determe the cutoff frequency. There are three capacitors two couplg capacitor C and C, and one bypass capacitor, C S. et us assume thatc, C and S and can be represented by short-circuit. The total resistance series with R = R + R C P C are arbitrarily large C is given by where R R R = 1 is the put impedance of the amplifier circuit. The power supplied by the signal generator is P = Vgen /( R + R ). However, the reactance X C of capacitance C is not negligible at very low frequencies. The frequency at which P is cut half is when X = R + R. Thus the lower half-power pot for gate circuit occurs at frequency C f 1 = = πr C π C 1 ( R + R ) C +V R R C R C S R V gen V R 1 R S C S Figure (a): Schematic diagram of a JFET amplifier

4 EEE106 Electronics II: C R C V S R R V gen V R1 R R S C S Figure (b): JFET amplifier low-frequency ac equivalent circuit V C g m V gs R R S Figure (c): Approximate dra circuit of JFET amplifier (assumg the resistance of the JFET dra termal, r d, is much larger than R ). When C and C S are arbitrarily large and can be represented by short-circuit, the dra circuit of the JFET amplifier is as shown Figure (c). At high frequency where C can also be represented by a short-circuit, the output power to load resistor R is P = V / R. At low frequencies where the reactance X C of capacitance C is not negligible, P out is cut half when X = R. Thus the lower half-power pot for dra circuit occurs at frequency C f 1 = πr C At the half-power pot, the output voltage reduces to times its midband value. The actual lower cutoff frequency is the higher value between f (determed by C ) and f (determed by C ). High Frequency Response of FET Amplifier The high frequency response of the FET is limited by values of ternal capacitance, as shown Figure 3(a). There is a measurable amount of capacitance between each termal pair of the FET. These capacitances each have a reactance that decreases as frequency creases. As the reactance of a given termal capacitance decreases, more and more of the signal at the termal is bypassed through the capacitance. out

5 EEE106 Electronics II: +V R R C R C C gd C ds R C V gen C gs R 1 R S C S Figure 3(a): JFET amplifier with ternal capacitors that affect the high frequency response. R C out(m) C ds C R R V gen R1 R C gs C (M) Figure 3(b): FET amplifier high frequency ac equivalent circuit. The high frequency equivalent circuit for the FET amplifier Figure 3(a) is shown Figure 3(b), cludg all the termal capacitance values. C is replaced with the Miller equivalent put and output capacitance values given as gd ( A 1) C and ( M ) = Cgd v + C gd C out( M ) = C gd Av + 1 A v A V A V C (M) C out(m) Figure 4: Miller equivalent circuit for a feedback capacitor.

6 EEE106 Electronics II: Note the absence of capacitors C, C and C S Figure 3(b), which are all assumed to be short circuit at high frequencies. From this figure, the gate and dra circuit capacitance are given by C = C + C and C = Cout ( M ) + Cds + C gs (M ) where C is the put capacitance of the followg stage. In general the capacitance C gs is the largest of the parasitic capacitances, with C ds the smallest. The high cutoff frequencies for the gate and dra circuits are then given by f H = 1 πr C and f H 1 = πr' C where R = R R and R ' = R R. At very high frequencies, the effect of C is to reduce the total impedance of the parallel combation of R 1, R and C Figure 3(b). The result is a reduced level of voltage across the gate-source termals. Similarly, for the dra circuit, the capacitive reactance of C will decrease with frequency and consequently reduces the total impedance of the output parallel branches of Figure 3(b). It causes the output voltage to decrease as the reactance becomes smaller. 3.0 Procedures 1. Before connectg the circuit of Figure 5, measure the actual resistance of R 1, R, R, R S and R as accurate as possiblewith a digital multimeter (set it to the best resistance range) and record the measured values.. Connect the common source JFET amplifier circuit as shown Figure 5 usg a breadboard (refer to Appendix B). o not connect the power supply and the function generator to the circuit yet. Keep the connectg wires on the breadboard as short as possible (< 3 cm) to reduce unwanted ductance and capacitance your circuit. 3. Set the power supply output to +1V. Connect its output to the circuit and measure its voltage V (meas) as accurate as possible with the multimeter. Calculate the gate C voltage V (cal) usg the voltage-divider rule. 4. Measure the C voltages V, V and V S at,, and S ps of the transistor as accurate as possible. Note that the measured V should be closed to the calculated V (cal), and V S should be >V sce V S must be < 0 V for N-channel JFET. 5. Before connectg the function generator to the circuit, use an oscilloscope to measure the output voltage of the generator and set it to 00 khz se-wave with a peak-to-peakvoltage of 0.1V. Press the attenuation button (ATT) of the generator for easy adjustment of its output voltage. 6. Connect the generator output to the circuit. Usg Channel 1 (CH1) of the oscilloscope (set at AC put couplg), probe the put voltage v. Usg Channel (CH) of the oscilloscope, probe the load resistor R, as shown Figure 5. Set the trigger source of the oscilloscope to CH. Adjust the trigger level on the oscilloscope to obta stable waveforms. Make sure the variable (VAR) knobs of the oscilloscope are set at the calibrated (CA ) positions.

7 EEE106 Electronics II: +V =1V CH1 (v ) Function enerator R 1 =kω R =3.3kΩ C =0.01µF 0.1µF 50Ω C =0.47µF S R =10kΩ CH (v ) V gen R =10kΩ R S =3.9kΩ C S =0.47µF Figure 5: A Common source JFET amplifier S 7. Adjust the Volts/div and Time/div to display the waveforms on the oscilloscope screen as big as possible with one to two cycles. Sketch the put AC voltage (v ) and the load voltage (v ) waveforms on the graph. Record the Time/div and Volts/div used. Note that the put and output waveforms should be approximately 180 o out of phase. 8. From your graph, determe V (pp) and V (pp) which are the peak-to-peak voltages ofv and v, respectively. Calculate the voltage ga (A v ) of the JFET amplifier circuit at 00 khz.ask the structor to check all of your results. You must show the oscilloscope waveforms to the structor. 9. Sweep the frequency of the function generator from 1 khz to 550 khz (use smaller frequency steps near the half-power pot while larger steps can be used at mid-band frequencies). Record the peak-to-peak voltages of v (CH1) and v (CH) and calculate the db magnitude of the voltage ga A v. Use both coarse and fe adjustment knobs of the function generator for frequency adjustment. 10. Plot a curve of A v versus frequency. 11. Calculate the lower cutoff frequency f (cal) (use the measured R and R values). Set the frequency to 0 khz. To measure the lower cutoff frequency (f ), decrease the generator frequency until V (pp) decreases to 0.707V,mid-band(pp), where V,mid-band(pp) is the V (pp) value the mid-band. 1. Set the frequency to 300 khz. To measure the upper cutoff frequency (f H ), crease the generator frequency until V (pp) decreases to 0.707V,mid-band(pp). 13. eterme the bandwidth (BW) and the geometric center frequency (f o ) of the amplifier from the above measurements. Ask the structor to check all of your results. You must show the oscilloscope waveforms at 550 khz to the structor. 14. esign or modify the circuit Figure 5 order to measure the parameter of the device, namely ate-source Cutoff Voltage (V S(off) or V p ) and Zero-ate Voltage Current (I SS ). These two values can be used the Shockley equation I = I SS (1 V S /V p ). Ht: You can use a potentiometer and/or negative power source the circuit. By solvg the simultaneous equation of the Shockley equation and the load le equation, you can obta the calculated value for the Q pot V SQ, V SQ, I Q.. Compare this with the measured value.

8 EEE106 Electronics II: APPENIX A The Resistor color code chart Capacitance ABC.abc AB x 10 C pf 0.abcµF Potentiometer A Var B og Scale The distance a decade of the log scale the figure below is x mm. Sce log 10 1 = 0, it is used as a refernce pot (0 mm) the lear scale. Then, the readg 10 is located at x mm and the readg 0.1 is located at x mm. For a readg F, it is located at [1og 10 (F)]*x mm. E.g.: Readg 0.5 is located at [1og 10 (0.5)]*x mm = -0.60x mm Readg.5 is loacted at [1og 10 (.5)]*x mm = 0.398x mm Readg 5 is located at [1og 10 (5)]*x mm = 1.398x mm (not shown the figure) Readg 50 is located at [1og 10 (50)]*x mm =.398x mm (not shown) Conversely, a pot at z mm location is read as E.g.: -0.3x mm is read as 10 (-0.3x/x) = x mm is read as 10 (0.6x/x) = x mm is read as 10 (1.5x/x) = 31.6 (not shown).7x mm is read as 10 (.7x/x) = 501 (not shown) z / x x -x x 0.6x -0.60x x ear scale (mm) og scale (unit)

9 EEE106 Electronics II: Appendix B: Breadboard Internal Connections Horizontally connected Internal connections Horizontally connected +V CC 0.1 µf Vertically connected Vertically connected V N Internal connections MultimediaUniversity eneral mistakes: The legs of the resistors and the transistor are shorted by the breadboard ternal connections. FOE

10 EEE106 Electronics II: STUENT'S NAME: I NO: SUBJECT COE AN TITE: EEE106 EECTRONICS EXPERIMENT TITE: EB1 - FET Amplifier Frequency Response EXPERIMENT ATE: Criteria 1 (Need Improvement) (Satisfactory) 3 (ood) 4 (Excellent) ata Collection and Settg up the Experiment 1 Ability to construct the Unable to construct the Able to construct the Able to construct the Able to construct the amplifier amplifier circuit on the amplifier circuit, and not amplifier circuit amplifier circuit. circuit correctly, with neat and breadboard askg for help. partially. tidy placement of components and jumper wires Ability to set-up the power supply for the circuit, the function generator to the amplifier and to connect the oscilloscope to display the waveform 3 Ability to extract the midband amplifier's characteristics. 4 Ability to extract the amplifier's complete frequency response. 5 Ability to answer the questions by Oral Assessment Unable to setup the C or AC put to the amplifier, and not askg for help. No voltage ga is observed, and not askg for help. There is no difference between the low-, midand high-frequency response of the amplifier. Not able to answer the question, no attempt was made to answer Able to setup the C and AC put to the amplifier partially. Analysis and Conclusions No voltage ga is observed, but the waveforms are approximately at opposite phase. Mor differences between the low-, midand high-frequency response of the amplifier. Able to answer questions with some basics answers and demonstrate some attempts to refer to the text books, notes, lab sheet C and AC put to the amplifier is correctly setup. Voltage ga is more than unity, with the put and output at approximately opposite phase. ow-, mid- and highfrequency response of the amplifier shows some difference. Able to answer most part of the questions, with some explanations and elaborations and demonstrate some attempts to refer to text books, notes or lab sheet TIME: C and AC put to the amplifier is correctly setup and the waveforms are visible the oscilloscope. The voltage ga is fair, with the put and output at opposite phase. ow-, mid- and high-frequency response of the amplifier is clearly seen on a graph. Answered all correctly with proper explanations and elaborations, without a need to refer to any references. Ratg Awarded by Assessor

11 EEE106 Electronics II : FET Amplifier Frequency Response ab Report (Submit your report on the same day immediately after the experiment) Name: Student I..: ate: Majorg: roup: Table No.: 1. Table E1: Measured resistance values R R 1 R R S R [5 marks] 3. V (meas) = V, V (cal) = V [ marks] 4. Table E: Measured C voltages V V V S 7. raph E1: v and v waveforms at 00 khz [3 marks] Time base : s/div, CH1 (v ) : V/div, CH (v ) : V/div CH1 & CH ground [5 marks] V( pp) 8. A v = = at 00 khz [1 mark] V ( pp)

12 EEE106 Electronics II 9. Table E3: Measure V (pp) and V (pp), and calculated A V f /khz V (pp) /V V (pp) /V A v (db) [6 marks] 10. raph E: A v versus frequency 11. f 1 ( = = Hz π cal ) (meas) ( R + R ) C f = Hz [5 marks] 1. f H(meas) = khz 13. BW = f H f = khz f = f f = khz o H [5 marks]

13 EEE106 Electronics II Questions 1. Identify the sources of error the calculated V (cal).. Calculate the actual C currents flowg through R and R S, respectively, I R and I RS (calculation steps must be cluded). Expla why they are the same. 3. What is the measured Q-pot value (V SQ, V SQ, I Q ) of the JFET amplifier circuit? Analyze and compare this with the calculated one. 4. Estimate the lower cutoff frequency of the put circuit, f (show your calculation steps). 5. Estimate the total output capacitance which determes the upper cutoff frequency f H [15 marks] iscussion 1. Identify how the v and v waveforms Step 7 are related terms of positive and negative peak voltages, waveform shapes and phase shift. 3

14 EEE106 Electronics II. escribe the A v versus frequency characteristic. 3. Expla the difference between the calculated f (cal) and the measured f. 4. Propose why f H cannot be calculated and as to what factor determes this f H. [16 marks] Conclusion. [7 marks] 4