NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. *MR for LS160A and LS161A *SR for LS162A and LS163A

Transcription

1 BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS The LS160A/ 161A/ 162A/ 163A are hgh-speed 4-bt synchronous counters. They are edge-trggered, synchronously presettable, and cascadable MSI buldng blocks for countng, memory addressng, frequency dvson and other applcatons. The LS160A and LS162A count modulo 10 (BCD). The LS161A and LS163A count modulo 16 (bnary.) The LS160A and LS161A have an asynchronous Master Reset (Clear) nput that overrdes, and s ndependent of, the clock and all other control nputs. The LS162A and LS163A have a Synchronous Reset (Clear) nput that overrdes all other control nputs, but s actve only durng the rsng clock edge. BCD (Modulo 10) Bnary (Modulo 16) Asynchronous Reset LS160A LS161A Synchronous Reset LS162A LS163A Synchronous Countng and Loadng Two Count Enable Inputs for Hgh Speed Synchronous Expanson Termnal Count Fully Decoded Edge-Trggered Operaton Typcal Count Rate of 35 MHz ESD > 3500 Volts CONNECTION DIAGRAM DIP (TOP VIEW) SN54/74LS160A SN54/74LS161A SN54/74LS162A SN54/74LS163A BCD DECADE COUNTERS/ 4-BIT BINARY COUNTERS LOW POWER SCHOTTKY 1 1 J SUFFIX CERAMIC CASE N SUFFIX PLASTIC CASE VCC Q0 Q1 Q2 Q3 PE *R P0 P1 P2 P3 CEP GND NOTE: The Flatpak verson has the same pnouts (Connecton Dagram) as the Dual In-Lne Package. *MR for LS160A and LS161A *SR for LS162A and LS163A 16 1 ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD D SUFFIX SOIC CASE 751B-03 Ceramc Plastc SOIC PIN NAMES LOADING (Note a) HIGH LOW PE P0 P3 CEP MR SR Q0 Q3 Parallel Enable (Actve LOW) Input Parallel Inputs Count Enable Parallel Input Count Enable Trckle Input Clock (Actve HIGH Gong Edge) Input Master Reset (Actve LOW) Input Synchronous Reset (Actve LOW) Input Parallel Outputs (Note b) Termnal Count Output (Note b) 1.0 U.L. 1.0 U.L. 1.0 U.L. 10 U.L. 10 U.L. 5 (2.5) U.L. 5 (2.5) U.L LOGIC SYMBOL PE CEP P0 P1 P2 P3 *R Q 0 Q1 Q2 Q3 15 NOTES: a) 1 TTL Unt Load (U.L.) = 40 µa HIGH/1.6 LOW. b) The Output LOW drve factor s 2.5 U.L. for Mltary (54) and 5 U.L. for Commercal (74) Temperature Ranges VCC = PIN 16 GND = PIN 8 *MR for LS160A and LS161A *SR for LS162A and LS163A 5-1

2 STATE DIAGRAM LS160A LS162A LS161A LS163A LOGIC EQUATIONS Count Enable = CEP PE for LS160A & LS162A = Q 0 Q 1 Q 2 Q 3 for LS161A & LS163A = Q 0 Q 1 Q 2 Q 3 Preset = PE + (rsng clock edge) Reset = MR (LS160A & LS161A) Reset = SR + (rsng clock edge) Reset = (LS162A & LS163A) NOTE: The LS160A and LS162A can be preset to any state, but wll not count beyond 9. If preset to state 10, 11, 12, 13,, or 15, t wll return to ts normal sequence wthn two clock pulses. FUNCTIONAL DESCRIPTION The LS160A/ 161A/ 162A/ 163A are 4-bt synchronous counters wth a synchronous Parallel Enable (Load) feature. The counters consst of four edge-trggered D flp-flops wth the approprate data routng networks feedng the D nputs. All changes of the Q outputs (except due to the asynchronous Master Reset n the LS160A and LS161A) occur as a result of, and synchronous wth, the LOW to HIGH transton of the Clock nput (). As long as the set-up tme requrements are met, there are no specal tmng or actvty constrants on any of the mode control or data nputs. Three control nputs Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trckle () select the mode of operaton as shown n the tables below. The Count Mode s enabled when the CEP,, and PE nputs are HIGH. When the PE s LOW, the counters wll synchronously load the data from the parallel nputs nto the flp-flops on the LOW to HIGH transton of the clock. Ether the CEP or can be used to nhbt the count sequence. Wth the PE held HIGH, a LOW on ether the CEP or nputs at least one set-up tme pror to the LOW to HIGH clock transton wll cause the exstng output states to be retaned. The AND feature of the two Count Enable nputs ( CEP) allows synchronous cascadng wthout external gatng and wthout delay accumulaton over any practcal number of bts or dgts. The Termnal Count () output s HIGH when the Count Enable Trckle () nput s HIGH whle the counter s n ts maxmum count state (HLLH for the BCD counters, HHHH for the Bnary counters). Note that s fully decoded and wll, therefore, be HIGH only for one count state. The LS160A and LS162A count modulo 10 followng a bnary coded decmal (BCD) sequence. They generate a output when the nput s HIGH whle the counter s n state 9 (HLLH). From ths state they ncrement to state 0 (LLLL). If loaded wth a code n excess of 9 they return to ther legtmate sequence wthn two counts, as explaned n the state dagram. States 10 through 15 do not generate a output. The LS161A and LS163A count modulo 16 followng a bnary sequence. They generate a when the nput s HIGH whle the counter s n state 15 (HHHH). From ths state they ncrement to state 0 (LLLL). The Master Reset (MR) of the LS160A and LS161A s asynchronous. When the MR s LOW, t overrdes all other nput condtons and sets the outputs LOW. The MR pn should never be left open. If not used, the MR pn should be ted through a resstor to VCC, or to a gate output whch s permanently set to a HIGH logc level. The actve LOW Synchronous Reset (SR) nput of the LS162A and LS163A acts as an edge-trggered control nput, overrdng, CEP and PE, and resettng the four counter flp-flops on the LOW to HIGH transton of the clock. Ths smplfes the desgn from race-free logc controlled reset crcuts, e.g., to reset the counter synchronously after reachng a predetermned value. MODE SELECT TABLE *SR PE CEP Acton on the Rsng Clock Edge ( ) L X X X RESET (Clear) H L X X LOAD (Pn Qn) H H H H COUNT (Increment) H H L X NO CHANGE (Hold) H H X L NO CHANGE (Hold) *For the LS162A and *LS163A only. H = HIGH Voltage Level L = LOW Voltage Level X = Don t Care 5-2

3 GUARANTEED OPERATING RANGES Symbol Parameter Mn Typ Max Unt VCC Supply Voltage TA Operatng Ambent Temperature Range IOH Output Current Hgh 54, IOL Output Current Low LS160A and LS161A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwse specfed) Lmts Symbol Parameter Mn Typ Max Unt Test Condtons VIH Input HIGH Voltage 2.0 V VIL Input LOW Voltage V Guaranteed Input HIGH Voltage for Guaranteed Input LOW Voltage for VIK Input Clamp Dode Voltage V VCC = MIN, IIN = 18 V C VOH VOL Output HIGH Voltage Output LOW Voltage V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table 54, V IOL = 4.0 VCC = VCC MIN, VIN =VIL or VIH V IOL = 8.0 per Truth Table IIH IIL Input HIGH Current MR, Data, CEP, Clock PE, MR, Data, CEP, Clock PE, Input LOW Current MR, Data, CEP, Clock PE, µa VCC = MAX, VIN = 2.7 V IOS Short Crcut Current (Note 1) VCC = MAX ICC Power Supply Current Total, Output HIGH Total, Output LOW Note 1: Not more than one output should be shorted at a tme, nor for more than 1 second VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX 5-3

4 LS162A and LS163A DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwse specfed) Lmts Symbol Parameter Mn Typ Max Unt Test Condtons VIH Input HIGH Voltage 2.0 V VIL Input LOW Voltage V Guaranteed Input HIGH Voltage for Guaranteed Input LOW Voltage for VIK Input Clamp Dode Voltage V VCC = MIN, IIN = 18 VOH VOL Output HIGH Voltage Output LOW Voltage V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table 54, V IOL = 4.0 VCC = VCC MIN, VIN =VIL or VIH V IOL = 8.0 per Truth Table IIH IIL Input HIGH Current Data, CEP, Clock PE,, SR Data, CEP, Clock PE,, SR Input LOW Current Data, CEP, Clock, PE, SR µa VCC = MAX, VIN = 2.7 V IOS Short Crcut Current (Note 1) VCC = MAX ICC Power Supply Current Total, Output HIGH Total, Output LOW Note 1: Not more than one output should be shorted at a tme, nor for more than 1 second. AC CHARACTERISTICS (TA = 25 C) Lmts VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX Symbol Parameter Mn Typ Max Unt Test Condtons fmax Maxmum Clock Frequency MHz Propagaton Delay Clock to Propagaton Delay Clock to Q Propagaton Delay to MR or SR to Q ns ns ns ns VCC = 5.0 V CL = 15 pf 5-4

5 AC SETUP REQUIREMENTS (TA = 25 C) Symbol Parameter Mn Lmts Typ Max Unt Test Condtons tw Clock Pulse Wdth Low 25 ns tw MR or SR Pulse Wdth 20 ns ts Setup Tme, other* 20 ns ts Setup Tme PE or SR 25 ns VCC = 5.0 V th Hold Tme, data 3 ns th Hold Tme, other 0 ns trec Recovery Tme MR to 15 ns *CEP, or DATA DEFINITION OF TERMS SETUP TIME (ts) s defned as the mnmum tme requred for the correct logc level to be present at the logc nput pror to the clock transton from LOW to HIGH n order to be recognzed and transferred to the outputs. HOLD TIME (th) s defned as the mnmum tme followng the clock transton from LOW to HIGH that the logc level must be mantaned at the nput n order to ensure contnued recognton. A negatve HOLD TIME ndcates that the correct logc level may be released pror to the clock transton from LOW to HIGH and stll be recognzed. RECOVERY TIME (trec) s defned as the mnmum tme requred between the end of the reset pulse and the clock transton from LOW to HIGH n order to recognze and transfer HIGH Data to the Q outputs. AC WAVEFORMS Q tw(h) tw(l) OTHER CONDITIONS: PE = MR (SR) = H CEP = = H MR Q0 Q1 Q2 Q3 tw trec OTHER CONDITIONS: PE = L P0 = P1 = P2 = P3 = H Fgure 1. Clock to Output Delays, Count Frequency, and Clock Pulse Wdth Fgure 2. Master Reset to Output Delay, Master Reset Pulse Wdth, and Master Reset Recovery Tme 5-5

6 AC WAVEFORMS (contnued) COUNT ENABLE TRICKLE INPUT TO TERMINAL COUNT OUTPUT DELAYS The postve pulse occurs when the outputs are n the (Q0 Q1 Q2 Q3) state for the LS160 and LS162 and the (Q0 Q1 Q2 Q3) state for the LS161 and LS163. Fgure 3 OTHER CONDITIONS: = PE = CEP = MR = H CLOCK TO TERMINAL COUNT DELAYS The postve pulse s concdent wth the output state (Q0 Q1 Q2 Q3) state for the LS161 and LS163 and (Q0 Q1 Q2 Q3) for the LS161 and LS163. Fgure 4 OTHER CONDITIONS: PE = CEP = = MR = H SETUP TIME (ts) AND HOLD TIME (th) FOR PARALLEL DATA INPUTS The shaded areas ndcate when the nput s permtted to change for predctable output performance. P0 P1 P2 P3 Q0 Q1 Q2 Q3 th(h) = 0 th(l) = 0 Fgure 5 OTHER CONDITIONS: PE = L, MR = H SETUP TIME (ts) AND HOLD TIME (th) FOR COUNT ENABLE (CEP) AND () AND PARALLEL ENABLE (PE) INPUTS The shaded areas ndcate when the nput s permtted to change for predctable output performance. SR or PE Q RESPONSE TO PE RESET th (L) = 0 t h(h) = 0 PARALLEL LOAD (See Fg. 5) COUNT MODE (See Fg. 7) COUNT OR LOAD CEP th(h) = 0 th(l) = 0 th(h) = 0 th(l) = 0 COUNT HOLD HOLD Q RESPONSE TO SR Fgure 6 Q OTHER CONDITIONS: PE = H, MR = H Fgure 7 5-6