Extremely Scaled Silicon Nano-CMOS Devices

Transcription

1 Extremely Scaled Silicon Nano-CMOS Devices LELAND CHANG, STUDENT MEMBER, IEEE, YANG-KYU CHOI, DAEWON HA, PUSHKAR RANADE, SHIYING XIONG, JEFFREY BOKOR, FELLOW, IEEE, CHENMING HU, FELLOW, IEEE, AND TSU-JAE KING, SENIOR MEMBER, IEEE Invited Paper Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of the key elements of these technologies are described, including sublithographic patterning, the effects of crystal orientation and roughness on carrier mobility, gate work function engineering, circuit performance, and sensitivity to process-induced variations. Keywords CMOS, FinFET, metal gate, molybdenum, MOSFET, nanotechnology, scaling, ultrathin body (UTB). I. INTRODUCTION Rapid advances in the semiconductor industry have led to the proliferation of electronic devices and information technology. Integrated circuits (ICs) based upon silicon MOSFETs can perform functions such as computing, signal processing, and information storage efficiently and cheaply, and are, thus, used in virtually every electronic device produced today. Over the past three decades, by reducing transistor gate lengths with each new generation of manufacturing technology, steady improvements in circuit performance (speed) and cost per function have been achieved. However, continued transistor scaling will not be as straightforward in the future as it has been in the past because fundamental materials and process limits are rapidly Manuscript received December 19, 2002; revised June 2, This work was supported by the Semiconductor Research Corporation under Contract 2000-NJ-850 and the Microelectronics Advanced Research Corporation under Contract 2001-MT-887. L. Chang, Y.-K. Choi, D. Ha, P. Ranade, S. Xiong, J. Bokor, and T.-J. King are with the Electrical Engineering and Computer Sciences Department, University of California, Berkeley, CA USA. C. Hu is with the Taiwan Semiconductor Manufacturing Corporation, Hsin-chu, Taiwan 300, R.O.C., on leave from the Electrical Engineering and Computer Science Department, University of California, Berkeley, CA USA. Digital Object Identifier /JPROC Fig. 1. Cross-sectional schematics of various MOSFET structures. (a) the classic bulk-si structure. (b) UTB SOI structure. (c) DG structure. The classic structure utilizes very heavy channel doping (localized to halo regions near to the source/drain junctions) to suppress subthreshold leakage current. This results in degraded carrier mobility and ON current. The advanced structures utilize a very thin channel (thickness T ) to suppress leakage more effectively. being approached [1]. In the future, bulk-si MOSFETs will require high-permittivity (high- ) gate dielectrics and metal gate electrodes, as well as low-resistance ultrashallow junctions, in order to meet the stringent specifications of the International Technology Roadmap for Semiconductors (ITRS) [2]. Techniques such as semiconductor band-gap and strain engineering to improve device transconductance and on-state current may also be required [3]. Advanced MOSFET structures (Fig. 1) such as the ultrathin-body (UTB) silicon-on-insulator (SOI) single-gate transistor and the double-gate (DG) transistor can be scaled more aggressively than the classic bulk-si structure [4], [5] and, hence, may be adapted for IC production as early as the 65-nm technology node (25-nm physical gate length) [2]. However, these advanced structures have distinctly different materials and process technology requirements and associated challenges. This paper begins by discussing the significant circuit performance advantages that advanced transistor structures can provide. Metallic gate electrodes will be necessary in order for these devices to provide the maximum performance benefit over bulk-si MOSFETs; therefore, the development of metal gate technology for fully depleted SOI CMOS devices /03$ IEEE 1860 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003

2 is described. Design considerations, fabrication process details, and measured electrical characteristics are then presented in turn for the UTB and DG structures. Ultimate limits for CMOS scaling are discussed, and practical consideration is then given to the effects of process-induced variations on transistor performance and their implications for manufacturing processes. II. CIRCUIT PERFORMANCE ENHANCEMENT OF THIN-BODY MOSFETS While it may be possible to scale the traditional bulk MOSFET device structure down into the 10-nm gate length regime [6], a heavy channel doping will likely be required to control short-channel effects. This presents a challenge in terms of device fabrication because a heavy halo implant must be localized close to the surface underneath the gate edge. However, even if this is achievable, it will likely result in the degradation of device performance. Because thin-body devices can control short-channel effects with only intrinsic doping in the channel, significant performance enhancements can be expected [7]. In a bulk device with a heavily doped channel, carrier mobility will be severely degraded due to impurity scattering and an increased transverse electric field. Above a concentration of 2 10 cm, mobility is expected to be noticeably affected by channel dopants [8]. In addition, significant depletion charge in the channel will form, thus increasing the average vertical field experienced by a carrier in the inversion layer and increasing the effects of phonon and interface scattering [9]. Furthermore, this increased depletion charge will result in a larger depletion capacitance and subthreshold slope. As a result, for a given off-state leakage current specification, the threshold voltage must be raised, thus reducing the on-state drive current. A large channel doping will also inevitably enhance band-to-band tunneling leakage between the body and drain [10]. This will be especially important because abrupt halo doping profiles in the channel are desirable to localize the heavy channel doping whereas abrupt drain doping profiles are desirable for the reduction of series resistance. Together, these effects will greatly increase band-to-band tunneling, which could eventually become the dominant off-state leakage mechanism in the transistor. In UTB and DG devices, short-channel effects are controlled by a thin silicon film, thus allowing for gate-length scaling down to the 10-nm regime [11] without the use of channel dopants. With a lightly doped channel, DG and UTB devices have negligible depletion charge and capacitance, which yields a steep subthreshold slope. DG devices show even better subthreshold slope than their UTB counterparts due to better short-channel effect control by the DG structure. Lower transverse electric field and negligible impurity scattering contribute to increased mobility that further improves the drive current in both devices. With respect to circuit performance, DG and UTB devices provide an additional advantage in that the capacitive load is decreased by the elimination of both depletion and junction capacitances. Fig. 2. DG maintains a 40% FO4 inverter delay improvement over bulk devices. The UTB improvement disappears at small L because of poor short-channel effect control in a 5-nm body, especially in the PMOS. To meet leakage specifications, V must therefore be extremely high. Fig. 2 quantifies the benefits of DG and UTB devices in terms of inverter gate delay through simulation using realistic device structures based on ITRS specifications [2] for sub-50-nm gate length technology generations. Body thickness requirements for each gate length are derived from scaling rules presented in [12] for DG devices; for single-gate UTB devices, body thicknesses are assumed to be half this value. Mixed-mode device simulation [13] is employed using the energy balance model for carrier transport. Because the full Boltzmann equation is not solved, drain current values may be overestimated [14], but the trends and differences between device technologies should still be valid. Quantum effects, including carrier confinement due to body thickness scaling, which can increase the device threshold voltage [15], and carrier scattering due to quantum charge transport, which may affect current distribution in the channel [16], are not considered. For DG and UTB devices, the enhancement in drive current at a given off-state current specification leads directly to an improvement in inverter delay. An additional speedup ( 5% 10%) results from the elimination of depletion and junction capacitances. As shown in Fig. 2, improvements in fanout of four (FO4) inverter delay over bulk devices are in the 30% 40% range. The amount of improvement shown here is smaller than that reported in [7] due primarily to the realistic doping profiles used. Series resistance is, thus, considered in this work, which lessens the improvements associated with the intrinsic device structure. For all technologies, the DG device shows a larger enhancement over traditional bulk-si MOSFETs than the UTB case because of improved short-channel effects. It is possible, however, that body thickness scaling may be limited to 5 nm [17]. In that case, UTB devices at 25-nm gate lengths and below, which need body thicknesses below 5 nm to adequately control short-channel effects, can show severely degraded device performance. Because DG and UTB devices exhibit better short-channel effects, which become more important at small gate lengths, it could be expected that the delay improvement should increase with technology scaling. However, the value stays relatively constant with technology scaling following ITRS specifications because the roadmap allows a dramatic rise CHANG et al.: EXTREMELY SCALED SILICON NANO-CMOS DEVICES 1861

3 Fig. 3. V can be lowered in thin-body devices to reduce energy consumption per transition. When the delay is matched to that of bulk, a reduction of up to 60% can be observed. As with delay, the UTB improvement disappears at small gate lengths if T is limited to 5 nm. in the off-state leakage current specification based on the expectations of bulk-si MOSFET scaling. Thin-body devices essentially improve the tradeoff between gate delay and energy consumption. Given a delay specification, the advantage of thin-body MOSFETs can be expressed in terms of energy consumption, since the power supply voltage can be reduced to match the delay of a bulk-si device. Since energy is a quadratic function of the power supply voltage, this can result in a dramatic improvement in energy. In this scenario, thin-body devices can show up to a 60% reduction in energy consumption (Fig. 3). Ideally, since channel dopants are not necessary in thin-body MOSFETs, threshold voltage adjustment is achieved by gate work function engineering. However, until suitable gate materials become available, alternative methods of controlling the threshold voltage may need to be used [11]. The use of channel dopants is one solution to control the threshold voltage; however, this brings problems with reduced mobility and random dopant fluctuations [18]. An asymmetric DG structure can also achieve an appropriate threshold voltage by using n and p polysilicon gates in the DG device; this is, however, at the cost of increased transverse electric field, since a built-in potential exists through the body due to the asymmetric gate work functions. As a result, both channel doping and an asymmetric DG result in degraded device performance (Fig. 4). This emphasizes the need for gate work function engineering as alternative solutions can negate the performance benefits of thin-body devices. III. METAL GATE CMOS TECHNOLOGY For thin-body transistors with undoped channels, gate work functions must be chosen such that the gate Fermi level falls between 0.2 V of (intrinsic Si Fermi level) [11]. These work function values are needed for low and complementary CMOSFET devices. This requirement precludes the use of doped poly-si as the gate electrode. Metallic materials are, thus, likely to replace poly-si for this application beyond the ITRS 45-nm node. Metal gate materials also eliminate problems associated with the gate Fig. 4. Because metal gate work function engineering is difficult, V adjustment in thin-body devices may need to be accomplished through channel doping or the asymmetric DG structure. Both solutions degrade circuit performance, but could still provide slight improvement over bulk. Threshold voltage adjustment in all cases was adjusted to meet roadmap specifications [2]. depletion effect, which increases the effective dielectric thickness, and dopant penetration through the dielectric, which can degrade oxide reliability and shift the device threshold voltage. Over the last few years, research in metal gate CMOS technology has led to the identification of several candidate metals for this application. Several high melting point refractory metals, e.g., W, Ti, Ta, Mo, Nb, Re, Ru, and their binary or ternary metallic derivatives, e.g., WN, TiN, TaN, MoN, and TaSiN, have been investigated [19] [24]. In the most straightforward case, two separate metals with appropriate work functions need to be used on a single Si substrate in order to obtain low and symmetric devices [25]. For minimal process complexity, however, a method for tuning the gate work function over the required range is highly desirable. Such a tunable work function gate CMOS technology is attractive for bulk-si and SOI-CMOS devices alike. From an integration perspective, ion implantation, whether by structural or chemical modification of the gate material, is the simplest method by which to achieve a tunable gate work function technology. There have been several reports on the use of ion implantation to change the work function of thin metal films [19], [26] [28]. Molybdenum (Mo) is an attractive candidate for this application given the strong crystalline anisotropy of its work function [29]. Such anisotropy is generally displayed by most metals and is believed to arise from differences in interatomic spacing and atom plane smoothness with crystal orientation [30]. Mo is particularly attractive given its compatibility with Si CMOS processing, as it can be deposited by physical vapor deposition (PVD) and chemical vapor deposition (CVD), can be etched by conventional reactive ion etching (RIE) chemistry, and is thermodynamically stable on SiO. It has been shown that a high-dose Ar ion implant can selectively amorphize thin Mo films, thus leading to a significant lowering of the work function [26]. Unfortunately, such a purely structural change is seldom permanent, and crystallization upon high-temperature annealing restores the work function to the unimplanted value. Nevertheless, the possibility of locking in amorphous metal states is still a possibility through the simultaneous modification of film chemistry (e.g., implanting another element, e.g., Si, along with Ar) PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003

4 Fig. 5. Variation of Mo work function with thermal annealing. All anneals were 15 min long except for the 900 C anneal (15 s). An alternative approach to changing the Mo work function is through selective changes in the film chemistry. Nitrogen implantation has been shown to be an effective way to nitridize the Mo film and controllably lower its work function [26]. As shown in Fig. 5, the Mo work function is dependent on the N implant dose and energy. Chemical changes like nitridation are permanent and continue to evolve with temperature. The Mo work function after N implantation becomes progressively lower with increasing annealing temperature and tends to stabilize between 800 C and 900 C. The range of work functions obtained makes this approach attractive for FDSOI-CMOS applications. The next two sections will illustrate the application of this approach to both UTB (UTBFET) and FinFET fabrication. It is important to evaluate the effects of potential channeling of the N ions into the gate dielectric and the subsequent impact on dielectric reliability. In this context, the use of thin Mo films and low implant energies is beneficial in ensuring tight implant straggles and relatively high atomic fractions of N in the Mo film. The thin Mo films can then be capped with poly-si so that while the of the device is determined by the metal work function, the bulk of the gate electrode is made of doped Si to be more compatible with subsequent processing steps (e.g., gate etch and self-aligned source/drain dopant implants). Recently, the use of large angled implants has also been shown to lower the ion channeling effect [31]. Yet another way to introduce N into thin Mo films with minimal damage to the underlying dielectric is to use a solid sacrificial source for N, e.g., N rich TiN. It was recently shown that Mo films capped with nitrogen-rich TiN can act as sinks for the excess N upon high temperature annealing [32]. The N diffusing into the Mo film segregates at the dielectric interface and serves to change the gate work function. This is an attractive technique and can also be used with other metals and diffusion sources. Finally, it should be emphasized that the search for advanced gate dielectrics needs to be carried out in tandem with that for alternative gate dielectric materials, since it is quite likely that aggressively scaled CMOS devices will employ high-permittivity gate dielectrics instead of the conventional SiO -based gate dielectrics [5]. It was recently shown that Fig. 6. Cross-sectional transmission electron microscopy (TEM) of a 3-nm UTB MOSFET. interfacial metal work functions are dependent on the permittivity of the gate dielectric [33]. Thus, while the potential benefits of metal gate electrodes can be fairly significant, the task of metal selection and process integration is far from trivial and is likely to need major research and development efforts in the coming years. IV. ULTRATHIN BODY SINGLE-GATE MOSFET In this section, we review recent work in our group on the development of the UTB single-gate MOSFET device structure. Fig. 6 shows a transmission electron micrograph depicting a cross-sectional view of a UTB ( 30 nm, 3 nm) single-gate MOSFET. The detailed fabrication processes, which are fully compatible with conventional bulk CMOS processes, have been previously reported in [34]. Fig. 7 shows measured electrical characteristics for an 80-nm gate length UTB n-channel MOSFET 20 nm and a 30-nm gate length UTB p-channel MOSFET 4nm, each with a 2.1-nm gate oxide. High drive current 750 A m for NMOS and 400 A m for PMOS at a 1.0 V gate overdrive V was achieved while short-channel effects are well suppressed. For UTB MOSFETs, short-channel effects are strongly dependent on the body thickness, and can be evaluated by the ratio of the gate length to the body thickness. Fig. 8 shows the measured subthreshold swing (S) and drain-induced barrier lowering (DIBL) across a large sample of devices with gate lengths ranging from 30 to 190 nm and body thicknesses from 4 to 8 nm. Short-channel effects are sufficiently suppressed when the ratio between the two device dimensions is larger than 4. This criterion holds for the measured experimental devices, which have a relatively thick gate oxide (2.1 nm) and low channel doping; the value may be further reduced by scaling the gate-oxide thickness or an increase in the channel doping concentration. As discussed in the previous section, metal gate work function engineering is necessary to control the threshold voltage of UTB MOSFETs. Fig. 9 shows the measured subthreshold characteristics for 300-nm gate length UTB PMOS- FETs 15 nm using pure and nitrogen-implanted Mo gate [27]. The measured Mo-gated PMOS threshold voltage CHANG et al.: EXTREMELY SCALED SILICON NANO-CMOS DEVICES 1863

5 Fig. 7. Measured electrical characteristics for UTB n-channel MOSFET (L = 80 nm, T = 20 nm) and p-channel MOSFET (L = 30 nm, T = 4 nm) with 2.1-nm-thick gate oxide. Fig. 8. Measured subthreshold swing (S) and DIBL (30 nm <L < 190 nm, and 4 nm <T < 8 nm). The short-channel effects can be evaluated by L =T. All devices have a nominal gate-oxide thickness of 2.1 nm. limit transistor drive currents [35] [37]. By using selective deposition, a raised source/drain structure can be created to reduce the parasitic resistance. One drawback of this structure, however, is that it inevitably results in increased overlap capacitance. Thus, spacer widths between the gates and raised source/drain should be optimized [38]. Several methods have been demonstrated, including selective silicon epitaxial growth [36], selective silicon germanium (SiGe) epitaxial growth [39], and selective germanium (Ge) deposition [40]. Among these approaches, germanium carries additional benefits in higher dopant solid solubility, which can further reduce parasitic resistance, and lower thermal budget for dopant activation, which is promising for highdielectric integration. While traditional silicides cannot be formed when selective Ge is used, promising results on the formation of metal germanides have been obtained [41], [42], which could further reduce the series resistance. High-performance UTB device technologies have also been reported by other research groups [37], [43], [44] (Table 1). In [37], gate lengths down to 6 nm were achieved by the introduction of an ultrathin gate dielectric and strong halo implant, which can further improve the control of short-channel effects. Fig. 9. Measured subthreshold I 0 V characteristics for UTB p-channel MOSFETs using pure and nitrogen-implanted Mo gate. The V of UTB MOSFETs can be effectively adjusted via gate work function engineering. is 0.2 V, and shifts by approximately 65 mv for every 10 cm increment in the N implant dose. In the UTB device structure, the body thickness should be as thin as possible for ultimate scalability; however, the series resistance of the source and drain regions could V. DOUBLE-GATE FINFET The DG device is electrostatically more robust than a single-gate UTB MOSFET because two gates are used to control the channel from both sides, thus allowing for additional gate length scaling by at least a factor of two. The addition of a second gate electrode not only halves the effect body thickness of the device, but also eliminates penetration of the drain electric field through the buried oxide, which improves gate control of the channel. In the past, numerous methods have been proposed and demonstrated to fabricate DG devices [45] [49]; however, many suffer from process complexity. A more practical DG structure, the FinFET, was, thus, proposed [50], [51]. In this device, the gate straddles a thin, fin-shaped body, which forms two self-aligned channels along the sidewalls of the fin. This original FinFET structure, however, still required a 1864 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003

6 Table 1 Performance Comparison of Published UTB MOSFETs Fig. 10. Schematic diagram, SEM, and TEM photographs of FinFET. (a) Schematic diagram after gate patterning. (b) Top view of SEM photograph showing 10-nm fin width and 20-nm gate length after gate patterning. (c) Cross-sectional TEM photograph of 10-nm fin (x-x direction). (d) Cross-sectional TEM photograph (z-z direction) showing selective Ge raised source/drain. complicated fabrication process and resulted in a large overlap capacitance between the gate and source and drain regions. A simpler, more manufacturable process similar to conventional SOI CMOS processes was then developed to create a quasi-planar FinFET structure (Fig. 10) with significantly less gate-to-source/drain overlap capacitance [12], [52] [55]. The FinFET uses a single-gate material deposited over a silicon fin to form perfectly aligned gates along the fin sidewalls. The fin width is the most important process variable because it determines the body thickness, which governs short-channel effects. The off-state leakage current density increases dramatically as the fin width increased because gate control of the channel is worsened [11]. Channel mobility [56] and threshold voltage [40], [57] can also be sensitive to this dimension. It is, thus, important to achieve small and controllable dimensions for the fin width. This can be accomplished using optical or electron beam lithography, but both inevitably lead to critical dimension (CD) variation and line edge roughness. A key issue for the FinFET is that adequate suppression of short-channel effects requires that the fin width be approximately half of the gate length [11], [50] such that a sublithographic patterning technology is needed for fin formation. This is a clear departure from historic device scaling in the gate length is at the limit of lithographic capabilities. We have explored two sublithographic patterning technologies: photoresist ashing followed by oxide hard mask trimming and spacer lithography (Fig. 11). Photoresist ashing by oxygen plasma can be used to reduce the size of resist patterns defined by lithography. Further size reduction can be achieved by additional hard mask oxide trimming in HF. A combination of ashing and trimming can be used to reduce 500-nm line widths down to below 20 nm [58]. Spacer lithography involves the use of a sacrificial layer and a spacer layer [58] [60]. Sacrificial layers to support the spacers are initially defined by conventional lithography and plasma etching. Then, a second thin layer is deposited CHANG et al.: EXTREMELY SCALED SILICON NANO-CMOS DEVICES 1865

7 Fig. 11. Sublithographic patterning technology: photoresist ashing-hard mask oxide trimming technique and spacer lithography. (a) (d) Process flows of ashing-trimming from 500-nm initial line width to sub-20 nm. (e) Minimum-sized features are defined by thin film deposited by CVD. The spacer lithography doubles pattern density within a given pitch. by CVD and etched back to form spacers. After removal of the sacrificial structures, these spacers are used as an etch mask to transfer the pattern to the substrate by an anisotropic plasma etch. With this process, minimum-sized features as small as 7 nm can be defined [60], [61]. Another feature of spacer lithography is that it can double the pattern density achievable by lithography. This is important in the FinFET structure because in order to obtain higher drive current multiple fins must be placed parallel all straddled by a single-gate line [7]. The achievable fin pitch, thus, determines the amount of layout area required for a device. To further decrease line pitch, this spacer lithography process can be repeated, effectively doubling the line density with each successive iteration (Figs. 11 and 12). As with single-gate UTB MOSFETs, additional FinFET technological challenges include threshold voltage control and parasitic source/drain resistance. We have integrated nitrogen-implanted Mo gate technology [62] and selective germanium deposition for raised source/drain formation [53]. Due to their vertical nature, FinFET devices lie in the (110) plane when oriented parallel and perpendicular to the wafer flat of a standard (100) wafer (Fig. 13). As compared with (100) silicon surfaces, hole mobility is enhanced while electron mobility is degraded in (110) surfaces [63]. These Fig. 12. Multiplication of pattern density by spacer lithography. (a) After patterning sacrificial poly-si layer. (b) After low-temperature oxide (LTO) deposition, LTO spacer etch by CF plasma, and removal of sacrificial poly-si by KOH. (c) After poly-si deposition, poly-si spacer etch by Cl and HBr, and removal of LTO by HF. (d) After LTO deposition, LTO spacer etch by CF plasma, and removal of sacrificial poly-si by KOH.As an etch stop, nitride was deposited before any spacer lithography steps. Eight (= 2 ) lines were generated after repeating the spacer lithography process three times. As shown in (d), the final line width and space was 70 nm and 80 nm, respectively PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003

8 source/drain and metal silicide, the performance of DG MOSFETs can exceed that of traditional bulk-si MOSFETs. VI. SCALING LIMITS Fig. 13. Crystal orientation of NMOS and PMOS FinFETs. PMOS FinFETs are parallel or perpendicular to the flat zone, which situates the channel in the (110) plane. NMOS FinFETs can be rotated by 45 in order to use the (100) plane. trends are consistent with previous reports of FinFET dependence on crystal orientation [12]. These anisotropy effects become even more important in trigate [64] or gate-all-around devices [65]. To simultaneously achieve high NMOS and PMOS drive currents, a (100) sidewall surface for NMOS and (110) sidewall surface for PMOS is desirable. One way to implement these two different crystal orientations is to align silicon fins to be perpendicular or parallel to the flat zone of a (100) wafer for PMOS and at a 45 rotation for NMOS as shown in Fig. 13. Such a scheme, which may incur a small area penalty, will depend on lithographic capabilities. Using electron beam lithography, CMOS FinFETs down to below sub-20 nm in gate length ( 20 nm, 10 nm, 2.1 nm) have been fabricated. For these devices, NMOS drive current is 365 A m and PMOS drive current is 270 A mat V V and V V (Fig. 14). The drive current is normalized with twice the fin height [ in Fig. 10(a)]. The relatively low NMOS current is likely caused by the low electron mobility in the (110) surface and by fin sidewall roughness. Furthermore, a raised source/drain was not used for these devices. The drive current could be increased by 28% with a selectively deposited raised Ge source/drain [53]. FinFET short-channel characteristics are shown in Fig. 15(a) (c). Threshold voltage rolloff is improved as the fin width is decreased [Fig. 15(a)]. Saturation subthreshold swing at V V and DIBL at na m were measured for gate lengths ranging from 20 nm to 150 nm and fin widths from 10 nm to 42 nm. When the ratio of the gate length to the fin width is larger than 1.5, the subthreshold slope and DIBL are below 100 mv/dec and 0.1 V/V, respectively, for NMOS and PMOS devices [Fig. 15(b), (c)]. PMOS devices show somewhat worse short-channel effects because boron diffusivity is higher than that of phosphorus, which results in a smaller after rapid thermal annealing for source/drain activation. An added benefit of DG FinFETs is that they show extremely low gate-induced drain leakage (GIDL) current as shown in Fig. 15(d) [66]. The device performance of published DG FinFETs are summarized in Table 2. With an appropriate raised While MOSFET gate length scaling can be extended with the UTB and DG device structures, an ultimate limit will eventually be reached. For digital circuit applications, this limit will be determined by the ability to maintain proper transistor operation namely that an ultimately scaled device must have the capability to be turned both on and off. With scaling of transistor gate lengths, the primary difficulty lies in control of the off-state leakage current, which, if not properly controlled, can be greatly increased by DIBL in the channel of the device. By quantifying the off-state leakage current for the DG MOSFET structure, an estimate of its scaling limit can be obtained. This structure has been shown to be the most scalable transistor design due to its dual-gate nature, in which the two gate electrodes provide significant control of the channel. Thus, evaluation of the scaling limit of the DG structure can be an estimate of the scaling limit of traditional silicon MOSFETs. At very small channel lengths, carrier scattering can be ignored because ballistic transport will occur in the channel. Under this assumption, the off-state leakage current of a MOSFET will be composed of three major mechanisms: thermionic emission above the channel potential barrier, band-to-band tunneling between the body and drain p-n junction, and quantum mechanical tunneling directly between the source and drain. Thermionic emission is primarily controlled by the channel potential barrier height, which is determined by the degree of short-channel effect control in the device structure. Band-to-band tunneling is governed by the electric field across the body/drain junction, which depends upon the gradient of the source/drain doping profiles as well as the applied drain voltage (in the worst case, the supply voltage). Direct tunneling of carriers from the source to drain may occur at extremely small gate lengths because the channel potential barrier width is very small. In this analysis, tunneling leakage current through the gate dielectric is ignored. Under the assumption that highdielectric materials will become available, we investigate only those drain leakage current mechanisms that cannot be avoided. By calculating these three leakage current components, the off-state leakage can be estimated for the DG MOSFET (Fig. 16). Scaling of the gate length results in increased leakage current because gate control of the channel is reduced, thus allowing for increased DIBL. This reduces the barrier height of the channel potential barrier, thus enhancing the thermionic emission, the dominant leakage component. Scaling of the body thickness, however, eliminates leakage paths that are not well controlled by the gate those that are physically far from the gate electrode. As a result, short-channel effects are minimized at small gate lengths, thus reducing leakage by thermionic emission. The scaling limit of DG MOSFETs is, thus, a strong function of the body thickness. Previous work has suggested CHANG et al.: EXTREMELY SCALED SILICON NANO-CMOS DEVICES 1867

9 Fig. 14. FinFET I-V characteristics. Device dimensions are L = 20 nm, W = 10 nm, and T = 2.1 nm. Fig. 15. FinFET short-channel effects and GIDL. (a) Threshold voltage rolloff versus L. (b) Subthreshold swing versus L =W. (c) DIBL versus L =W. (d) GIDL current. The fabricated FinFET devices show very low GIDL current, which decreases as the fin width is reduced. that the minimum acceptable body thickness for a thin-body MOSFET will be 5 nm [17]. This is because the series resistance in the source and drain regions introduced by such a thin film may become unacceptable even with the incorporation of a raised source/drain technology. In addition, quantum confinement in the thin body may cause an intolerable shift in the device threshold voltage. Furthermore, quantum confinement effects could also impact charge scattering and transport in the on-state [16], which may present a practical limit to device scaling. Thus, a scaling limit for DG MOSFETs can be obtained under the assumption that body thicknesses cannot be scaled below 5 nm. With the additional assumption that equivalent oxide thickness scaling will be limited to 1 nm (due to gate leakage current even with alternative gate dielectric materials), off-state leakage current targets can be met at gate lengths down to 10 nm [11]. This scaling limit is also dependent upon the choice of threshold voltage and the lateral source/drain doping gradient. The value of the scaling limit based upon off-state leakage criteria becomes 1868 PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003

10 Table 2 Performance Comparison of Published FinFETs Fig. 16. DIBL improves as the body thickness is reduced, thus lowering off-state leakage current. At a body thickness of 5 nm, a 10-nm gate length DG MOSFET can meet an off-state leakage current target of 160 na=m. The above data assumes a 1-nm/decade lateral source/drain doping gradient, a long-channel threshold voltage of 0.2 V, and a power supply of 0.6 V. smaller as the body thickness and equivalent oxide thickness are decreased, but is raised by an abrupt source/drain doping profile and a low threshold voltage. VII. THE EFFECTS OF PROCESS VARIATIONS Ultimately, scaling of DG MOSFETs may be limited by process controllability. Because the FinFET is a vertical structure, the fin width is susceptible to line width variation and line edge roughness effects. Furthermore, gate oxidation may be affected by sidewall roughness of the fin. We have, thus, studied the sensitivity of several important device parameters to process variation using device simulation [67]. As a specific example, we choose a nominal device with a 20-nm gate length, 5-nm fin width, and 1.0-nm gate-oxide thickness. The device is assumed to be ideal with a adjustable work function metal gate and small spacer widths (parasitic source/drain series resistance is not significant). The device is designed for low power application according to the ITRS roadmap [2] with off-state current of 1 na m for both NMOS and PMOS. The results (Table 3) show that process variation can be tolerable, as the deviation in electrical parameters is comparable to current values seen in the industry today. The device threshold voltage fluctuates significantly with fin width variation due to changes in the degree of short-channel effect control ( rolloff) and quantum confinement effects. The combined effects result in NMOS V (extracted at low drain bias) variation of 16 mv for every nanometer change in body thickness while V (extracted at high drain bias) variation is slightly higher (33 mv/nm) due to DIBL; PMOS values are similar. Gate length and oxide thickness variation have a significantly weaker effect on the threshold voltage because only the short-channel effect is modulated. Using the drift-diffusion model for carrier transport (nonequilibrium and quantum charge transport effects are, thus, ignored), only a moderate dependence of the drive current on the body thickness was observed. A dramatic change in the off-state current ( 5 per nm around 5 nm) is seen due to the exponential dependence of on the threshold voltage. Using these simulation results, a statistical calculation of the values of each electrical parameter was performed. The contributions of each of the physical parameters are assumed to be independent. Threshold voltage variation is in the range of 40 mv while drive current variation is within 8% 10%. The subthreshold swing is 68 6 mv for NMOS and 70 6 mv for PMOS. The highest leakage is five times larger than that of the nominal device. Based on these results, with reasonable assumptions for process variation ( 1nm, 2 nm, and ), device parameter fluctuations can be kept within reason. VIII. CONCLUSION Advanced MOSFET structures such as the UTB SOI MOSFET and the DG MOSFET show promise for scaling CMOS technology to gate lengths below 10 nm to enable continued improvements in IC cost and performance (e.g., THz operating frequencies) for at least 15 more years. Their CHANG et al.: EXTREMELY SCALED SILICON NANO-CMOS DEVICES 1869

11 Table 3 3 Values of Parameter Variation in FinFET Devices. In Each Case, Two Numbers Are Given: The First Is for NMOS and the Second for PMOS Devices. Nominal Device Parameters aare: L = 20 nm, W = 5 nm, T = 1 nm, N = 10 cm, I =1nA=m, and Source Drain Doping Profiles With a Peak of cm With a 2-nm/dec Gaussian Lateral Decay performance benefit is maximized by using a lightly doped (or undoped) channel to achieve high carrier mobilities. The use of a lightly doped body requires that the gate work function be tunable in the range 4.4 ev to 5.0 ev to provide a means for adjusting the transistor threshold voltage. Molybdenum is an attractive candidate for gateelectrode application because of its compatibility with CMOS processing, and its high work function ( 5 ev) makes it ideal as a gate material for lightly doped p-channel UTB and DG MOSFETs. The work function of molybdenum can be lowered to 4.4 ev in a controllable manner by low-energy nitrogen implantation followed by thermal annealing, which makes it suitable as a gate material for n-channel UTB and DG MOSFETs as well. The capability to achieve multiple values by selectively adjusting the implant dose is important because it enables optimization for high-performance versus low-power applications without the need for any channel doping. UTB SOI MOSFETs with body thicknesses down to 3 nm have been successfully demonstrated. It was found that shortchannel effects (reduction in with decreasing, and with increasing drain bias) are effectively suppressed if the thickness of the body is smaller than the gate length. Excellent drive current can be achieved with a relatively thick (2.1 nm) gate oxide, so long as parasitic source/drain resistance is kept low by selectively thickening the source/drain contact regions. Mo gate work function engineering by nitrogen implantation was shown to be effective for tuning. The FinFET offers the superior scalability of a DG MOSFET structure together with a process flow and layout similar to that of the conventional MOSFET. In order to effectively suppress short-channel effects, the width of the Si fin (i.e., the transistor body thickness) must be less than half the gate length. Sublithographic fins (narrower than any feature that can be defined by conventional lithography) can be formed in an SOI film by using spacers, formed along the sidewalls of a sacrificial patterned layer, as a hard mask. Since the width of the spacers is determined by the thickness of the deposited spacer layer, it can be very narrow and uniform across a wafer. This spacer lithography process can be used to achieve very high fin densities for efficient layout of wide-channel FinFETs. Sub-20-nm FinFETs have been successfully demonstrated, with tuning possible by using Mo gate technology. As with the UTB device, selective thickening of the source/drain contact regions is needed to reduce parasitic resistance. Care must also be taken to remove etch damage and to smoothen the Si fin sidewalls, as well as to orient the fin channel surfaces in order to achieve high drive current. For very short gate lengths, the body can be so thin that quantum confinement effects become significant. At 5nm, is very sensitive to variations in body thickness more so than to variations in. Since can be twice as thick for the DG MOSFET as compared to the UTB MOSFET (for a given ), the DG MOSFET will be more tolerant of process-induced variations for sub-20-nm gate lengths and, hence, will ultimately be more manufacturable. ACKNOWLEDGMENT The authors would like to thank the University of California, Berkeley, Microlab staff for their support in device fabrication. REFERENCES [1] D. J. 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13 [51] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, Sub-50 nm p-channel FinFET, IEEE Trans. Electron Devices, vol. 48, pp , May [52] N. Lindert, L. Chang, Y.-K. Choi, E. H. Anderson, W.-C. Lee, T.-J. King, and C. Hu, Sub-60-nm quasiplanar FinFET s fabricated using a simplified process, IEEE Electron Device Lett., vol. 22, pp , Oct [53] Y.-K. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T.-J. King, J. Bokor, and C. Hu, Sub-20 nm CMOS FinFET technologies, in Int. Electron Devices Meeting Tech. Dig., 2001, pp [54] F.-L. Yang, H.-Y. Chen, F.-C. Chen, Y.-L. Chan, K.-N. Yang, C.-J. Chen, H.-J. Tao, Y.-K. Choi, M.-S. Liang, and C. Hu, 35 nm CMOS FinFETs, in Symp. VLSI Technology Tech. Dig., 2002, pp [55] B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, and C. 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Bokor, Reduction of gateinduced drain leakage (GIDL) current in single-gate ultra-thin body and double-gate FinFET devices, in Proc. Solid State Devices and Materials, 2002, pp [67] ISE TCAD: DESSIS, v7.0 User s Manual, Integrated Systems Engineering, Inc., San Jose, CA, Yang-Kyu Choi received the B.S. and M.S. degrees from Seoul National University, Seoul, Korea, in 1989 and 1991, respectively, and the M.S. and Ph.D. degrees from the University of California, Berkeley, in 1999 and 2001, respectively. From 1991 to 2001, he was a Process Integration Engineer with Hynix Co., Ltd., Kyungki-Do, Korea, where he developed 4-, 16-, 64-, and 256-M DRAM. He is currently a Postdoctoral Researcher at the University of California, Berkeley. He has authored or coauthored over 35 papers and holds six U.S. patents as well as 99 Korea patents. His research interests are novel MOSFET structure such as UTBFETs and FinFETs, nanofabrication, and an investigation of quantum phenomena for nanoscale CMOS. Dr. Choi received the Sakrison Award for the best dissertation in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley, in Daewon Ha was born in Seoul, Korea, on December 4, He received the B.S. and M.S. degrees in electrical engineering from Yonsei University, Seoul, Korea, in 1993 and 1995, respectively. He is currently working toward the Ph.D. degree at the University of California, Berkeley, CA. From 1995 to 2000, he was with Samsung Electronics Company, Ltd., Kyungki-Do, Korea, where he was involved in the development of 512-Mb DRAM and 1-Gb DRAM. His research interests are novel device structures such as ultrathin body SOI and FinFETs for sub-50-nm CMOS technology, device reliability, and memory cell technology. Pushkar Ranade received the B.Eng. degree (with distinction) in metallurgy from the University of Pune, Pune, India in 1996 and the M.S. and Ph.D. degrees in materials science and engineering from the University of California, Berkeley, in 1998 and 2002, respectively. In 2002, he was with IBM Corporation s T.J. Watson Research Center, Yorktown Heights, NY. He is currently with Intel Corporation, Hillsboro, OR. He has authored or coauthored over 30 scientific publications and has three U.S. patents pending. His doctoral research was in the area of sub-100-nm MOS transistor design and fabrication and involved the integration of novel gate stack materials and processes and ultrashallow junction fabrication techniques. Leland Chang (Student Member, IEEE) received the B.S. (highest honors) M.S., and Ph.D. degrees in electrical engineering and computer sciences in 1999, 2001, and 2003, respectively, from the University of California, Berkeley. He is with the Electrical Engineering and Computer Science Department, University of California, Berkeley, CA. His research interests include the fabrication and analysis of thin-body SOI MOSFETs, nonvolatile memory devices, and RF MEMS resonators. Dr. Chang received the National Defense Science and Engineering Graduate (NDSEG) Fellowship from the Department of Defense in 1999 and the IBM Ph.D. Fellowship in Shiying Xiong received the M.S. degree in physics from Tsinghua University, P. R. China, in He is currently working toward the Ph.D. degree in solid-state devices in the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley PROCEEDINGS OF THE IEEE, VOL. 91, NO. 11, NOVEMBER 2003

14 Jeffrey Bokor (Fellow, IEEE) received the B.S. degree in electrical engineering from the Massachusetts Institute of Technology in 1975 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1976 and 1980, respectively. From 1980 to 1993, he was with AT&T Bell Laboratories, Holmdel, NJ, where he did research on novel sources of ultraviolet and soft X-ray coherent radiation, advanced lithography, picosecond optoelectronics, semiconductor physics, surface physics, MOS device physics, and integrated circuit process technology. From 1987 to 1990, he was Head of the Laser Science Research Department at Bell Labs. From 1990 to 1993, he was Head of the ULSI Technology Research Department, Bell Labs, Murray Hill, NJ. Since 1993, he has been Professor of Electrical Engineering and Computer Sciences at the University of California, Berkeley, with a joint appointment at the Lawrence Berkeley National Laboratory, Berkeley, CA. His current research activities include extreme ultraviolet lithography, nanoscale MOSFET device technology, novel techniques for nanofabrication, and new devices for nanoelectronics. Dr. Bokor is a Fellow of the American Physical Society and the Optical Society of America. Tsu-Jae King (Senior Member, IEEE) received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1984, 1986, and 1994, respectively. Her research involved the seminal study of polycrystalline silicon germanium films and their applications in metal oxide semiconductor technologies. From 1992 to 1996, she was a Member of Research Staff with the Xerox Palo Alto Research Center, Palo Alto, CA, researching and developing polycrystalline silicon thin-film transistor technologies for high-performance flat-panel display and imaging applications. She is currently an Associate Professor of Electrical Engineering and Computer Sciences, University of California, Berkeley, and the Director of the University of California, Berkeley, Microfabrication Laboratory. She has authored or coauthored over 150 publications and holds six U.S. patents. Her research activities are presently in sub-50-nm Si devices and technology, and thin-film materials and devices for integrated microsystems and large-area electronics. Chenming Hu (Fellow, IEEE) received the B.S. degree from the National Taiwan University, Taipei, Taiwan, R.O.C., in 1968 and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 1970 and 1973, respectively. He is the CTO of the Taiwan Semiconductor Manufacturing Corporation, Hsinchu, Taiwan, R.O.C., on leave from the University of California, Berkeley. He has authored or coauthored five books and over 700 research papers. He is a Member of the editorial boards of the Journal of Semiconductor Science and Technology and the Journal of Microelectronics Reliability. Dr. Hu received the 2002 IEEE Solid State Circuits Award for leading the development of the industry standard MOSFET model for IC simulation, BSIM. He also received the 1997 IEEE Jack A. Morton Award for contributions to the physics of MOSFET reliability. He is a Member of the U.S. National Academy of Engineering, a Fellow of the Institute of Physics, and a Life Honorary Professor of the Chinese Academy of Science. He has received the University of California, Berkeley s highest honor for teaching, the Distinguished Teaching Award; the Monie A. Ferst Award of Sigma Xi; the W. Y. Pan Foundation Award; and the DARPA Most Significant Technological Accomplishment Award for codeveloping the FinFET transistor structure. CHANG et al.: EXTREMELY SCALED SILICON NANO-CMOS DEVICES 1873