Computer Engineering 290. Digital Design: I. Lecture Notes Summer 2002

Computer Engineering 290 Digital Design: I Lecture Notes Summer 2002 W.D. Little Dept. of Electrical and Computer Engineering University of Victoria 1

Preface These lecture notes complement the material covered in the textbook and the lab book for the course. 2

CENG 290 Lecture Topics Introduction Engineering Process Digital Design Signals and logic variables Polarized mnemonics Basic Digital Components Two-Level Combinational Logic Boolean Algebra Truth tables and Boolean Equations Design Example Karnaugh Maps Sequential Circuit Logic Design RS latch RS latch with enable D latch JK master/slave flip-flop Edge triggered D flip-flops Edge triggered JK flip-flop Flip-Flop circuits Sequential Circuit Analysis Sequential Circuit Design Design Example 1 Design Example 2 Design Example 3 Design Example 4 3-bit counter Mealy state machine Pop Machine Controller Simple Memory Based System Gate Outputs Totem pole outputs Open Collector Outputs Wired Logic Open Collector Bus Drivers Tri-State Outputs 3

Hazards Static Hazards Dynamic Hazards Simulation of Gate Circuits Miscellaneous Circuits and Components Multiplexors Multiplexors for Logic Multiplexors for routing Demultiplexors Decoders 74163 Counter Circuits Transmission Gates and Steering Logic Sequential Circuit Timing Minimum Clock Period Maximum Clock Skew Metastability 4

Introduction Engineering Process specifications design implementation -what is required -how is it -assemble to be done -marketing -engineering -manufacturing -incomplete/ambiguous -technology -test -cost -speed -install -service -reliability -documentation -modularization -algorithms -CAD 5

Digital Design Much of design is concerned with precisely describing how something is to be done. Being precise is very difficult. Use various types of mathematics and languages to precisely express a design. We will use: -Boolean algebra -finite difference equations -polarized mnemonics -circuit and component symbols -timing diagrams and tables -hardware description language (eg. VHDL) Real (physical) signals, components and systems are almost impossible to precisely represent or define so engineers use various simplifications or models that approximately represent or define real signals, components and systems. Such simplifications are called abstractions and we talk about a level of abstraction depending upon how much detail the simplification includes. Consider a real digital signal as an example. -the real signal is very difficult to precisely describe -a timing diagram may model the real signal -stating the signal is High or Low may model the real signal Common to use H,L to model the value (level) of a signal. Digital components and systems are often modelled by variables call logical or Boolean variables that have values of 0 or 1 and by simple operations (eg. AND, OR, INVERT) on the logical variables. 6

May use mathematical language, graphical language, truth table or hardware description language to represent components and systems as shown below. Mathematical language e = /a f = e.b g = c.d h = f+g Graphical language a e f b h c d g Truth table a b c d e f g h 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 1 1 0 1 0 0 1 1 0 1 0 1 0 1 1 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 1 1 7

Hardware Description Language (VHDL) entity and2 is port (a,b : in bit; y : out bit); end and2; architecture basic of and2 is begin and2_behavior : process is begin y<= a and b after 2 ns; wait on a,b; end process and2_behavior; end architecture basic; entity or2 is port (a,b : in bit; y : out bit); end or2; architecture basic of or2 is begin or2_behavior : process is begin y<= a or b after 2 ns; wait on a,b; end process or2_behavior; end architecture basic; entity inv1 is port (a : in bit; y : out bit); end inv1; architecture basic of inv1 is begin inv1_behavior : process is begin y<= not a after 2 ns; wait on a; end process inv1_behavior; end architecture basic; 8

9 architecture struct of system is signal e,f,g : bit; begin inv_1 : entity work.inv(basic) port map (a,e); and_1 : entity work.and(basic) port map (e,b,f); and_2 : entity work.and(basic) port map (c,d,g); or_1 : entity work.or(basic) port map (f,g,h); end architecture struct;

Signals and logic variables Real components and systems have signals. Digital design models signals with logic variables. analog signals digital signals -all signal levels (voltages) of interest -use R,L,C, op-amps etc. to process -processing can be very fast (gigahertz) -subject to noise problems -only interested if signal is above (H) or below (L) a threshold value -threshold about 1.4 volts for TTL, 2.5 volts for CMOS -several or many digital signals used to represent an analog signal or value -digital signals relatively immune to noise logic variables -have values 0 or 1 -logic variables represent assertions -0 means assertion is false -1 means assertion is true - example assertions: the motor is running the switch is up the temperature is too hot bit #7 has value 1 the reset condition is applied -use variable name that mean something ie. m_run as a logic variable name to represent the assertion "the motor is running", b7 as a variable name to represent the assertion "bit#7 has value 1", reset as a variable name to represent "the reset condition is applied" -often use 1 letter logic variable names to simplify equations 10

Polarized Mnenonics (names) When digital signals represent logic variables we may let H represent 1 or H represent 0. (L, of course, will represent the other logic value). If a system always uses H to represent 1 we says the system uses positive logic. If a system always uses H to represent 0 we say the system uses negative logic. If a system sometimes uses H to represent 1 and sometimes uses H to represent 0 we say the system uses mixed logic. When mixed logic is used we use polarized mnemonic signal names such as m_run(h) to mean that the motor is running when the digital signal is H and reset(l) to mean that the reset condition is applied when the signal is L. In concise terminology we say that a signal named x(h) means that the logic variable x is asserted when the signal is high. Examples 1. Positive or negative logic system door_closed enable_starter_switch seat_belt_buckled The logic variable names and signal names are the same. For positive logic, enable_starter_switch = 1 when the output voltage is high. For negative logic, enable_starter_switch = 1 when the output voltage is low. 11

2. Mixed logic system door_closed(l) enable_starter_switch(l) seat_belt_buckled(h) low. Polarized mnemonics are used for the signal names. enable_starter_switch = 1 when the output voltage is 12

Basic Digital Components SPST switch +5V 1K switch_open(h) SPST switch used to generate digital signal SPDT pushbutton +5V 1K 1K pb_up(l) pb_down(l) SPDT pushbutton Analog to Digital Converter A/D V in 8-bit A/D bit 0 (L) bit 1 (L) bit 7 (L) 13

Light Emitting Diode Symbol I + V - IV Characteristic I.6 volt V 14

NPN Transistor Symbol I collector I base + V CE - Characteristic For Ibase sufficiently positive, VCE is approximately.2 volt and collector current can flow. PNP Transistor Symbol I emitter I base + V EC - Characteristic For Ibase sufficiently negative, VEC is approximately.3 volt and emitter current can flow. 15

NMOS Transistor Symbol I drain + V GS - + V DS - Characteristic For VGS sufficiently positive, VDS is approximately 0 and drain current can flow. PMOS Transistor Symbol I source + + V GS - V SD - Characteristic For VGS sufficiently negative, VSD is approximately 0 and source current can flow. 16

TTL gates There are several families of transistor-tranistor logic gates. The 7400 series, the 74LS (low power Schottky) series and the 74 FAST series are wiely used. All the components in a given family are directly interconnectable. Interconnection of components from different families is sometimes possible but requires detailed knowledge of the specifications to know if components are compatible and how many components can be driven from another component. TTL components require a 5 volt power supply. Several common TTL components are illustrated below. 04 13 12 11 10 9 8 5 6 3 4 1 2 1 2 4 5 9 10 12 13 00 3 6 8 11 2 3 4 1 12 11 10 13 D 74 CLK PR/ / CLR/ D CLK PR/ CLR/ 193 5 4 DN 5 UP 6 9 D 10 C 1 9 15 A B / 8 11 LOAD 14 CLR BO CO D C B A 7 6 2 3 13 12 TTL inverter, NAND, flip-flop and counter chips 17

TTL voltage specifications If Vin >= VIH = 2 or Vin <= VIL =.8 then Vout >= VOH = 2.4 or Vout <= VOL =.4 When a TTL output drives a TTL input the high level noise margin is 2.4-2 =.4 volt. When a TTL output drives a TTL input the low level noise margin is.8 -.4 =.4 volt. Hence TTL can withstand a noise spike of at least.4 volts between an output and an input before a logic level will be affected. TTL current specifications I I I O 74LS component For a high IOH <= -400 ua IIH <= 20 ua Therefore high fanout = 400/20 = 20 For a low IOL >= 8 ma IIL >= -.4 ma Therefore low fanout = 8/.4 = 20 18

Timing specifications Input Output t plh t phl Propagation delays measured from 50% levels Rise and fall times measured between 10% and 90% levels Propagation delays approximately: 10 nsec. for LS 8 nsec. for TTL 5 nsec. for F 19

TTL inverter Input/Ouput Characteristics V out threshold V in Inverters in a loop Odd number oscillate with half period = tp1 + tp2 + tp3 tp1 tp2 tp3 Even number has two stable states. 20

Two-Level Combinational Logic Combinational logic Output = Function(Inputs) We will study sequential logic where State = Function(Inputs, State) and Outputs = Function(State, Inputs) later. Two-level Input signals or their complements pass through, at most, two gates to effect the output. Example /A B C X D X = /A. B + C. D Material Covered Boolean Algebra Gates Truth Tables Karnaugh Maps Canonic (standard) Forms Circuits 21

Boolean Algebra A Boolean algebra consists of a set of elements B, together with two binary operations + and. and a unary operation / such that the following axioms hold: 1. The set B contains at least two elements a,b such that a/=b. 2. Closure: For every a,b in B, a. a + b is in B b. a. b is in B 3. Commutative laws: For every a,b in B a. a + b = b + a b. a. b = b. a 4. Associative laws: For every a,b,c in B a. (a + b) + c = a + (b + c) = a + b + c b. (a. b). c = a. (b. c) = a. b. c 5. Identities: a. There exists an element with respect to +, designated by 0, such that a + 0 = a for every a in B. b. There exists an element with respect to., designated by 1, such that a. 1 = a for every a in B. 6. Distributive laws: For every a,b,c in B, a. a + (b. c) = (a + b). (a + c) b. a. (b + c) = (a.b) + (a. c) 7. Complement: For each a in B, there exists an element /a in B (the complement of a) such that a. a + /a = 1 b. a. /a = 0 22

When B is the set {0,1}, + is the OR operation,. is the AND operation and / is the NOT operation defined as follows then the Boolean algebra is called Switching algebra. a b a + b a b a.b a /a 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 1 1 1 1 1 These operations are represented symbolically as follows a a + b a a.b a /a b b OR + AND. NOT / Duality Note that the axioms occur in pairs. This property of Boolean Algebra leads to the Duality Theorem stated as follows; {f(x1,x2,...,xn,0,1,+,.)} D = f(x1,x2,...,xn,1,0,.,+) ie, the dual of an expression is obtained by interchanging 0s and 1s and interchanging +s and.s. If f( ) = g( ) then {f( )} D = {g( )} D DeMorgan's Theorem (for finding the complement of an expression) /{f(x1,x2,...,xn,0,1,+,.)} = f(/x1,/x2,...,/xn,1,0,.,+) 23

Examples The above theorems and axioms are used to simplify Boolean expressions and to put expressions in alternate equivalent forms. Ex1. Find the complement of a + b + c By DeMorgan /(a + b + c) = /a. /b. /c Ex2. Show that a. b + a./b = a a. (b + /b)=?a distributive axiom a. 1 =?a complement axiom a = a identity axiom Ex3. What is the dual of the following relationship? (X + /Y). Y = X. Y {(X + /Y). Y} D = (X. Y) D X. /Y + Y = X + Y Truth tables and Boolean Equations A truth table is a table that specifies a Boolean function. That is, it gives the value of an output Boolean varaible for all possible input variable combinations. Example A B C X 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 24

Here, X is a function of the three variables A,B,C. There are 2 3 input combinations that are enumerated. For n input variables there are 2 n input combinations and 22 n possible functions of the n input variables. The above table is only 1 of 256 possible functions of 3 variables. The above function was selected at random as a example. It is easy to write Boolean equations that are equivalent to a truth table. For the above truth table X=1 when (A=0).(B=0).(C=0) + (A=0).(B=1).(C=0) + (A=0).(B=1).(C=1) + (A=1).(B=1).(C=1) ie X = /A./B./C + /A. B. /C + /A.B.C + A.B.C 1. Try substituting input values to convince yourself of the validity of this equation. It is also possible to get an equation for X by considering the 0's of the function. X=0 when (A=0).(B=0).(C=1) + (A=1).(B=0).(C=0) + (A=1).(B=0).(C=1) + (A=1).(B=1).(C=0) ie X = (A+B+/C). (/A+B +C). (/A+B+/C). (/A+/B+C) 2. It is very important that you try substituting values in this equation to make sure it agrees with the truth table. 25

Equation 1 is said to be in sum of product form SOP. A more precise term would be OR of AND form. Equation 2 is said to be in product of sum form POS. A more precise term would be AND of OR form. Equation 1 has 4 product terms while equation 2 has 4 sum terms. A product term that contains each variable or it's complement is called a minterm. A sum term that contains each variable or it's complement is called a maxterm. A variable or it's complements is called a literal. A SOP equation in which all product terms are minterms is called a minterm canonic form. A POS equation in which all sum terms are maxterms is called a maxterm canonic form. It is very easy to convert between truth tables and canonic forms. It is also easy to augment SOP and POS equations to form canonic forms. eg. X = A.B + C SOP form X = AB(C + /C) + (A + /A)(B + /B)C X = ABC + AB/C + ABC + A/BC +/ABC + /A/BC X = ABC + AB/C + A/BC + /A/BC Minterm Canonic Form The minterms are named mi and the maxterms are named Mi as illustrated below for three variables, a,b,c. m0 = /a/b/c m1 = /a/bc m2 = /ab/c m3 = /abc m4 = a/b/c m5 = a/bc m6 = ab/c m7 = abc M0 = a+b+c M1 = a+b+/c M2 = a+/b+c M3 = a+/b+/c M4 = /a+b+c M5 = /a+b+/c M6 = /a+/b+c M7 = /a+/b+/c The minterms and maxterms are obtained from the binary number corresponding to the subscript. For example, for 5 variables, x,y,d,s,k, m13 = /xyd/sk and M22 = /xy/d/sk. Equation 1 above can be expressed as X = m0 + m2 + m3 + m7 = m0,m2,m3,m7 26

Equation 2 above can be expressed as X = M1.M4.M5.M6 = π M1,M4,M5,M6 Note that the subscripts not present in the m list are present in the M list. Hence it is easy with this notation to convert between minterm and maxterm canonic forms. Design Example Design of a circuit module (full adder) for a binary adder. A common binary adder known as a ripple adder is shown below. an bn an-1 bn-1 a2 b2 a1 b1 a0 b0 cn+1 FAn cn FAn-1 cn-1 FA2 c2 FA1 c1 FA0 c0 sn sn-1 s2 s1 s0 An n bit ripple adder uses n full adder modules to add a binary number A = {an,an-1,...a2,a1,a0} to binary number B = {bn,bn-1,...b2,b1,b0}. Si are the sum bits and ci are the carry bits. For the ith module ai bi ci si ci+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 27

Therefore we can write si = m1+m2+m4+m7 = M0.M3.M5.M6 ci+1 = m3+m5+m6+m7 = M0.M1.M2.M4 Using Boolean Algebra or other means si and ci+1 can be expressed as si = ai bi ci ci+1 = ai.bi + (ai bi).ci where is the exclusive OR operation A full adder circuit for si and ci+1 is given below. The circuit given uses a small number of simple components. si is generated after 2 gate delays and ci+1 is generated after 3 gate delays. The canonic equations could also be directly implemented to give 2 level circuits for both si and ci+1 but more components and more complex components would be required. ai si bi ci ci+1 Full Adder Module. 28

Karnaugh Maps K-maps are used to determine 2 level SOP and POS equations, and subsequently circuits, that have a minimum number of literals. Such circuits are often the cheapest to implement. In general, 2 level circuits are also the fastest circuits possible. K-maps are classic paper and pencil maps for determining optimum circuits for up to 6 variable systems. Computer suitable tabular methods like the uine McCluskey method to be studied later are suitable for more variables. K-maps contain the same information as truth tables but the input combinations are arranged so that adjacent cells in a K-map are a unit distance apart. With this arrangement a group of 2 m cells is equivalent to a product (or sum) term with n-m literals when dealing with an n variable system. The smallest number of largest possible groups that cover all the 1s (or 0s) in a K-map gives rise to a minimum equation.for the output variable. 29

Two equal length binary sequences are a Hamming distance k apart if they differ in k corresponding positions. For example, the sequence 1011001010 differs from the sequence 1110101001 in 4 corresponding positions therfore the distance between the two sequences is 4. Examples of 2, 3 and 4 variable K-maps are given below. a 0 1 b 0 1 0 1 1 1 x 2 Variable K-map ab 00 01 11 10 c 0 1 1 0 0 1 0 1 1 0 x 3 Variable K-map ab 00 01 11 10 00 1 1 1 1 cd 01 0 0 0 0 11 1 1 0 0 10 1 1 0 1 x 4 Variable K-map 30

Consider the 3 variable map. The two adjacent 1s in the 2 adjacent cells corresponding to abc = 000 and 010 give rise to the subexpression /a./b./c + /a.b./c = /a./c. The b variable drops out because the 2 cells are a unit distance apart. Hence if we group cells of 1s as shown below we can write x by inspection as x = /a./c + b.c ab 00 01 11 10 c 0 1 1 0 0 1 0 1 1 0 x For the 4 variable map we cover the 1s with the smallest number of largest possible groups as shown below. ab 00 01 11 10 00 1 1 1 1 cd 01 0 0 0 0 11 1 1 0 0 10 1 1 0 1 x There are 3 groups. The 4 1s in the corners form a group since the corner cells are adjacent. By inspection we get x = /c./d + /a.c + /b./d This SOP equation contains a minimum number of literals, ie 6. 31

Some Definitions Implicant: A product term corresponding to a group of adjacent K-map cells. Prime Implicant : A product term corresponding to a largest possible grouping of adjacent K-map cells. Essential Prime Implicant: If a cell is covered by only 1 prime implicant, that prime implicant is an essential prime implicant. K-map Minimization Procedure Identify all prime implicants. Select a minimum number of prime implicants that cover the 1s. 32

Examples ab 00 01 11 10 0 1 1 c 1 1 1 1 x prime implicant prime implicant Example with 11 implicants and 2 prime implicants. 33

ab 00 01 11 10 0 1 1 1 1 1 x essential prime implicants Example with 7 implicants, 3 prime implicants and 2 essential prime implicants Don't Cares Sometimes input combinations never occur or it doesn't matter what the output is for a given input combination. Such conditions are called don't cares. They can be used to minimizes logic expressions. A K-map with don't cares is shown below. The X s are don't cares. For the purpose of finding a prime implicant cover they can be treated as either a 0 or a 1. 34

ab 00 01 11 10 00 1 1 X X cd 01 0 1 1 0 11 0 0 X 0 10 1 0 0 X f K-map for POS expression f = b./c + /b./d f may also be written in canonical form as f = Σ m0,m2,m4,m5,m13 + Σ d8,d10,d12,d15 ab 00 01 11 10 00 1 1 X X cd 01 0 1 1 0 11 0 0 X 0 10 1 0 0 X f f = (/b + /c). (b + /d) To get a POS expression you may also group the 1s on a K-map of /f to get a SOP expression for /f then use DeMorgan to get the POS expression for f. See example below. 35

ab 00 01 11 10 00 0 0 X X cd 01 1 0 0 1 11 1 1 X 1 10 0 1 1 X /f Therefore /f = b.c + /b.d f = (/b + /c). (b + /d) 5 Variable K-map Use 3D to visualize 2 2D K-maps and group in 3D. e = 1 ab 00 01 11 10 00 0 0 0 0 cd 01 0 1 1 0 11 0 1 1 0 10 0 0 0 1 e = 0 ab 00 01 11 10 00 1 0 0 0 cd 01 1 1 1 0 11 0 1 1 0 10 0 0 0 1 f f = b.d + a./b.c./d + /a./b./c./e 36

6 Variable K-Map Same approach as 5 variable K-map but use 4 planes as illustrated below ef = 11 00 cd 01 11 10 ef = 10 ab 00 01 11 10 00 cd 01 11 10 ab 00 01 11 10 ef = 01 00 cd 01 11 10 ab 00 01 11 10 ef = 00 00 cd 01 11 10 ab 00 01 11 10 K-Map Method Summary f. K-map method is an easy to use graphical paper and pencil method to obtain two level SOP and POS expressions that contain a 37

minimum number of literals. Method is suitable for up to 6 variables. Sequential Circuit Logic Design Digiatal circuits can be divided into two classes. Combinational circuits and sequential circuits. The steady state outputs of combinational circuits, as we have seen, are functions only of the inputs, ie outputs = Function(inputs). We have looked at some aspects of simple conbinational circuits and we will be returning to look at many more aspects. Sequential circuits are digital circuits whose outputs depend upon a sequence of inputs. The sequence of inputs that have been applied is remembered by the state variables of the circuit. There are two classes of sequential circuits, Moore and Mealy. For Moore sequential circuits For Mealy sequential circuits state = Function(state, inputs) outputs = function(state) state = Function(state, inputs) outputs = function(state,inputs) Note that the current state (ie state variables) is fed back to determine the next state. All sequential circuits have feedback. Sequential circuits are the basis of digital circuits that exhibit memory including flip-flops, registers, counters, and controllers. Sequential circuits are a very important class of circuit. Sequential circuits are often considerably more complex than combinational circuits. 38

The following is a block diagram of a generic sequential circuit. input variables next state logic for Mealy only next state variables memory output logic output variables state variables A memory element is required for each state variable. The memory may be simply the capacitance or delay of a gate as it is in asynchronous sequential circuits or it may be a set of flip flop memory elements. as it is in synchronous (clocked) sequential circuits. We will start our study of sequential circuits by studying the RS latch flip-flop and then study other flip-flops, counters, clocking methods, design methods, and controllers. RS Latch The RS latch is a basic asynchronous sequential circuit that is the heart of all flip-flops. Flip-flops, in turn, are the heart of all registers, counters and controllers. The following is a basic latch with no inputs. If the output of either inverter is forced high or low it will remain high or low after the forcing signal is removed. The circuit 39

remembers the state of the last forcing signal. This is the basis of digital memory. If the inverters are replaced by NOR gates or NAND gates so that forcing signals can be more easily applied we get two versions of the RS latch as shown below. S R NOR form of RS latch /R /S NAND form of RS latch R is a signal to reset to 0 and S is a signal to set to 1. For the NOR circuit For the NAND circuit = /(R + /( + S)) = /(R + /./S ) = /R.( + S) = /(/S. /(./R)) = /(/S.(/ + R)) = S +./R These are called the characteristic equations for the circuits. They give the next state as a function of the present state and the inputs. In actual fact, with perfect (mathematical) operations the RS does not work since the on the left side of the equations cannot be different from the on the right hand side. There must be some delay in the loop for the latch to be able to change state. One possible model to handle this situation is shown below for the NAND implementation. 40

/R /S + delay To distinguish next state and present state the next state is usually labeled + and the present state is labeled as shown. The characteristic equation becomes + = S +./R A next state table can be easily constructed from the characteristic equation: S R + 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1 A timing diagram to illustrate the behavior of the NAND circuit is given below. S R + Note that is a delayed version of + and that if S and R are 1 simultaneously that S wins out. 41

Some models of the RS latch do not behave deterministically when S and R are simultaneously changed from 1 to 0. To avoid nondeterministic behavior R and S are often restricted to not being 1 simultaneously. State diagrams are often used to specify sequential circuits. Three forms of a state diagram for the RS latch are shown below. 00,10 /R./S + R./S RS =0 =0 =0 10 01 R./S /R.S R./S /R.S =1 =1 =1 RS not allowed 00,01 /R./S + /R.S These state diagrams give the next state for all valid inputs. The input combination RS = 11 is excluded for the reason given above. NOR and NAND RS latch circuits in cross-coupled form and the RS latch symbol are shown below. S / /S R /R / RS latch Circuits S R RS latch Symbol 42

RS Latch with enable S C S R S C R R Circuit Symbol Timing Diagram transparent transparent C T setup T hold S T prop Device is often called a level sensitive transparent latch 43

D Latch D C S C R D C Circiut Symbol JK Master/Slave Flip_Flop Next State K-map JK 00 01 11 10 0 0 0 1 1 1 1 0 0 1 + Characteristic Equation + = J./ + /K. Excitation K-map for RS implementation JK 00 01 11 10 0 X0 X0 01 01 1 0X 10 10 0X RS Excitation Equations R = K. S = J./ 44

Circuit Symbol J K C S C R P /P /C S C R / J K C Comments The left latch can set or reset while C = 1 and hence the new state may not be determined by values of J,K at time of clock negative edge. This is the 1s or 0s catching problem. Example of 1s catching: If = 0 and J = 1 momentarily while C = 1 and J,K = 0 on clock negative edge, the new will be 1 rather than 0. Example of 0s catching: If = 1 and K = 1 momentarily while C = 1 and J,K = 0 on clock negative edge, the new will be 0 rather than 1. 45

Edge triggered D flip-flops Characteristic equation + = D Symbols D C + edge triggered D flip-flop D C -edge triggered D flip-flop 46

Edge triggered JK flip-flop D flip flop excitation equation D = J./ + /K. Circuit J /K D C Symbol J K C 47

Concise Flip-Flop Summary =1 T T + = /.T +./T =0 T flip-flop =1 J K + = /.J +./k =0 JK flip-flop =1 D /D + = /.D +.D = D =0 D flip-flop 48

Flip Flop Circuits Switch Debouncer +5V S R Shift Register datain D D D D dataout C C C C clock 49

4-bit Asynchronous Counter +5V +5V +5V +5V count J K C b0 b1 b2 b3 J J J K K K C C C count b0 b1 b2 b3 50

b3,b2,b1,b0 0000 0001 0010 0011 0111 0110 0101 0100 1000 1001 1010 1011 1111 1110 1101 1100 State Diagram Sequential Circuit Analysis Given a sequential circuit, determine the corresponding state diagram. Analysis Steps write excitation equations write output equations generate excitation K-maps and output K-maps generate next state K-maps and output K-maps generate state diagram 51

Example #1 X S J C K R A /A S J C K R B /B Excitation Equations Ja = X Jb = X Ka = X./B Kb = X /A Outputs are state variables A and B Generate excitation K-maps and output K-maps AB 00 01 11 10 X 0 00 00 00 00 1 11 10 10 11 JaKa AB 00 01 11 10 X 0 01 01 00 00 1 10 10 11 11 JbKb 52

Generate next state K-maps State Diagram AB 00 01 11 10 X 0 00 00 11 10 1 11 11 10 01 A+B+ 00 AB X /x 11 X 01 X 10 X 53

Example#2 X S D A C R Z S J C K R B Excitation Equations Da = (A + X).B = A.B + X.B Jb = X /A Kb = /X Output equation Z = X.A + /X.B Generate excitation K-maps AB 00 01 11 10 X 0 0 0 1 0 1 0 1 1 0 Da AB 00 01 11 10 X 0 11 11 01 01 1 00 00 10 10 JbKb 54

Generate output K-map AB 00 01 11 10 X 0 0 1 1 0 1 0 0 1 1 Z Generate next state K-maps State Diagram AB 00 01 11 10 X 0 01 00 10 00 1 00 11 11 01 A+B+ AB X/0 00 /X/0 /X/0 11 X/1 /X/1 X/0 /X/1 10 X/1 01 Comments This example was a Mealy sequential circuit. Note the way the state diagram was drawn for the Mealy circuit. 55

Sequential Circuit Design Design is the reverse of analysis. The steps are: Understand problem. Generate state diagram (or other formal representation) Assign state variables to states state excitation Determine next state equations possibly using next K-maps. Determine output equations possibly using output K-maps. Specify flip-flops to be used for state variable memory. Determine excitation equations possibly using K-maps. Generate circuit or circuit description. Design Example 1 3-bit synchronous binary down counter. Assume that asynchronous sets are be used to set the counter to an initial state of state S7. Use the state variables as the outputs. State Diagram 56

reset S7 S0 S6 S1 S5 S2 S3 S4 State Assignment 000 111 reset state variables ABC 110 001 101 010 011 100 Next state K-map AB 00 01 11 10 C 0 111 001 101 011 1 000 010 110 100 A+B+C+ therefore Choose JK flip flops with + =./K + /.J and 57

58 + J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0

Excitation K-maps AB 00 01 11 10 C 0 1X 0X X0 X1 1 0X 0X X0 X0 JA,KA JA = /B./C KA = /B./C AB 00 01 11 10 C 0 1X X1 X1 1X 1 0X X0 X0 0X JB,KB JB = /C KB = /C AB 00 01 11 10 C 0 1X 1X 1X 1X 1 X1 X1 X1 X1 JC,KC JC = 1 KC = 1 59

Circuit +5V S J C K R A S J C K R B S J C K R C Comments It is possible to write next state equations directly from the assigned state diagam by accounting for all cases where the next state variable is 1. This gives the following equations: but A+ = /A./B./C + A.B.C + A.B./C + A./B.C /A./B./C + A.(B + C) /A.(/B./C) + A.(/(/B./C)) A+ = /A.JA + A./KA for the A JK flip-flop. therefore JA = /B./C and KA = /B./C Similarily, but B+ = /A./B./C + A.B.C + A./B./C + /A.B.C = /B.(/A./C + A./C) + B.(A.C + /A.C) = /B./C + B. C B+ = /B.JB + B./KB for the B JK flip-flop. therefore JB = /C and KB = /C 60

Also but C+ = /A./B./C + A.B./C + A./B./C + /A.B./C = /C.(/A./B + A.B + A./B + /A.B) = /C C+ = /C.JC + C./KC for the C JK flip-flop. therefore JC = 1 and KB = 1 These equations, obtained directly from the assigned state diagram are the same as those obtained from the excitation maps. Design Example 2 Mealy State Machine Consider the Mealy state diagram given below. /A/B X X /Z /AB X A/B [Z] X AB X/Z X 61

The next state equations and the output equation can be written by inspection of the state diagram. A+ = /A.B.X + A./B.X + A./B./X B+ = /A./B./X + A.B.X + A./B./X Z = /A.B./X + A.B.X + A./B If D flip flops are to be used to store the state variables then Da = A+ and Db = B+. If JK flip flops are to be used to store the state variables then equate the characteristic equation A+ = A./Ka + /A.Ja with A+ above to get Ja and Ka and similarily for Jb and Kb. Design Example 3 Pop Machine Controller This example is a simple pop machine controller based on material in Chapter 8 of the text. The pop machine accepts nickels and dimes and dispenses pop when atleast 15 cents has been deposited. A reset button must be pushed to reset the machine before money is deposited and the machine gives no change. The machine is organized as shown below. N coin sensor D FSM controller open pop dispenser clock Note very carefully that the inputs N and D (Nickel and Dime) are asserted for 1 clock cycle and are synchronized with the clock. If the presence of a nickel, for example, depresses a switch, the following circuit could be used to generate the N input signal. 62

+5V X S D C R S D C R N clock The presence of a nickel lifts the pushbutton to make contact with the top contacts of the switch. X is a debounced signal that feeds a 2 bit shift register. N will be asserted for 1 clock cycle following release of the pushbutton. The state diagram of a controller that meets the problem statement is shown below. reset zero N five D N D ten N,D fifteen [open] 63

State variables A and B may be used to encode the states as shown below. reset /A/B N /AB D N D A/B N,D AB [open] Note that this is a Moore machine and the output open is given by open = A.B 64

The next state table is AB 00 01 11 10 00 00 01 11 10 ND 01 10 11 11 11 11 X X X X 10 01 10 11 11 A+B+ The excitation tables for a JK implementation are as follows. AB 00 01 11 10 00 0X 0X X0 X0 ND 01 1X 1X X0 X0 11 X X X X 10 0X 1X X0 X0 JaKa Therefore Ja = D + N.B Ka = 0 Also AB 00 01 11 10 00 0X X0 X0 0X ND 01 0X X0 X0 1X 11 X X X X 10 1X X1 X0 1X JbKb Therefore Jb = N + D.A Kb = N./A 65

The controller schematic is therefore as follows. N D S J C K R open D N N S J C K R B Note also that the next state equations can be easily written directly from the state diagram. A+ = /A.B.N + /A./B.D + A./B.(/(N+D)) + A./B.(N+D) + /A.B.D + A.B B+ = /A./BN + /A.B.(/(N+D)) + /A.B.D + A./B.(N+D) + A.B The excitation equations for the chosen flip flops are obtained from these equations using the characteristic equations of the flip flops. 66

Design Example 4 Simple Memory Based System This example is based upon the latter part of Chapter 7 of the text. The example is also the subject of the last laboratory for the course. The system consists of a Data Path subsystem and a Controller subsystem as shown below. The system enables a user to store data in a memory and read and display the data from the memory. To store data in the memory, the user enters data on the hex keypad, sets the read/write switch to write and activates the pushbutton to store the data at the address supplied by the counter. After pushing the pushbutton, the counter is incremented so that the next time data is stored it is at the next sequential address. To read data from the current address supplied by the counter, the user sets the read/write switch to read and pushes the pushbutton. This will read data from memory and store it in the 74379 D register which in turn drives the hex display. The counter is then incremented in anticipation of the next push of the pushbutton. 67

68 The Data Path Subsystem

69 The Controller Subsystem

The Data Path To understand this system, first consider the Data Path circuit and its components. 74163 Counter The 74163 counter is a 4 bit positive edge triggered synchronous counter with a few handy features. When LOAD and CLR are not asserted, the counter increments on a positive clock edge if P=T=1. When LOAD is asserted the counter is loaded with the data A,B,C,D on the positive edge of the clock. When CLR is asserted the counter is cleared on the positive edge of the clock. LOAD and CLR should not be asserted simultaneously and LOAD and CLR override the P=T increment enable inputs. The ripple carry out, RCO, is asserted when the count equals 1111. In the Data Path circuit it can be seen that the 74163 load feature is not used. Control signals /reset and Inc_Adr are used to clear the counter and enable incrementing the counter. 74379 4 bit Register This register is loaded with data on the positive clock edge iff enable, EN, is asserted. In the Data Path circuit the control signal /Latch_Data is used to drive EN. 74244 Octal Tri-State Buffer The buffers in this chip are enabled with the GA and GB inputs. In the Data Path circuit, the control signal, /Enab_Buf, is used to enable the buffers in order to place the contents of the hex keypad onto the memory Input/Output bus. 2114 Static Ram The 2114 Static Ram is a typical static ram. In the lab you will substitute a 6116 Static Ram for the 2114. The two chips work basically the same except that the 6116 also has an output enable pin that must be asserted when reading from the chip. The 2114 is a 1K X 4 memory that uses 4096 internal flip flops to store data. The chip is enabled for use by asserting chip_select, CS. Write enable, 70

WE, is asserted to write data to the chip and not asserted to read data from the chip. In addition there are 10 address lines, Ai, to address a particular 4 bit piece of data (nibble) and 4 input/output lines, IOi. The IO lines are inputs when WE is asserted and outputs when WE is not asserted. In order to read from the chip the chip control signals must be applied in the correct order and meet timing constraints and the output data will be available after a specified delay. In order to write to the chip, the chip control signals and input data must be applied in the correct order and meet timing constraints. The order and timing of events is referred to as the read cycle and the write cycle. These cycles are carefully specified in the manufacturer's data books. The timing diagram that follows shows suitable read and write cycles. The Controller The controller is a sequential circuit that is responsible for generating the correct sequence of control signals to cause things to happen in the data path circuit. That is, the output signals of the controller are the input control signals of the data path. The controller used in this example uses a 74194 shift register to generate a sequence of signals, Φ1,Φ2,Φ3,Φ4 that are decoded (combined with simple logic functions) to generate the required control signals. The 74194 generates the sequence of signals following release of the push button as shown in the controller circuit diagram below. Note that a 1 cycle synchronous /GO signal, generated as per the pop machine example, initiates the 74194 sequence. To fully understand the controller the 74194 must be well understood. 71

72 System Timing Diagram

74194 Universal 4-bit Shift Register This positive edge triggered shift register call hold data, shift data left, shift data right, or load data depending upon the mode control signals S1 and S0 as given below. S1S0 function 00 hold 01 shift right 10 shift left 11 load The function takes place on the positive edge of the clock. LS1 is the left shift input and RS1 is the right shift input. A, B, C, and D are the input pins for loading new data and a, b, c and d are the shift register output bits (a is the leftmost bit). The CLR input on the 74194 is an asynchronous reset; that is the shift register is cleared immediately upon assertion of CLR and does not wait for a clock edge as in the case of the synchronous clear on the 74163. Note that feeding d back into RS1 and only shifting when GO + Φ1 + Φ2 + Φ3 + Φ4 is asserted results in a sequential circuit that cycles through 8 states. The equations for all the required control signals are given on the timing diagram. 73

Gate Outputs Logic gates and other logic components such as flip-flops, registers and counters typically have one of three types of outputs; totem pole, open collector or tri-state. These are described below. Totem Pole Outputs This is the most common gate output. Outputs of this type have circuitry to pull the output down to the low voltage level and circuitry to pull the output up to the high voltage level. The outputs provide good high and low logic levels for inputs of the same logic family. The output circuitry for both TTL gates and CMOS gates is illustrated below. 74

Vcc Inputs Circuitry Output Vcc Inputs Circuitry Output With these circuits, the top transistor is on and the bottom transistor off for a high level output and the top transistor is off and the bottom transistor on for a low level output. 75

Open Collector Outputs This type of output is provided to drive nonstandard loads such as light emitting diodes, lights and relays and to enable gate outputs to be connected together to realize wired logic and to drive busses. An open collector gate output is illustrared below. There is no pull up circuitry and the collector is open as an output. The output transistor is either on, for a low level, or off. When off, the output impedance of the circuit is high. The two output states are often called Low and High Z. Inputs Output Circuitry The symbols for an open collector NAND gate, an open collector inverter and an open collector buffer are shown below. The vertical line at the output indicates open collector. Collector Open Collector Open Collector Open NAND Inverter Buffer Wired Logic With wired logic, open collector gate outputs are wired together to realize certain logic functions as illustrated below. The pull up resistor is designed to provide a suitable high voltage level. 76

+5V a f /b c /d e f = /(a./b). /(c+/d)./e For positive logic, as illustrated above, the wired connection performs the AND function and the connection is referred to as a wired AND connection. When using mixed mode logic with a wired connection labelled as shown below the connection is referred to as a wired OR connection and f = a + b. +5V a(l) f(l) b(l) 77

When using mixed mode logic with a wired connection labelled as shown below the connection is referred to as a wired AND connection and f = a.b. +5V a(h) f(h) b(h) Open Collector Bus Drivers of Open collector gates are sometimes used to enable one many devices to drive a bus as shown below. +5V enable1 enable2 enable3 enable4 data1 data2 data3 data4 Only one enable signal is asserted at a time. When enablei is asserted /datai is placed on the bus. This data value can be the input to one or more device inputs that may also be connected to the bus. Note that inputs are not shown in the partial bus circuit above. Note also that the pull up resistor must be designed to give good high and low voltage levels. 78

Tri-State Outputs Gates with tri-state outputs have output states that can be High, Low or High Z depending upon an enable signal as shown for the tri-state buffer below. /enable a b Tri-State Buffer For this buffer, when enable is asserted b = a. When enable is not asserted, b = High Z. Tri-state gates, such as the buffer shown above, are widely used to connect multiple devices to a bus. Only one enable is asserted at a time and the enabled device pulls the bus both High and Low as required. No pull up resister is required as in the open collector bus connection method. Hazards Hazards are circuit conditions that may cause a glitch in the output of a combinational circuit when a circuit input changes level. A glitch is a momentary output pulse. We consider the case where only one input changes level at a time. Glitches are very common when two or more inputs change level simultaneously or almost simultaneously but these cases are seldom studied. Glitches may or not be a problem in a circuit. For example, glitches in the combinational circuits for the excitation variables of a clocked sequential are not a problem since the glitches disappear before the next clock pulse active edge arrives. Glitches are a problem in combinational circuits that drive a clock input and in sequential circuits that don't use a clock. Hazards are easy to detect in 2 level combinational circuits but more difficult to detect in multilevel combinational circuits. We will deal primarily with 2 level circuits. Hazards are classified as 0 static hazards, 1 static hazards or dynamic hazards. Glitches corresponding to these hazards are illustrated below. 79

Glitch from 0 Static Hazard Glitch from1 Static Hazard Glitch from Dynamic Hazard For a 0 static hazard the circuit output should remain 0 but it may have a 1 glitch as shown. For a 1 static hazard the circuit output should remain 1 but it may have a 0 glitch as shown. For a dynamic hazard the circuit should go cleanly from one level to another but it may have one or more glitches as shown. Static Hazards Static hazards in 2 level circuits can be detected and eliminated by considering the K-map for the circuit. Consider the following example. ab 00 01 11 10 00 1 1 0 0 cd 01 1 1 0 0 11 0 1 1 0 10 0 1 1 0 f The three prime implicants that cover the 1s of f are shown. If f is realized as f = /a./c + b.c, a static hazard exists when inputs change so that a different prime implicant provides the 1 output.. 80

For example, when abcd = 0101 prime implicant /a./c provides the 1 output. When the input changes to abcd=0111 prime implicant b.c provides the 1 output. If prime implicant /a./c goes to 0 faster than prime implicant b.c goes to 1, a 1 glitch will occur and the circuit is said to have a 1 static hazard. The hazard can be eliminated by using the redundant prime implicant, /a.b, to realize f. That is, realize f as f = /a./c + a.b + /a.b. This take one more 2 input AND gate and a 3 input rather than 2 input OR gate but the circuit will be hazard free. To eliminate static hazards in 2 level combinational circuits include redundant prime implicants so that a single prime implicant covers all transitions between adjacent cells with a 1 output. The same principal applies when functions are realized in POS form. A 2 level combinational circuit that has no 1 static hazards, has no 0 static hazards and no dynamic hazards. (This is proven somewhere but the proof will not be studied in this course. ) Dynamic Hazards A multilevel combinational circuit has a dynamic hazard if there are an odd number greater than or equal to 3, sensitized paths from an input or its complement to the output. Consider the circuit below b a c d g e f When b=1 there are 3 sensitized paths between the input a and the output g. Note that if b=0 the top path is not sensitized because the output of the AND is always 0 and therefore not sensitive to 81

changes in a. A timing diagram for input a changing from 0 to 1 is shown below. The diagram assumes all gates have the same delay. a c e f d g The circuit has a dynamic hazard according to the definition. With the assumed delay values the dynamic hazard gave rise to the glitch shown in the timing diagram. Regardless of the delay values, the circuit has a dynamic hazard. However, the glitch will only occur for specific ranges of component delay times. 82

Simulation of Gate Circuits It is often desireable to simulate logic circuits to get a better understanding of their operation. Simulation programs like LogicWorks are widely used for this purpose. In this section we will discuss the theory behind a simple but very useful and widely used simulation approach. The approach models real gates as ideal gates followed by a delay of n dt time units. With this form of gate model, logic variables are specified and evaluated only at times idt so we let x(t) = x(idt) = xi. Therefore ci = ai-3.bi-3 for example, models an AND gate with 3 units of delay. To model the following circuit a c d b when the top NOR gate has one unit of delay and the bottom NOR gate has 3 units of delay we would write the following equations known as difference equations ci = /(ai-1 + di-1) di = /(ci-3 + bi-3) Given input variables ai and bi, we can solve for output variables ci and di providing 1 past value of di and 3 past values of ci are also given. A spreadsheet program is very convenient for evaluating and displaying the results as shown below. 83

i a b c d -3 FALSE TRUE -2 FALSE TRUE -1 FALSE FALSE TRUE FALSE 0 TRUE FALSE TRUE FALSE 1 TRUE FALSE FALSE FALSE 2 TRUE FALSE FALSE FALSE 3 FALSE FALSE FALSE FALSE 4 FALSE FALSE TRUE TRUE 5 FALSE TRUE FALSE TRUE 6 FALSE TRUE FALSE TRUE 7 FALSE TRUE FALSE FALSE 8 FALSE FALSE TRUE FALSE 9 FALSE FALSE TRUE FALSE 10 FALSE FALSE TRUE FALSE In the above table, generated by Excel, the bold values are calculated by Excel and the other values are initial and input values. The table shows how the circuit responds to a short input a pulse followed by a short input b pulse. 84

Miscellaneous Circuits and Components Multiplexors A multiplexor routes 1 of many inputs to its output under the control of 1 or more select signals. Multiplexors are very useful components. 85

X0 X1 0 1 S Y Y = X0./C + X1.C C 2-input multiplexor X0 0 X1 1 X2 X3 X4 X5 X6 2 3 4 5 6 Y Y = X0./C2./C1./C0 + X1./C2./C1.C0 + X2./C2.C1./C0 + X3./C2.C1.C0 + X4.C2./C1./C0 + X5.C2./C1.C0 + X6.C2.C1./C0 + X7.C2.C1.C0 X7 7 S2 S1 S0 C2 C1 C0 8-input multiplexor Multiplexors for Logic It is possible to use a 2 n input mux to realize any function of n+1 variables. 86

Example a b c f ------------------- 0 0 0 1 0 0 1 0 ------------------- 0 1 0 0 0 1 1 0 ------------------- 1 0 0 0 1 0 1 1 ------------------- 1 1 0 1 1 1 1 1 c 0 c 1 0 1 2 3 S1 S0 f a b Multiplexors for Routing Example: The B stage of the 74194 universal shift register. 87

0 A 1 C 2 D B B 3 S1 S0 Demultiplexors A demultiplexor routes a single input to one of many outputs under the control of select signals as illustrated below. 88

X 0 Y0 = X./A S 1 Y1 = X.A A 2-output demultipexor X 0 1 2 3 4 5 6 Y0 = X./C./B./A Y1 = X./C./B.A Y2 = X./C.B./A Y3 = X./C.B.A Y4 = X.C./B./A Y5 = X.C./B.A Y6 = X.C.B./A S2 S1 7 S0 Y7 = X.C.B.A C B A 8-output demultiplexor Decoders A binary decoder is the same as a demultiplexor. When used as a decoder the input signal X acts an enable. When X = 0, all outputs are 0. When X = 1, one and only one output is asserted depending 89

upon the input combination of C, B and A. We say the outputs decode the select inputs. Decoders are commonly used to decode the state of a sequential circuit. They may also be used to generate combinational logic functions by using OR gates to combine the required minterms. The example below illustrates logic function generation. 0 1 2 X =! 3 4 5 6 f = m1 + m3 + m5 + m7 S2 S1 7 S0 C B A 74163 Counter Circuits Cascaded Counters Use ripple carry out to enable counting of the next most significant stage. 90

+5V 7 10 P T 2 CLK 6 D 5 C 4 B 3 A 9 LOAD 1 CLR 163 RCO D C B A 15 11 12 13 14 7 10 P T 2 CLK 6 D 5 C 4 B 3 A 9 LOAD 1 CLR 163 RCO D C B A 15 11 12 13 14 Count from 0 to a limit +5V 7 10 P T 2 CLK 6 D 5 C 4 B 3 A 9 LOAD 1 CLR 163 RCO D C B A 15 11 12 13 14 DCBA el even This circuit counts from 0 to 11 and then repeats. It is called a modulo 12 counter. It has 12 states. 91

+5V 7 10 P T 2 CLK 6 D 5 C 4 B 3 A 9 LOAD 1 CLR 163 RCO D C B A 15 11 12 13 14 DCBA This counter counts from a base of 10 to 15. It has 6 states. Generate a waveform in response to release of a pushbutton The following circuit has a zero count rest state and counts one, two, three... ten, zero... upon application of a synchronized single cycle GO signal. 92

DCBA GO +5V 7 10 P T 2 CLK 6 D 5 C 4 B 3 A 9 LOAD 1 CLR 163 RCO D C B A 15 11 12 13 14 /zero ten The 10 nonzero states can be decoded and ORed to generate any 10 cycle waveform. For example, a signal generated from the following K-map will be asserted when the counter state is two, four, six and ten. D,C 00 01 11 10 00 1 B,A 01 11 10 1 1 1 signal 93

Transmission Gates and Steering Logic NMOS and PMOS technology is suitable for inline switching of signals. Inline switching of signals using can be used to 'steer' signals to an output point. This can be an effective way to realize logic circuits. In the following we assume positive logic. In the following circuit, a 0 is steered to the output when c=1.when c=0 the output is high impedance. 0 output c In the following circuit, a 1 is steered to the output when c=1.when c=0 the output is high impedance. 1 output /c In the following circuit, an input signal x (x may be 0 or 1) is steered to the output when c=1.when c=0 the output is high impedance. This circuit is called a transmission gate. /c x output x /c output c c Circuit Equivalent Symbol 94

Consider the realization of a 2-input NAND gate using the above circuits. We need to steer a 0 to the output when a and b are 1 and we need to steer a 1 to the output when /a or /b is 1. The following circuit does the required steering. If the circuit is rearranged and Vcc is used instead of 1 and ground is used instead of 0 the circuit is a standard CMOS NAND gate. 0 a b output 1 1 a b Consider the following 4-input multiplexor circuit realized with steering logic. x0 x1 x2 a b /a /b a /b /a b /a b a /b output x3 /a a /b b This circuit requires the complement of the steering signals a and b. 95

The following circuit is used to generate complements. +5V /x x In this circuit, x can be looked upon as a steering signal that steers 5v or ground potential to the output. 96

Sequential Circuit Timing The key timing parameters for sequential circuits are, Ts the setup time, Th the hold time, and Tpf the propagation delay of the flip flops and Tpl, the propagation delay of combinational logic in the sequential circuit feedback loop.. These have been defined earlier in the course. From these parameters and the circuit under consideration it is possible to calculate the minimum allowable clock period, Tcpmin, and maximum allowable clock skew, Tcsmax, of the circuit. Clock skew is the time between the application of the active edge of the clock to two flip flops in a sequential circuit. Clock skew is usually due to wiring delay. The maximum circuit clock frequency, fmax, is given by fmax = /Tcpmin Example of Minimum Clock Period Calculation Consider the following sequential circuit. combinational logic T pl T s T h D T pf T clock period >= Ts + Tpf + Tpl Therefore Tcpmin = Tsmax + Tpfmax + Tplmax 97

Example of Maximum Clock Skew Calculation Consider the following portion of a sequential circuit. combinational logic T pl T s1 T T pf1 h1 D clock1 T s2 T pf2 T D h2 clock2 If the positive edge of clock2 occurs slightly before the positive edge of clock1 becuase of wiring delay in the clock lines, the lower flip flop will get the intended new value based on the old value of the upper flip flop. If, however, the positive edge of clock2 occurs considerably after the positive edge of clock1, the lower flip flop will get a new value based upon the new value received by the upper flip flop. This is not what is intended by the circuit. To quantify the situation, let Ts = time of positive edge of clock2 - time of positive edge of clock1 For the lower flip flop to get correctly updated Tsmax <= Tpf1min + Tplmin - Th2max The following timing diagram should clarify this relationship. 98

clock1 D2 T pf1 + T pl T h2 clock2 T s For the lower flip flop to get the intended value, the edge of clock2 must occur with at least Th2 time left before D2 goes high in order to meet the hold time of the lower flip flop Metastability It is important that the active clock edge for a flip flop not occur during the setup and hold time of the flip flop. If the active clock edge does occur during the setup and hold time the circuit may become metastable and take a long time (milliseconds) to settle to a high or low logic level. Metastability is caused by what are called runt pulses. These are small pulses that can arise when setup and hold times are not satisfied that are not sufficient to cause a flip flop to properly change state. Consider the following simple flip flop circuit. 99

D X Y clock D should be stable while the clock is high for correct operation as shown below. If however, as also shown below, D changes close to a clock edge, X or Y may be a runt pulse that is insufficient to cause the flip flop to change state. The flip flop may slowly change state or it may start to change state then revert to its old state. This slow, nondeterministic operation is known as metastability and must be avoided for reliable circuit operation. D clock X runt pulse Y possibleresponses 100

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