INTERCONNECT-CENTRIC DESIGN FOR ADVANCED SOC AND NOC

Similar documents
2B1459 System-on-Chip Applications (5CU/7.5ECTS) Course Number for Graduate Students (2B5476, 4CU)

D.Sc. (Tech) Tero Säntti (1974) 29 April Publications

Optimizing Configuration and Application Mapping for MPSoC Architectures

Extending Platform-Based Design to Network on Chip Systems

From Bus and Crossbar to Network-On-Chip. Arteris S.A.

Simulation and Evaluation for a Network on Chip Architecture Using Ns-2

3D On-chip Data Center Networks Using Circuit Switches and Packet Switches

CURRICULUM VITAE (D.Sc. (Tech.) Tero Säntti, )

Introduction to Exploration and Optimization of Multiprocessor Embedded Architectures based on Networks On-Chip

Multiprocessor System-on-Chip

CLEEN - The vehicle for SGEM

AN EVENT-BASED NETWORK-ON-CHIP MONITORING SERVICE

Computer System Design. System-on-Chip

On-Chip Communications Network Report

CLASSIC -- Overall Match Results XXV TCC-Cup Printed elokuu 18, 2013 at 19:17

1 Introduction. Kari I. Leväinen

Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture AWET YEMANE WELDEZION

A CDMA Based Scalable Hierarchical Architecture for Network- On-Chip

A RDT-Based Interconnection Network for Scalable Network-on-Chip Designs

Tero Säntti. A Co-Processor Approach for Efficient Java Execution in Embedded Systems

Best paper, 14th International Conference on Computer Systems and Technologies.

CONSTRAINT RANDOM VERIFICATION OF NETWORK ROUTER FOR SYSTEM ON CHIP APPLICATION

Interconnection Generation for System-on-Chip Design and Design Space Exploration

Multistage Interconnection Network for MPSoC: Performances study and prototyping on FPGA

Design and Implementation of an On-Chip timing based Permutation Network for Multiprocessor system on Chip

Academic Course Description

XVIII Finnish- Austrian Orthopaedic Trauma Course January 24 30, 2015 Congress Center, Hotel Montana, Oberlech, Austria

The agenda of the Shanghai healthcare delegations meeting on September 5 th morning at Tekes

Hardware Implementation of Improved Adaptive NoC Router with Flit Flow History based Load Balancing Selection Strategy

Introduction to System-on-Chip

Design and Verification of Nine port Network Router

2014 International Symposium on System-on-Chip

Analysis of Error Recovery Schemes for Networks-on-Chips

Applying the Benefits of Network on a Chip Architecture to FPGA System Design

SOC architecture and design

Building a functioning startup ecosystem

XV Finnish-Austrian Orthopaedic Trauma Meeting January 24 31, 2009 Hotel Montana, Oberlech, Austria

Interconnection Networks

SoC IP Interfaces and Infrastructure A Hybrid Approach

AN EFFICIENT DESIGN OF LATCHES FOR MULTI-CLOCK MULTI- MICROCONTROLLER SYSTEM ON CHIP FOR BUS SYNCHRONIZATION

Architectural Level Power Consumption of Network on Chip. Presenter: YUAN Zheng

Switched Interconnect for System-on-a-Chip Designs

THEMATIC REVIEW ON ADULT LEARNING

A Survey of Research and Practices of Network-on-Chip

Performance comparison of selected wired and wireless Networks on Chip (NoC) architectures

Lizy Kurian John Electrical and Computer Engineering Department, The University of Texas as Austin

SOCWIRE: A SPACEWIRE INSPIRED FAULT TOLERANT NETWORK-ON-CHIP FOR RECONFIGURABLE SYSTEM-ON-CHIP DESIGNS

A Generic Network Interface Architecture for a Networked Processor Array (NePA)

How To Write An Fpa Programmable Gate Array

Lesson 7: SYSTEM-ON. SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY. Chapter-1L07: "Embedded Systems - ", Raj Kamal, Publs.: McGraw-Hill Education

What is a System on a Chip?

In-network Monitoring and Control Policy for DVFS of CMP Networkson-Chip and Last Level Caches

On-Chip Interconnect: The Past, Present, and Future

INVENTORY MANAGEMENT: Principles, Concepts and Techniques

RAPID PROTOTYPING OF DIGITAL SYSTEMS Second Edition

Computer Engineering: MS Program Overview, Fall 2013

Hyper Node Torus: A New Interconnection Network for High Speed Packet Processors

Final report for. SoC-SME feasibility project

Qsys and IP Core Integration

Emerging Trends in Software Testing Introduction to course

An Initiative towards Open Network-on-Chip Benchmarks

Dissemination of air quality information in Finland the national air quality portal

NELI-Programme. Kymenlaakso Logistics Development Programme Raija Salo, March 2009

ESTC2014 September 16-18, 2014 Helsinki, Finland

MULTIPOS D5.3 Version 1.0 Winter School 1

System-on. on-chip Design Flow. Prof. Jouni Tomberg Tampere University of Technology Institute of Digital and Computer Systems.

A Hardware and Software Monitor for High-Level System-on-Chip Verification

Architectures and Platforms

Towards a Design Space Exploration Methodology for System-on-Chip

Real-time Processor Interconnection Network for FPGA-based Multiprocessor System-on-Chip (MPSoC)

Chapter 12: Multiprocessor Architectures. Lesson 04: Interconnect Networks

THE NORDIC MODEL. Embracing globalization and sharing risks

Quality-of-service and error control techniques for mesh-based network-on-chip architectures

SoC-Based Microcontroller Bus Design In High Bandwidth Embedded Applications

Transcription:

INTERCONNECT-CENTRIC DESIGN FOR ADVANCED SOC AND NOC

Interconnect-Centric Design for Advanced SoC and NoC Edited by Jari Nurmi Tampere University of Technology, Finland Hannu Tenhunen Royal Institute of Technology, Sweden Jouni Isoaho University of Turku, Finland and Axel Jantsch Royal Institute of Technology, Sweden KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

ebook ISBN: 1-4020-7836-6 Print ISBN: 1-4020-7835-8 2005 Springer Science + Business Media, Inc. Print 2004 Kluwer Academic Publishers Dordrecht All rights reserved No part of this ebook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Springer's ebookstore at: and the Springer Global Website Online at: http://ebooks.kluweronline.com http://www.springeronline.com

Contents Preface vii Part I PHYSICAL AND ELECTRICAL ISSUES 1 Communication-based Design for Network-on-Chip Jan Rabaey 2 Wires as Interconnects Li-Rong Zheng and Hannu Tenhunen 3 Global Interconnect Analysis 55 Tero Nurmi, Li-Rong Zheng, Jian Liu, Tapani Ahonen, Dinesh Pamunuwa, Jouni Isoaho and Hannu Tenhunen 4 Design Methodologies for On-Chip Inductive Interconnect 85 Magdy Ali El-Moursy and Eby Friedman 5 Clock Distribution for High-Performance Designs 125 Stefan Rusu 3 25 Part II LOGICAL AND ARCHITECTURAL ISSUES 6 Error-Tolerant Interconnect Schemes 155 Heiko Zimmer and Axel Jantsch 7 Power Reduction Coding for Buses 177 Paul P. Sotiriadis 8 Bus Structures in Networks-on-Chip 207 Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna and Timo D. Hämäläinen

vi 9 From Buses to Networks David Sigüenza Tortosa and Jari Nurmi 10 Arbitration and Routing Schemes for On-Chip Packet Networks Heikki Kariniemi and Jari Nurmi 231 253 Part III DESIGN METHODOLOGY AND TOOLS 11 Self-Timed Approach for Noise Reduction in NoC 285 Pasi Liljeberg, Johanna Tuominen, Sampo Tuuna, Juha Plosila and Jouni Isoaho 12 Formal Communication Modelling and Refinement Juha Plosila, Tiberius Seceleanu and Kaisa Sere 13 Network Centric System-Level Model for Multiprocessor Systemon-Chip Simulation Jan Madsen, Shankar Mahadevan and Kashif Virk 14 Socket-based Design Techniques using Decoupled Interconnects Drew Wingard Part IV APPLICATION CASES 15 Interconnect and Memory Organization in SOCs for Advanced Set- Top Boxes and TV Kees Goossens, Om Prakash Gangwal, Jens Röver and A.P. Niranjan 16 A Brunch from the Coffee Table - Case Study in NOC Platform 425 Design Tapani Ahonen, Seppo Virtanen, Juha Kylliäinen, Dragos Truscan, Tuukka Kasanko, David Sigüenza-Tortosa, Tapio Ristimäki, Jani Paakkulainen, Tero Nurmi, Ilkka Saastamoinen, Hannu Isännäinen, Johan Lilius, Jari Nurmi and Jouni Isoaho 315 341 367 399

Preface This book was mainly catalyzed by the SoC-Mobinet EU-project (IST 2000-30094), where the editors have acted in 2001-2004 to create the European System-on-Chip infrastructure for joint research and education. The topic was seen very important especially after writing the previous book (Networks on Chip) where the higher-level on-chip communication issues were tackled. In this book, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design. We owe very much to the authors of this book, who represent the expertise on different aspects of interconnects, communication and system-on-chip and network-on-chip development worldwide. One major contributing project was also the Complain (Communication platform architectures for gigascale integration) project in the Finnish-Swedish EXSITE research programme, mainly supported by TEKES, Vinnova, Nokia and Ericsson. We were happy to have such a good crew to assist us in creating the book for the interested readers in this field. We hope that you enjoy the book and, even more, wish that it will be of professional benefit to you! Tampere, Stockholm, Turku January 2004 JARI NURMI HANNU TENHUNEN JOUNI ISOAHO AXEL JANTSCH