Lecture 150 Clock and Data Recovery Circuits (09/03/03) Page 150-1

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-1 LECTURE 150 CLOCK N T RECOVERY CRCUTS NTROUCTON Objective The objective of this presentation is: 1.) Understand the applications of PLLs in clock/ recovery 2.) Examine and characterize CR circuits Outline ntroduction and basics of clock and recovery circuits Clock recovery architectures and issues Phase and frequency detectors for random CR architectures Jitter in CR circuits VCOs for CR applications Examples of CR circuits Summary Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-2 BSCS OF CLOCK N T RECOVERY CRCUTS Why Clock and ata Recovery Circuits? n many systems, is transmitted or retrieved without any additional timing reference. For example, in optical communications, a stream of flows over a single fiber with no accompanying clock, but the receiver is required to process this synchronously. Therefore, the clock or timing information must be recovered from the at the receiver. ata Recovered Clock Most all clock recovery circuits employ some form of a PLL. Fig. 4.2-01 t

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-3 Properties of NRZ ata Most binary is transmitted in a nonreturn-to-zero (NRZ) format. NRZ is compared with return-to-zero (RZ) below. NRZ ata T b RZ ata Fig. 4.2-02 The NRZ format has a duration of T b for each bit period. The bit rate, r b = 1/T b in bits/sec. The bandwidth of RZ > bandwidth of NRZ Maximum bandwidth of NRZ is determined by a square wave of period 2T b. n general, NRZ is treated as a random waveform with certain known statistical properties. Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-4 The Challenge of Clock Recovery 1.) The may exhibit long sequences of ONEs or ZEROs requiring the CRC to remember the bit rate during such an interval. The CRC must not only continue to produce the clock, but do so without drift or variation in the clock frequency. 2.) The spectrum of the NRZ has nulls at frequencies which are integer multiples of the bit rate. For example, if r b = 1Gb/s, the spectrum has no energy at 1GHz. 1ns 2ns 1ns Fig. 4.2-03 500 MHz square wave with all even-order harmonics absent

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-5 NRZ ata Spectrum The autocorrelation function of a random binary sequence can be written as R x (τ) = 1 - τ T b, τ < T b = 0, τ = T b From this, the power spectral density of a random binary sequence is written as, sin(ωt b /2) P x (ω) = T b ωt b /2 which is illustrated as, P x (ω) 2 0 2π T b 4π T b 6π T b ω 8π T b Fig. 4.2-04 S.K.Shanmugam, igital and nalog Communication Systems, New York: Wiley &Sons, 1979. Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-6 Edge etection CRC circuits require the ability to detect both the positive and negative transitions of the incoming as illustrated below, NRZ ata Edge etection Methods of edge detection: 1.) EXOR gate with a delay on one input. Fig. 4.2-05 2.) differentiator followed by a full-wave rectifier. out Fig. 4.2-06 d dt Out n out Fig. 4.2-07

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-7 Edge etection and Sampling of NRZ ata - Continued 3.) Use a flipflop that operates on both the rising and falling edges. This technique takes advantage of the fact that in a phase-locked CRC, the edge-detected is multiplied by the output of a VCO as shown. n effect, the transition impulses sample points on the VCO output. a.) Master-slave flipflop consisting of two latches. CLK Latch Edge etector X VCO out Fig. 4.2-08 Latch out CLK X VCO Fig. 4.2-09 b.) ouble-edge-triggered flipflop. CLK Latch X VCO MUX out CLK Latch Fig. 4.2-10 Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-8 CLOCK RECOVERY RCHTECTURES N SSUES Clock Recovery rchitectures From the previous considerations, we see that clock recovery consists of two basic functions: 1.) Edge detection 2.) Generation of a periodic output that settles to the input rate but has negligible drift when some transitions are absent. Conceptual illustration of these functions: Edge etector High- Oscillator out Fig. 4.2-11 n essence, the high- oscillator is synchronized with the input transitions and oscillates freely in their absence. Synchronization is achieved by means of phase locking.

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-9 Phase Locked Clock Recovery Circuit Circuit: Edge etector LPF VCO CLK Fig. 4.2-11 Operation: 1.) ssume the input is periodic with a frequency of 1/T b (Hz). 2.) The edge detector doubles the frequency causing the PLL to lock to 2/T b (Hz). 3.) f a number of transitions are absent, the output of the multiplier is zero and the control voltage applied to the VCO begins to decay causing the oscillator to drift from 1/T b (Hz). 4.) To minimize the drift due to the lack of transitions, τ LPF >> Maximum allowable interval between consecutive transitions. 5.) The result is a small loop bandwidth and a narrow capture range. Fortunately, most communication systems guarantee an upper bound of the allowable interval between consecutive transitions by encoding the. Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-10 Frequency ided cquisition Frequency acquisition can be accomplished with and without an external reference. f an external reference clock is available, frequency acquisition can be done with a secondary PLL loop having a PF. Frequency acquisition with Frequency acquisition with a a external reference: frequency detector: Phase etector Charge Pump1 Phase etector Charge Pump1 N VCO Loop Filter _clk _clk VCO Loop Filter ref clk Phase/ Freq. etector Charge Pump2 Freq. etector Charge Pump2 f no reference clock is available, a frequency detector has to be used which requires and clocks and for typical implementations, the VCO frequency cannot be off more that about 25% of the rate.

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-11 PHSE ETECTORS FOR RNOM T Linear Phase etectors up This type of detector is represented by the Hogge detector. down B clk Clock rising edge is at center: Clock is 0.5 period ahead of center. clk clk B B up down up down C. R. Hogge, EEE J. Lightwave Technology, pp. 1312-1314, 1985. Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-12 Linear Phase etector Continued Transfer characteristics of the Hogge phase detector: Normalized average up/down output +1.0 +0.5 11001100 density - π 0 + π 101010 density -0.5-1.0 Phase error Linear gain characteristics Phase detector gain is 0.5 for 11001100 transition density Small jitter generation due to P Suffers from bandwidth limitations Have static phase offset due to mismatch

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-13 Binary Phase etectors This type of phase detector is represented by the lexander type of phase detector. clk B Normalized average up/down output 0-1 +1 C Phase error up down Clock is ahead Clock is behind B C B C Binary Phase etector Truth-Table BC ecision Output 000 Tri-state ------- 001 Clock is ahead own 010 Error ------- 011 Clock is behind Up 100 Clock is behind Up 101 Error ------- 110 Clock is ahead own 111 Tri-state ------- High phase detector gain Causes higher output jitter compared to linear phase detectors Static phase offset set by sampling aperture errors Widely used in digital PLL and LL s J..H. lexander, EE Electronics Letters, pp. 541-542, 1975. Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-14 Binary Phase etectors Continued Meghelli Phase etector retimed Normalized average up/down output +1 clk 0 Phase error up/down -1 Clock lagging : clk retimed up / down Similar to the lexander phase detector Simpler implementation clk retimed up / down Clock leading : M. Meghelli, et. al. SSCC 2000, pp. 56-57.

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-15 Half-Rate etectors These detectors sense the input random at full rate but employ a VCO running at half-rate. Failure of the Hogge detector: random sequence can be selected such that the half-rate clock continues to sample a high level on the waveforms. Y CK FF 1 B FF 2 X B CK Y 030903-05 X t Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-16 Half-Rate etectors Continued What is required is to use both edges of the half-rate clock. simple linear half-rate P using latches: V out1 T CK L 1 CK B L 2 B 030904-01 This detector: 1.) etects edges 2.) Produces proportional pulses However, it must also provide a reference output so as to uniquely represent the phase error for different transitions. V out1 t

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-17 Complete Linear Half-Rate P C gives pulses of width T CK /2 which serves as the reference output. V out1 V out1 T CK L 1 L 3 C out1 CK B B out2 L 2 L 4 030904-02 Retimed and demultiplexed out How does the P lock to random? f the clock edge is to strobe the in the middle of the eye, then the proportional pulses are T CK /4 wide. (The disparity between the average values of these outputs is removed by scaling down the effect of the output of the second EXOR by a factor of two (i.e. halving the current in the charge pump.) V out1 V out2 t Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-18 Early-Late Circuits as a Half-Rate P Since the lexander P already requires sampling on both clock edges for full-rate detection, it must employ additional phase of the clock if it is to operate in the half-rate mode. Use of quadrature clocks for binary half-rate detection: FF 1 1 CK G 1 X 2 3 1 FF 3 3 CK CK G 1 Y CK t FF 2 2 030904-03 1, 2, and 3 have the same role as the consecutive samples in a full-rate counterpart. However, the flip-flops generate skewed outputs requiring additional retiming latches before the results can be applied to XOR gates.

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-19 Early-Late Circuits as a Half-Rate P Continued Effect of skews under locked condition (when CK samples the zero crossings driving FF 3 into metastability): CK f 2 is metastable, then 1 2 and 2 3 are metastable. Since 3 holds its value for T CK /4 seconds after 2 changes, then 2 3 produce an extraneous pulse of width T CK /4 causing the VCO to be disturbed. t desirable to delay 1 by T CK /2 and 2 by T CK /4. CK 1 2 3 1 2 Metastable Metastable 2 3 t 030904-04 Metastable Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-20 FREUENCY ETECTORS FOR RNOM T Rotational Frequency etectors Block diagram (Richman) -clk E-FF E-FF C up +1 Normalized frequncy detector gain -clk B E-FF E-FF Timing diagram example: (VCO clock is faster than the rate) _clk _clk B up down down f 2 frequency error f 2 10 11 01 10 11 11 01 01 10 01 11 01 01 10 11 11 01 Pull in range: ±25% of rate Prone to false locking in presence of jitter and/or short pattern B changing from 00 to 10 OWN pulse, B changing from 10 to 00 UP pulse f 4 3f 8 f 8 0-1 f 8 f 4 3f 8. Richman, Proc. of RE, pp. 106-133, Jan. 1954.

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-21 Phasor iagramexamples of Rotational Frequency etectors Phasor diagrams for a 0101 pattern: f VCO = 1.125 x rate f VCO = 1.250 x rate f VCO = 1.375 x rate f VCO = 1.500 x rate f VCO = 1.625 x rate f the VCO frequency is off more than 50%, the frequency is in the wrong direction. f c 3f c f c 4 2 f c 4 +1 0 Normalized frequncy detector gain f c 4 f c 2 3f c 4 frequency f c error -1 Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-22 Rotational Frequency etectors Continued simpler implementation of the Richman frequency detector (Pottbacker). The samples the clock. E-FF -clk 1 2 -clk E-FF F 3 up / down Logic Table of Pottbacker s Frequency etector 1 2 3 X 1 0 Rising 0-1 Falling 0 +1 Very similar characteristics to that of Richman s frequency detector, however, the implementation is simpler. Pull-in range: ±25% of rate Prone to false locking in the presence of jitter and/or short patterns. Pottbacker, et. al., EEE JSSC, pp. 1747-1751, ec. 1992.

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-23 CR RCHTECTURES Clock Recovery Spectral Line, Early-Late Enam, bidi 1992 nterleaved decision circuit nterleaved ecision Circuit out Output- V Output+ 2 ε F(s) VCO ±CLK Half-rate Clock ata ata ata ata ata Phase etector f = B T n-phase (f = 0.5B T ) uadrature (f = 0.5B T ) Fig. 4.2-15 Comments: Good example of CMOS solution to practical clock recovery circuits Circuit can be analyzed as spectral line or as early-late. clock clock ata clock Fig. 4.2-16 clock clock Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-24 Clock Recovery - uadricorrelator nalog version has three loops sharing the same VCO. LPF sin (ω 1 -ω 2 )t M NRZ ata Edge etector sin ω 1 t cos ω 2 t sin ω 2 t Loop VCO Loop (ω 1 -ω 2 ) P LPF Loop Fig 4.2-13 Edge detector plus three loops- Loops and perform frequency detection Loop performs phase detection Operation: The signal at P is (ω 1 -ω 2 ) cos 2 (ω 1 -ω 2 ) VCO is driven by sin(ω 1 -ω 2 )t + (ω 1 -ω 2 ) Loops and drive the VCO to lock when ω 1 ω 2. s ω 1 -ω 2 approaches zero, Loop begins to generate an asymmetrical signal at node M assisting the lock process. Finally, when ω 1 ω 2, the dc feedback signal produced by Loops and approaches zero and Loop dominates, locking the VCO output to the input. LPF cos (ω 1 -ω 2 )t d dt

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-25 uadricorrelator Continued The use of frequency detection in the quadricorrelator makes the capture range independent of the locked loop bandwidth, allowing a small cutoff frequency in the LPF of Loop so as to minimize the VCO drift between transitions. Because Loops and can respond to noise and spurious components, it is desirable to disable these loops once phase lock has been attained. Since the combination of an edge detector and a mixer can be replaced with a doubleedge triggered flipflop, the quadricorrelator can be implemented in a digital form as shown below. NRZ CLK ata Edge 0 etector 90 CLK Fig. 4.2-14 VCO LPF CLK ll flipflops are double-edge-triggered Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-26 JTTER N CR CRCUTS Jitter nfluence on Clock Recovery Types of jitter: Long term jitter deal Reference Oscillator Output Τ - iverges for a free-runnng oscillator - Meaningful only in a phase-locked system - epends on PLL dynamics Cycle-to-cycle jitter T Fig. 4.2-17 Τ T+ T 1 T+ T 2 T+ T 3 T+ T 4 Fig. 4.2-18 - Of great interest in many timing applications - Mostly due to the oscillator - Usually too fast for the PLL to correct

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-27 Jitter ue to evice Noise 1/f noise: 1/f noise is inversely proportional to frequency and causes the frequency to change very slowly. Easily suppressed by a wide PLL bandwidth. eni 2 B = fw i L i (V2/Hz) and ini 2 = 2BK i fl i 2 (2/Hz) where KF B = 2CoxK Thermal noise: Thermal noise is assumed to be white and is modeled in MOSFETs as, eni 2 8kT 3g m (V2/Hz) and ini 2 8kTg m 3 ( 2 /Hz) The relationship between phase noise and cycle-to-cycle jitter is, T 2 (rms) 4π ω 3 Sφ(ω) (ω-ω o ) 2 o (Razavi: EEE Trans. on Circuits and Systems, Part, Jan. 99) Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-28 Sources of Jitter nput jitter P LPF VCO f osc VCO jitter due to device noise Fig. 4.2-19 φ VCO P LPF VCO f osc VCO jitter due to ripple on control line P LPF VCO Fig. 4.2-20 f osc Fig. 4.2-21 njection pulling of the VCO by the CLK out Substrate and supply noise VCO Fig. 4.2-22

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-29 Substrate and Supply Noise How o Carriers Get njected into the Substrate? 1.) Hot carriers (substrate current) 2.) Electrostatic coupling (across depletion regions and other dielectrics) 3.) Electromagnetic coupling (parallel conductors) Why is this a Problem? With decreasing channel lengths, more circuitry is being integrated on the same substrate. The result is that noisy circuits (circuits with rapid transitions) are beginning to adversely influence sensitive circuits (such as analog circuits). Present Solution: Keep circuit separate by using multiple substrates and put the multiple substrates in the same package. Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-30 Hot Carrier njection in CMOS Technology without an Epitaxial Region Noisy Circuits V V (nalog) uiet Circuits v in v out R L V GS v in v out Substrate Noise v in V (nalog) v ; in v V(igital) ; out igital Ground p+ n- well ;;; n+ n+ ;;;;; p+ p + n+ Hot "C ground" ;;; Carrier ;;;;; Put substrate connections as close to the noise source as possible n+ channel stop (1 Ω-cm) "C ground" p+ channel stop (1Ω-cm) V R L GS v out nalog Ground ;;; n+ ;p+ n+ Back-gating due to a ;;; i momentary change in reverse bias i i p- substrate (10 Ω-cm) V GS v GS Heavily oped p Lightly oped p ntrinsic oping Lightly oped n Heavily oped n Metal Fig. S-01

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-31 Hot Carrier njection in CMOS Technology with an Epitaxial Region Noisy Circuits V V (nalog) uiet Circuits v in v out R L V GS v in v out Substrate Noise v in V (nalog) v ; in v V(igital) ; out igital Ground p+ n- well Put substrate connections Carrier as close to the noise source as possible ;;; n+ n+ ;;;;; p+ p + n+ "C ground" ;;; Hot ;;;;; p - epitaxial layer (15 Ω-cm) "C ground" V R L GS v out nalog Ground ;;; n+ ;p+ n+ Reduced back gating ;;; due to smaller resistance p+ substrate (0.05 Ω-cm) Heavily oped p Lightly oped p ntrinsic oping Lightly oped n Heavily oped n Metal Fig. S-02 Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-32 Computer Model for Substrate nterference Using SPCE Primitives Noise njection Model: V V v in v out igital Ground V(igital) v ; in v out p+ ;;; n+ n+ ;;;;; p+ ;;;;; ;n- p + n+ Hot well ;;; Hot Carrier Coupling Carrier Coupling Coupling ;;;;; p- substrate Heavily oped p Lightly oped p ntrinsic oping Lightly oped n Heavily oped n Metal v in C s3 L 1 C s1 n- well v out Rs1 R s2 C s4 C s2 C s5 R s3 L 2 L 3 Fig. S-06 Substrate C s1 = Capacitance between n-well and substrate C s2, C s3 and C s4 = Capacitances between interconnect lines (including bond pads) and substrate C s5 = ll capacitance between the substrate and ac ground R s1, R s2 and R s3 = Bulk resistances in n-well and substrate L 1, L 2 and L 3 = nductance of the bond wires and package leads

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-33 Computer Model for Substrate nterference Using SPCE Primitives Noise etection Model: V (nalog) R L V GS v in v out Substrate Noise V (nalog) V V GS v in ;;; ;p+ n+ n+ ;;; R L v out nalog Ground V GS Substrate L 6 C s6 R L L 4 R s4 C L C s7 v out C s5 L 5 p- substrate C s5, C s6 and C s7 = Capacitances between interconnect lines (including bond pads) and substrate R s4 = Bulk resistance in the substrate L 4, L 5 and L 6 = nductance of the bond wires and package leads Heavily oped p Lightly oped p ntrinsic oping Lightly oped n Heavily oped n Metal Fig. S-07 Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-34 Other Sources of Substrate njection (We do it to ourselves and can t blame the digital circuits.) Substrate BJT nductor Collector Base Emitter Collector ;;;;;;;; n+ p+ n+ n+ p- well Heavily oped p Lightly oped p ntrinsic oping Lightly oped n Heavily oped n Metal Fig. S-04 lso, there is coupling from power supplies and clock lines to other adjacent signal lines.

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-35 What is a Good Ground? On-chip, it is a region with very low bulk resistance. t is best accomplished by connecting metal to the region at as many points as possible. Off-chip, it is all determined by the connections or bond wires. The inductance of the bond wires is large enough to create significant ground potential changes for fast current transients. v = L di dt Use multiple bonding wires to reduce the ground noise caused by inductance. 20 16 12 8 4 Settling Time to within 0.5mV (ns) Peak-to-Peak Noise (mv) 0 0 1 2 3 4 5 6 7 8 Number of Substrate Contact Package Pins Fig. S-08 Fast changing signals have part of their path (circuit through ground and power supplies. Therefore bypass the off-chip power supplies to ground as close to the chip as possible. V in t = 0 C1 - + C 2 V out V V SS Fig. S-05 Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-36 Summary of Substrate nterference Methods to reduce substrate noise 1.) Physical separation 2.) Guard rings placed close to the sensitive circuits with dedicated package pins. 3.) Reduce the inductance in power supply and ground leads (best method) 4.) Connect regions of constant potential (wells and substrate) to metal with as many contacts as possible. Noise nsensitive Circuit esign Techniques 1.) esign for a high power supply rejection ratio (PSRR) 2.) Use multiple devices spatially distinct and average the signal and noise. 3.) Use quiet digital logic (power supply current remains constant) 4.) Use differential signal processing techniques. Some references 1.).K. Su, M.J. Loinaz, S. Masui and B.. Wooley, Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal C s, J. of Solid-State Circuits, vol. 28, No. 4, pril 1993, pp. 420-430. 2.) K.M. Fukuda, T. nbo, T. Tsukada, T. Matsuura and M. Hotta, Voltage-Comparator-Based Measurement of Equivalently Sampled Substrate Noise Waveforms in Mixed-Signal Cs, J. of Solid-State Circuits, vol. 31, No. 5, May 1996, pp. 726-731. 3.) X. ragones, J. Gonzalez and. Rubio, nalysis and Solutions for Switching Noise Coupling in Mixed- Signal Cs, Kluwer cadmic Publishers, Boston, M, 1999.

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-37 VOLTGE CONTROLLE OSCLLTORS FOR CR PPLCTONS Comparison of VCOs Comparison of VCO Topologies Relaxation Ring LC uadrature LC Control Voltage ifferential ifferential Single-ended ifferential Phase Noise High High Low Moderate Tuning Range Wide Wide Narrow Medium VCO Gain High High Low Medium PVT Variations High High Low Low Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-38 Ring Oscillator Example delay delay delay Current Steering MUX out_ delay delay delay Current Steering MUX out_ VCO control Comments: Tuning can be split into fine and coarse control Very wide tuning range ifferential control Moderate phase noise (See also, Y. Eken, High Frequency Voltage Controlled Ring Oscillators in Standard CMOS, Ph.. issertation, School of ECE, Georgia Tech, Nov. 2003) R. Walker, SSCC 1997, pp. 246-247.

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-39 LC VCO Example V outp C 2C 4C 8C L1 vctrl 1 2 L2 8C 4C outm 2C C M1 M2 VSS bias Comments: Fine tuning is through varactor control Coarse tuning is achieved by binary weighted capacitor array Low tuning range Single-ended control Very good phase noise characteristics Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-40 uadrature LC VCO Example vtunep vtunem VCO tune vtp vtm vtp vtm out2p out2m inp inm vtm vtp LC VCO core inp inm out2m out2p LC VCO core outp outm outp outm VCO buffer VCO buffer outim outip outqm outqp V vftp M5 2 x bias bias M1 vctp M3 M4 vctm vbias 3 vtp 1 2 R3 R1 R2 VSS M6 M2 4 vtm R4 vftm vbias T.P. Liu, EEE VLS 1999, pp. 55-56 V vbias2 Two identical LC VCOs are coupled in quadrature. VCO tuning is achieved through: - djusting the coupling between the two oscillator cores - Changing the LC-tank capacitance L1 R1 R2 L2 out2p out2m outp outm 2C C C1 C2 C 2C 3 1 2 4 inp inm S1 S2 S3 S4 vbias1 vtp vtm 5 6 7 8 R3 R4 R5 R6 VSS.L. Coban, et. al., VLS 2001, pp. 119-120

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-41 esign Procedure for VCOs for CR pplications The following procedure seeks to maximize the tuning range and minimize the phase noise with the knowledge of four parameters: Load capacitance, C L Required output voltage swing Center frequency, f o Power The first two parameters may require a buffer as shown below. VCO Core V L 1 L 2 C buf C L X Y Buffer M1 M2 C buf C L V control Fig. 210-01 Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-42 esign Procedure for VCOs Continued Other circuits that the VCO may have to drive include a flip-flop in a divider chain, two flipflops in the demultiplexer and a 50Ω output driver: Phase etector Procedure: Fig. 210-02 MUX 1.) With the power budget and hence the value of the width of M1 and M2 is chosen to yield an average CM level of approximately 0.5V at the X and Y nodes. Note that when V X = V Y, that V G1 = V G2 = 0. = K'W 2L (V GS-V T ) 2 W : V GS = 0.5V and L g m 2.) esign the inductors, L 1 and L 2. To maximize the tuning range (and ) the inductance must be minimized. To get the oscillator to start-up, the following must hold: (g m R p,min ) 2 = 1 However, R p,min, is the parallel resistance of the tank and is primarily due to the inductor. R p,min L min ω osc (g m L min ω osc ) 2 1 = 1 L min = g m ω osc The above assumes that the is approximately constant with the value of L min. LPF VCO N Output river FF FF

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-43 VCO esign Procedure Continued 3.) With L = L min, the oscillation amplitude is quite small in order to maintain unity loop gain. f the amplitude grows, the transistor nonlinearities reduce the loop gain which may prevent full swing. One must also be careful of the variation of g m and with PVT corners possibly prohibiting oscillation at some corners. Therefore, the values of L and R p must sufficiently exceed L min and R p,min to provide the required voltage swings and start under worst case conditions. 4.) The value of R p can be related to the required output swing as follows. M1 and M2 each have an average current of 0.5. f the drain currents are approximated by sinusoids varying between and zero, the V X and V Y swing from 0.5V - R p and 0.5V + R p. For this voltage sinusoid, the largest peak voltage is 0.5V = R p giving R p,swing = V (minimum parallel tank resistance giving maximum swing) 2 L opt = V 1 2 ω osc 5.) With W/L and L opt known, the varactor capacitance can be found as 1 C tot = ω 2 osc L opt where C tot = C var + C gs + C bds + 4C gd + C inductor + C buffer Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-44 esigning a VCO for CR pplications Use the above procedure to design a VCO for 5GHz using 0.18µm CMOS technology having K N = 120µ/V 2 and V TN = 0.5V. ssume the of the inductor is 5, V = 1.8V and the power is to be 5mW. ssume that C gs + C bds + 4C gd = 300fF, C inductor = 50fF, and C buffer = 200fF. Solution 1.) From the specifications we get = 5mW/1.8V = 2.78m. The W/L can be found as, W L = K N '(0.5V -V TN ) 2 = g m = 2K N ' (0.5 )145 = 6.95mS 2.) The minimum inductance can be found as 1 L min = g m ω = osc 2.78m 0.12m/V 2 (0.9-0.5) 2 = 144.67 145 1 6.95mS 5 2π 5x10 9 = 0.916nH 3.) The value of R p for maximum swing is R p,swing = V 1.8 2 = 2 2.78m = 323.7Ω L opt = V 1 2 ω = 323.7Ω osc 1 5 10πx10 9 = 2.06nH

Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-45 Example - Continued 4.) The value of C tot is, 1 1 C tot = ω osc 2L = opt (10πx10 9 ) 2 (2.06nH) = 491.6 ff Unfortunately, we see that C var = 491.6fF 550fF = -58fF Our only choices are: a.) ecrease the inductor size which will reduce the output swing. b.) ecrease the buffer input capacitance which will degrade the drive capability. c.) ecrease the W/L of the transistors by decreasing the power dissipation 5.) Since the inductance capacitance is small compared to the buffer input capacitance, we will choose to reduce the buffer input capacitance by a half giving C var = 491.6fF 450fF = 42fF Lecture 150 Clock and ata Recovery Circuits (09/03/03) Page 150-46 SUMMRY CR circuits are used for recovering the clock from NRZ The PLL consists of a phase detector, lowpass filter and VCO Phase detectors for random - Linear phase detectors (Hogge) - Binary phase detectors (lexander) - Half-rate detectors (linear and binary) Frequency detectors for random - Rotational frequency detectors (Richman, Pottbacker)) Jitter in CR circuits - Long term and short term - Sources include input, device noise, ripple on VCO control, injection pulling of the VCO, and substrate and supply noise VCOs for CR circuits - LC lower phase noise, less tuning range - Ring oscillator higher phase noise, wide tuning range, compatible with digital CMOS - esign procedure for LC VCOs