TEA1024/ TEA1124. Zero Voltage Switch with Fixed Ramp. Description. Features. Block Diagram

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1 Zero Voltage Switch with Fixed Ramp TEA04/ TEA4 Description The monolithic integrated bipolar circuit, TEA04/ TEA4 is a zero voltage switch for triac control in domestic equipments. It offers not only the control of a triac in zero crossing mode but also the possibility of power control. This is why the IC contains a mains synchronized ramp generator with 40 ms (80 ms) duration (0 Hz). It is suitable for a typical load of 70 W (000 W) meeting the Flicker Standard. (values in brackets relate to TEA4.) Features Direct supply from the mains Definite IC switching characteristics Very few external components Full wave drive no dc component in the load circuit Current consumption. ma Output short circuit protected Simple power control Integrated ramp generator Reference voltage variable by external resistance Pulse position optimization Package: DIP8 Block Diagram D N4007 L R 390 k (R sync ) R k/ W Load 000 W 7 4 C 00 F V V M = 30 V ~ k Ramp generator TEA ms TEA 4 80 ms Sync. logic Supply TIC 3N MT min. max. 00 k Protection 43 k Comparator 3 8 NC NC Pulse amplifier R G 8 MT N Figure. Typical block diagram open loop power control (8)

2 TEA04/ TEA4 Power Supply and its Limitations The voltage limitation contained in the IC allows it to be powered from mains via series resistance R and recti fying diode D between Pin ( Pol/) and Pin 4 (V S ). The capacitor C smooths the supply voltage (see figure ). An internal temperature-compensated limiting circuit protects the module from random peaks of voltage on the mains, and delivers a defined reference voltage during the negative half-cycle. Synchronization Figure. Pulse position optimization The logic function is synchronized by means of a separate resistance R connected between Pin 7 and phase (voltage-synchronization). The width of the pulse can be varied between wide limits by choice of R sync. The larger the value chosen, the wider the output pulse is on Pin. Automatic optimization of the phase of the pulse is necessary, since the latching current of the triac exceeds the steady current by a factor of 3. The phase of the pulse is chosen so that ca. /3 of the pulse width appears before the transition through null and /3 after it (see electrical characteristics and figure ). In order to avoid phase-clipping after the switch-on the first third of the first pulse is automatically suppressed. Full-Wave Logic The full-wave logic ensures that only pairs of pulses can be released, and that these always begin with the positive dv/dt. The load is thus switched on for a minimum of one complete mains cycle. This means that the triac receives a minimum of two driving pulses, so that the unwanted d.c. component in the load circuit is definitely eliminated. Pulse Amplifier The pulse amplifier connected to the output of the fullwave logic circuit, is proof against continuos short-circuits, and delivers negative output pulses of typ. 7 ma, via an integrated limiting resistance, to Pin. Ramp Generator (Figures 3, 4) Ramp voltage which is generated in the IC is available not only at reference Pin, but also at the non-inverted input of the comparator. The current sink which is controlled by D/A converter influences the internal reference voltage at Pin specified by voltage divider. The current sink is turned-off in the reset state of the D/A converter so that the voltage at Pin is primarily specified via the internal voltage divider (ramp starting voltage). In the maximum state of the 4 stage ( stage TEA4) D/A converter, the current sink overtakes the maximum current, whereby the ramp s final (end) voltage has reached. External resistance R x, R y shown in figure 4 are in position to influence the initial ramp voltage as well as the ramp amplitude. If the external resistances ratio R x, R y is the same as that of the internal ratio, the ramp voltage at the beginning remains maintained (constant), only the amplitude is compressed. V.3 V 3.8 V 9 40 T= 40 ms (T= 80 ms) stage ramp Figure 3. Ramp diagram without external circuit t. V (8)

3 TEA04/ TEA4 GND Protection R x R y V S 0 k 0 k 4 D/A converter A D Current sink 4 stage ripple counter 3 0 Period 0 ms (40 ms) Divider : (:4) 7 Sync (0 Hz) 9 4 Figure 4. Principle diagram Generation and evaluation of ramp Period. The time required for one complete cycle of a regular. repeating signal, function, or series of emends.. The tune between two consecutive transients of the pointer or indicating means of an electrical indicating instrument in the same disdain the rest position. Something called periodic fine. Comparator The comparison of set value and measured value is carried out via the two comparator inputs Pin and Pin. Here Pin is the inverting input and has a circuit protecting it against interference spikes. Figure shows the protective circuit of the comparator. Pin is the noninverting input. Ramp generator Firing Pulse Width (Figures, 7) It depends on the latching current as well as on the load current of the used triacs. t p [s] 3 4 f arcsin I L V M P whereas I L [A] = Latching current of the triac V M [V]= Mains voltage, effective P[W] = Power load f[/s] = Mains frequency Firing pulse width is specified through the zero cross over identification which can be influenced by the sync. resistance. R sync [] V M sin. 3 t. p where t p [s] = required ignition pulse width GND Z R T 9 4 Figure. Protective circuit of the comparator 3 (8)

4 TEA04/ TEA4 t p ( ms ) 0.00 V mains = 30 V.00 I L ( ma) P ( W ) Figure. Supply Voltage Due to higher trigger sensitivity of the triac it is supplied with negative signal. It can be supplied via diode and series resistance from the negative half wave of the mains. An internal parallel controller limits the voltage between Pin and 7 to a typical value of. V. Dimensioning of the Series Resistance R (Figures 8, 9) R max 0.8 V Mmin V M V S I tot I x V Smax I tot I tot I S I P I X P(R ) (V M V S ) R = Mains supply = Limiting voltage of the IC = Total current requirement = Current requirement for external circuit. V Mains =30V 0 R ( M ). R ( k ) V Mains =30V t p ( s ) I tot ( ma ) Figure 7. Figure 8. Ignition (Firing) Current The necessary ignition current depends on the specified triac. With the help of a resistance, it is possible to limit its value: R Gmax [].7VV Gmax I Gmax P R ( W ) 4 3 V Mains =30V I p [A] I Gmax T t p whereas V G [V]= Gate voltage of the triac I G [A]= Max. gate current I P [A] = Average gate current requirement t P [s] = Ignition pulse width T[s] = Duration (of mains frequency) I tot ( ma ) Figure 9. 4 (8)

5 TEA04/ TEA4 Absolute Maximum Ratings Reference point Pin Parameters Symbol Value Unit Current consumption Pin 4 I S 30 ma t 0 s i s 0 Sync. current Pin 7 t 0 s I Sync i Sync 40 Comparator input current Pin I I ma Input voltages Pin,4, Pin Power dissipation T amb = 4 C T amb = 00 C V I V I V S 0. P tot 400 Junction temperature T j C Ambient temperature range T amb 0 to 00 C Storage temperature range T stg 40 to C ma V mw Thermal Resistance Parameters Symbol Maximum Unit Junction ambient R thja 00 K/W Electrical Characteristics Supply voltage V S =. V, T amb = C, f = 0 Hz, reference point Pin, unless otherwise specified Parameters Test Conditions / Pins Symbol Min Typ Max Unit Supply voltage limitation I 4 = ma Pin 4 V S V Current consumption Pos. half, cycle Pin 4 I S ma Zero cross over (Pin open) Pin 4 I S neg. half cycle Pin 4 I S.8 Synchronization Pin 7 Voltage limitation ±I 7 = ma V I.0.8 V Synchronization current I Sync 0. ma Zero cross detection I Sync Comparator, figure Input zero voltage Pin, V 0 0 mv Input quiescent current Pin I B Common mode input range Pin, V IC (V S.) V (8)

6 TEA04/ TEA4 Parameters Test Conditions / Pins Ramp generator, figures 3, 4 Pin Symbol Period TEA04 T 40 ms TEA4 80 Step number n Initial voltage V..4. V Final voltage V V Internal reference. V S.% 47.%. V Temperature coefficient of internal reference Pulse amplifier Pin Min Typ Max Unit TC Ref. mv/k Output pulse current V G. V I O 0 00 ma Output pulse width V Sync = 30 V, s R = 0 k t 0 t t 33 0 Applications 9 4 D N4007 L 390 k/ 0. W R (R sync ) R k/ W Load kw Ramp generator TEA ms TEA 4 80 ms Sync. logic 7 4 Supply C 00 F V TIC 3N MT V M = 30 V ~ NTC / M87 B value = 3474 R () = 0 k R (30) = 8 k R (0) = 0 k Protection Comparator 3 8 NC NC Pulse amplifier R G 8 MT N Figure 0. Simple temperature regulation with maximum proportional range (8)

7 TEA04/ TEA D N4007 L 390 k 0. W R (R sync ) R k W Load kw R 4 33 k R p R 0 k Ramp generator TEA04 40 ms TEA4 80 ms Sync. logic 7 4 Supply C 00 F V TIC 3N V M = 30 V ~ MT 0 k NTC / M87 B value = 3474 R () = 0 k R (30) = 8 k R (0) = 0 k R. k Protection Comparator NC 3 8 NC Pulse amplifier R G 8 MT N Figure. Temperature regulation with proportional range, 0 to 30 C/ 40 ms ramp cycle Dimensions in mm Package: DIP8 7 (8)

8 TEA04/ TEA4 Ozone Depleting Substances Policy Statement It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to. Meet all present and future national and international statutory requirements.. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (987) and its London Amendments (990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents.. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively. Class I and II ozone depleting substances in the Clean Air Act Amendments of 990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/40/EEC and 9/90/EEC Annex A, B and C (transitional substances) respectively. TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 33, D-740 Heilbronn, Germany Telephone: 49 (0) , Fax number: 49 (0) (8)