Manufacturing Test of 3D Stacked ICs: Problems, Solutions and Standards

Manufacturing Test of 3D Stacked ICs: Problems, Solutions and Standards Yassine Fkih Hakim Zimouche Giorgio Di Natale Marie-Lise Flottes Bruno Rouzeyre Pascal Vivet 27 June, 2013 MASTER 3D

3D-SICs Test Flow Die 1 Die 2 Pre-bond Test Pre-bond Test Stack 1+2 Mid-bond Test Die 3 Pre-bond Test Stack 1+2+3 Post-bond Test 2

Motivation TAM Handling stimuli and responses Circuit TAM Circuit Pre-bond test of TSVs 3

Outline Pre-bond test of TSVs Test Access Mechanism for 3D-SIC Conclusions 4

Electrical and Fault Models TSV Oxide Substrate Rup Rdown CTSV Pinhole Micro-void Rup R up Rdown CTSV Rdown Broken TSV Rup CTSV Rdown C TSV 5

Electrical and Fault Models TSV The delay of RC network is affected in presence of defects Oxide Substrate Rup Rdown CTSV Pinhole Micro-void Rup R up Rdown CTSV Rdown Broken TSV Rup CTSV Rdown C TSV 6

Solutions Direct measurements of the discharge time of RC network Ring Oscillator, whose frequency depends on the RC delay 7

Solution 1: direct measurement!! ST 65nm technology! 8

Solution 1: direct measurement Resolution: 5%!!! 9

Solution 2: Ring Oscillators cmd cmd Functional Logic TSV Test Controller Good TSV: F=530MHz Faulty TSV (C faultytsv =C goodtsv /2): F=770MHz 10

Solution 2: Ring Oscillators (integration with 1149.1) >*+(6)+1;' ;)=<(' 3 9 @ '! 3 9 @ ' "!<+=')&(<;;1,).&'' -+1A;-' Resetn Clk_ext 8"93' :)+,.);;<+='>9?' TSV_BIST_Start Ringo_number Count_enble Capture_clock Compare_min_max Resetn Clk_ringo!"#$%&'()*+,-.' ()/01.1,).' Comparison_result Ringo_index_max[4:0] Ringo_index_min[4:0] Min_count[11:0] Max_count[11:0] 3?9' 3B"' 3!93+' "+&,.*(6)+'7-()7-.' ' ' 234$'345' 3B%' 11

Solution 2: Ring Oscillators (integration with 1149.1) $#+% $#+%,-./)0% 1)2(% '3*)&&-.'/%!"#$%&'()*% $#+% 1)2(% '3*)&&-.'/% STMicroelectronics CMOS 65nm 10µm diameter, 80µm depth, 50µm x 40µm pitch Wide IO interface (6*46 TSVs) Ring Oscillator designed as a macro cell, integrated within the TSVs matrix 12

Comparison Direct measurements of the discharge time of RC network More sensitive to variability Faster Ring Oscillator, whose frequency depends on the RC delay More robust Slower 13

Outline Pre-bond test of TSVs Test Access Mechanism for 3D-SIC Conclusions 14

Test Infrastructures and Standards Wrappers and Test Access Mechanisms (TAMs) to test and debug modules within the system Standards follow technologies Standard System Module 1149.1 PCB Chip 1500 SoC Core P1687 SoCs Cores + IPs P1838 3D-SIC Die 15

Automatic Die Detection (extension applicable to 1149.1 and 1500) Vdd 0 1 CUT Gnd 16

Automatic Die Detection (extension applicable to 1149.1 and 1500) Vdd 0 1 CUT Gnd 17

Automatic Die Detection (extension applicable to 1149.1 and 1500) Vdd 0 1 CUT Gnd Vdd 0 1 CUT Gnd 18

Automatic Die Detection (extension applicable to 1149.1 and 1500) Vdd 0 1 CUT Gnd Vdd 0 1 CUT Gnd Vdd 0 1 CUT Gnd 19

Extending P1687 Compared to 1149.1 (JTAG) and 1500, P1687 (IJTAG) networks are dynamic and variable in their configuration Segments can be added or subtracted as requirements change IJTAG standard is flexible from an architectural standpoint 20

3D DFT proposal with P1687 The stack and each die are compliant to JTAG and IJTAG Die detectors It allows pre-, mid- and post-bond tests Cooperation with Mentor Tessent 21

Conclusions 3D SIC Test: New problems (mainly: TSV pre-bond testing and Test Infrastructures) New solutions and standards (hopefully) are coming 22

Thank you!! 23