CO-DEVELOPMENT MANUFACTURING INNOVATION & SUPPORT Model-based system-on-chip design on Altera and Xilinx platforms Ronald Grootelaar, System Architect RJA.Grootelaar@3t.nl
Agenda 3T Company profile Technology Design process Tooling Gatsoradar tracking SoCsolution Conclusions www.3t.eu 24 November 2014 2
Company profile 3T: leading for more than 30 years Electronics & Embedded software 50 employees Offices in Enschede(HQ) and Eindhoven Co-development, Manufacturing, Innovation & Support Customer specific solutions, from idea to phase-out Analog/digital electronics, FPGA/SoC, Software www.3t.eu 24 November 2014 3
Partners for FPGA/SoC design Altera Design Service Network Partner Xilinx Alliance Program Partner MathWorks Connections Program Partner www.3t.eu 24 November 2014 4
Agenda 3T Company profile Technology Design process Tooling Gatsoradar tracking SoCsolution Conclusions www.3t.eu 24 November 2014 5
Technology FPGA benefits Field Programmable Gate Array Enormous capacity and performance Real-time / deterministic Parallel processing power (DSP, computing algorithms) Single chip Fast time-to-market (IP, reference designs) www.3t.eu 24 November 2014 6
Technology FPGA history 1985: Xilinx XC2000 1998: Xilinx Spartan / Virtex 2002: Xilinx Virtex-II Pro (PPC) 2010: Xilinx 7-series 2011: Xilinx SoC 2014: Xilinx UltraScale 4M LC 1984: Altera EP300 (EPLD) 1992: Altera Flex 8000 2000: Altera ARM-based Excalibur 2002: Altera Cyclone / Stratix 2007: Altera Arria series 2013: Altera SoC 2015: Altera 10-series 4M LE www.3t.eu 24 November 2014 7
Technology CPU benefits Easier programming Easier data handling (Real-time) Operating Systems Software protocol stacks Libraries, components, references www.3t.eu 24 November 2014 8
Technology TCM I-MEM CUSTOM INSTR IF TCM D-MEM FPGA soft-core solution I$ D$ INT CNTRL MMU MPU EXP CNTRL Debug Processor IP (HDL) JTAG DEBUG HW BP I & D TRCE TRCE PORT Altera NIOS II Xilinx MicroBlaze Performance ~300 DMIPS Hardware accelerators FPGA Your design here www.3t.eu 24 November 2014 9
Technology Soft-core drawbacks Less CPU performance than e.g. Cortex-A industry standard Increased FPGA resource utilization Decreased FPGA performance www.3t.eu 24 November 2014 10
Technology System on Chip (SoC) Altera and Xilinx adopt ARM Cortex-A industry standard Dual core ARM Cortex-A9 processing system 64-bit Quad core ARM Cortex-A53 next generation Microsemi(Actel) FPGA/Cortex-M3 SoC www.3t.eu 24 November 2014 11
Technology SoC benefits FPGA and CPU combined Increased reliability Higher flexibility Improved system performance Lower system cost Faster time-to-market www.3t.eu 24 November 2014 12
Technology Xilinx Zynq SoC Dual ARM Cortex-A9 1 GHz operation 2500 DMIPS / core Software SDK www.3t.eu 24 November 2014 13
Technology Altera SoC Dual ARM Cortex-A9 1 GHz operation 2500 DMIPS / core Embedded Design Suite (EDS) www.3t.eu 24 November 2014 14
Technology Xilinx vs Altera SoC Item Xilinx Zynq Altera SoC On-Chip RAM 256 kb 64 kb Boot Sequence Processor first Processor IP (HDL) Analog Mixed Signal (ADC) Yes No Altera NIOS Interconnect FPGA to ARM Xilinx MicroBlaze Processor first or FPGA first or simultaneous 4x 64 bit high performance 1x 128 bit high performance 2x 32 bit general purpose Interconnect ARM to FPGA 1x 128 bit high performance 2x 32 bit general purpose 1x 32 bit low latency Interconnect FPGA to SDRAM 4 read ports HPS interconnect 4 write ports Debug ARM FPGA cross trigger No Yes www.3t.eu 24 November 2014 15
Agenda 3T Company profile Technology Design process Tooling Gatsoradar tracking SoCsolution Conclusions www.3t.eu 24 November 2014 16
Design process V model Traditional model Criticized by Agile/Scrum fans Feedback in late stadium www.3t.eu 24 November 2014 17
Design process Model-based design Model is specification Multidisciplinary Continuous verification Code generation Co-simulation Tuning (quick iterations) System integrations www.3t.eu 24 November 2014 18
Agenda 3T Company profile Technology Design process Tooling Gatsoradar tracking SoCsolution Conclusions www.3t.eu 24 November 2014 19
Tooling MathWorks Model-based design Matlab/ Simulink Embedded coder / HDL coder Altera & Xilinx FPGA and SoCtarget Vision, DSP and control systems Focus on code generation (C/C++, HDL) 1million users http://www.mathworks.nl/matlabcentral/ www.3t.eu 24 November 2014 20
Tooling HDL Coder www.3t.eu 24 November 2014 21
Tooling HDL Co-Simulation www.3t.eu 24 November 2014 22
Tooling HDL coder notes Not as simple as just pressing the button HDL Coder Workflow Advisor Synthesis, MAP, timing analysis Pipelining, delay balancing Resource sharing Black boxing www.3t.eu 24 November 2014 23
Tooling www.3t.eu 24 November 2014 24
Tooling Xilinx Vivado www.3t.eu 24 November 2014 25
Tooling Altera Quartus II SoCfully integrated in QuartusII Configure and connect HPS in Qsys AXI and Avalon busses can connect together Eclipse based SoCEDS OpenCLSDK www.3t.eu 24 November 2014 26
Agenda 3T Company profile Technology Design process Tooling Gatso radar tracking SoC solution Conclusions www.3t.eu 24 November 2014 27
Radar tracking module High performance analog front-end for signal conditioning radar signals System on Module with Xilinx ZynqZ-7020 C/C++ code for radar tracking algorithms generated via Model-Based Design using MatLab and Simulink Digital Signal Processing in Zynq FPGA fabric ecos RTOS and bare-metal on ZynqARM cores Co-development / Manufacturing See: http://3t.nl/algemeen/soc/ (Bits&Chips#8 2014) www.3t.eu 24 November 2014 28
Radar tracking module Design overview System design - Golden Matlab model provided by customer Software design - Cortex-A9 in Asymmetric Multi Processing (AMP) - ecos RTOS and bare metal radar algorithms - Generated C code (Matlab) for radar algorithms Hardware design - Xilinx IP Integration (FFT) with Vivado - Custom IP Integration with Vivado -GbitEthernet UDP in hardware www.3t.eu 24 November 2014 29
Radar tracking module Vivado IP Integrator www.3t.eu 24 November 2014 30
Radar tracking module ZYNQ Processing System Configuration www.3t.eu 24 November 2014 31
Radar tracking module ZYNQ MIO Configuration www.3t.eu 24 November 2014 32
Radar tracking module Hardware / software interface Generate FPGA image (pre-loader / bootloader configures FPGA) Export hardware platform for SDK Generate BSP from hardware platform www.3t.eu 24 November 2014 33
Radar tracking module Software design RTOS for real-time requirements ecos available for System On Module (SOM) RTOS usage avoids rewriting Matlab algorithms Second CPU reserved exclusively for data processing www.3t.eu 24 November 2014 34
Altera Cyclone V SoC demo Visit the EBV-Altera booth #60 www.3t.eu 24 November 2014 35
Conclusions SoC benefits higher performance Flexibility lower costs faster time-to-market Multidisciplinary Model-based design highly suitable for SoC design High-level SoC design tooling under development StaywithyourFPGA vendor www.3t.eu 24 November 2014 36
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