.35V DDR3 SDRAM SODIMM MT6KSF5664HZ GB MT6KSF564HZ 4GB GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM Features Features DDR3L functionality and operations supported as defined in the component data sheet 04-pin, small outline dual in-line memory module (SODIMM) Fast data transfer rates: PC3-800, PC3-0600, PC3-8500, or PC3-6400 GB (56 Meg x 64), 4GB (5 Meg x 64) V DD =.35V (.83V to.45v) V DD =.5V (.45V to.575v) Backward compatible to V DD = +.5V ±0.075V V DDSPD = +3.0V to +3.6V Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Dual rank On-board I C temperature sensor with integrated serial presence-detect (SPD) EEPROM Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Selectable BC4 or BL8 on-the-fly (OTF) Gold edge contacts Halogen-free Fly-by topology Terminated control, command, and address bus Figure : 04-Pin SODIMM (MO-68 R/C F) Module height: 30.0mm (.8in) Options Marking Operating temperature Commercial (0 C T A +70 C) None Package 40-pin DIMM (halogen-free) Z Frequency/CAS latency.5ns @ CL = (DDR3-600) -G6.5ns @ CL = 9 (DDR3-333) -G4.87ns @ CL = 7 (DDR3-066) -G.87ns @ CL = 8 (DDR3-066) -G0.5ns @ CL = 5 (DDR3-800) -80C.5ns @ CL = 6 (DDR3-800) -80B Note:. Not recommended for new designs. Table : Key Timing Parameters Speed Grade Industry Nomenclature Data Rate (MT/s) CL = CL = 0 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5 -G6 PC3-800 600 333 333 066 066 800 667 3.5 3.5 48.5 -G4 PC3-0600 333 333 066 066 800 667 3.5 3.5 49.5 -G PC3-8500 066 066 800 667 3.5 3.5 50.65 -G0 PC3-8500 066 800 667 5 5 5.5-80B PC3-6400 800 667 5 5 5.5 t RCD (ns) t RP (ns) t RC (ns) PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 009 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.
GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM Features Table : Addressing Parameter GB 4GB Refresh count 8K 8K Row address 6K A[3:0] 3K A[4:0] Device bank address 8 BA[:0] 8 BA[:0] Device configuration Gb (8 Meg x 8) Gb (56 Meg x 8) Column address K A[9:0] K A[9:0] Module rank address S#[:0] S#[:0] Table 3: Part Numbers and Timing Parameters GB Modules Base device: MT4K8M8HX, Gb.35V DDR3 SDRAM Part Number Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MT6KSF5664HZ-G6 GB 56 Meg x 64.8 GB/s.5ns/600 MT/s -- MT6KSF5664HZ-G4 GB 56 Meg x 64 0.6 GB/s.5ns/333 MT/s 9-9-9 MT6KSF5664HZ-G GB 56 Meg x 64 8.5 GB/s.87ns/066 MT/s 7-7-7 MT6KSF5664HZ-G0 GB 56 Meg x 64 8.5 GB/s.87ns/066 MT/s 8-8-8 Table 4: Part Numbers and Timing Parameters 4GB Modules Base device: MT4K56M8HX, Gb.35V DDR3 SDRAM Part Number Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MT6KSF564HZ-G6 4GB 5 Meg x 64.8 GB/s.5ns/600 MT/s -- MT6KSF564HZ-G4 4GB 5 Meg x 64 0.6 GB/s.5ns/333 MT/s 9-9-9 MT6KSF564HZ-G 4GB 5 Meg x 64 8.5 GB/s.87ns/066 MT/s 7-7-7 MT6KSF564HZ-G0 4GB 5 Meg x 64 8.5 GB/s.87ns/066 MT/s 8-8-8 Notes:. The data sheet for the base device can be found on Micron s Web site.. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT6KSF564HZ-GD. PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM Pin Assignments Pin Assignments Table 5: Pin Assignments 04-Pin DDR3 SODIMM Front 04-Pin DDR3 SODIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol V REF 53 9 05 V DD 57 4 54 06 V DD 58 46 3 55 07 A0 59 43 4 4 56 8 08 BA 60 47 5 0 57 4 09 BA0 6 6 5 58 9 0 RAS# 6 7 59 5 V DD 63 48 8 60 V DD 64 5 9 6 3 WE# 65 49 0 S0# 6 3# 4 S0# 66 53 DM0 63 DM3 5 CAS# 67 S0 64 3 6 ODT0 68 3 65 7 V DD 69 S6# 4 66 8 V DD 70 DM6 5 67 6 9 A3 7 S6 6 6 68 30 0 ODT 7 7 3 69 7 S# 73 8 7 70 3 NC 74 54 9 7 3 V DD 75 50 0 7 4 V DD 76 55 8 73 CKE0 5 NC 77 5 74 CKE 6 V REFCA 78 3 9 75 V DD 7 79 4 3 76 V DD 8 80 60 5 77 NC 9 3 8 56 6 78 NF 30 36 8 6 7 S# 79 BA 3 33 83 57 8 DM 80 NF/A4 3 37 84 9 S 8 V DD 33 85 30 RESET# 8 V DD 34 86 S7# 3 83 A 35 S4# 87 DM7 3 84 A 36 DM4 88 S7 33 0 85 A9 37 S4 89 34 4 86 A7 38 90 35 87 V DD 39 9 58 36 5 88 V DD 40 38 9 6 37 89 A8 4 34 93 59 38 90 A6 4 39 94 63 39 6 9 A5 43 35 95 40 0 9 A4 44 96 4 7 93 V DD 45 97 SA0 4 94 V DD 46 44 98 EVENT# 43 95 A3 47 40 99 V DDSPD 44 96 A 48 45 00 SDA 45 S# 97 A 49 4 0 SA 46 DM 98 A0 50 0 SCL 47 S 99 V DD 5 03 V TT 48 00 V DD 5 S5# 04 V TT 49 0 CK0 53 DM5 50 0 CK 54 S5 5 8 03 CK0# 55 5 3 04 CK# 56 PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 3 009 Micron Technology, Inc. All rights reserved.
Pin Descriptions Table 6: Pin Descriptions Symbol Type Description The pin description table below is a comprehensive list of all possible pins for all DDR3 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A0) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A0 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A0 LOW, bank selected by BAx) or all banks (A0 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments table for density-specific addressing information. BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR, MR, or MR3) is loaded during the LOAD MODE command. CKx, CKx# Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the and S pins. ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to the following pins:, S, S#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input (LVCMOS) Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed. Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder. SAx Input Serial address inputs: Used to configure the temperature sensor/spd EEPROM address range on the I C bus. SCL Input Serial clock for temperature sensor/spd EEPROM: Used to synchronize communication to and from the temperature sensor/spd EEPROM on the I C bus. CBx I/O Check bits: Used for system error detection and correction. x I/O Data input/output: Bidirectional data bus. Sx, Sx# I/O GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM Pin Descriptions Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; input with write data; center-aligned with write data. PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 4 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM Pin Descriptions Table 6: Pin Descriptions (Continued) Symbol Type Description SDA I/O Serial data: Used to transfer addresses and data into and out of the temperature sensor/spd EEPROM on the I C bus. TSx, TSx# Err_Out# EVENT# Output Output (open drain) Output (open drain) Redundant data strobe (x8 devices only): TS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When TS is enabled, DM is disabled and TS and TS# provide termination resistance; otherwise, TS# are no function. Parity error output: Parity error found on the command and address bus. Temperature event: The EVENT# pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded. V DD Supply Power supply:.35v (.83.45V) backward-compatible to.5v (.45.575V). The component V DD and V D are connected to the module V DD. V DDSPD Supply Temperature sensor/spd EEPROM power supply: 3.0 3.6V. V REFCA Supply Reference voltage: Control, command, and address V DD /. V REF Supply Reference voltage:, DM V DD /. Supply Ground. V TT Supply Termination voltage: Used for control, command, and address V DD /. NC No connect: These pins are not connected on the module. NF No function: These pins are connected within the module, but provide no functionality. PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 5 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM Map Map Table 7: Component-to-Module Map (Front) Component Reference Number Component Module Module Pin Number Component Reference Number Component Module Module Pin Number U 0 5 U 0 8 5 5 6 4 3 7 9 53 3 0 5 3 6 39 4 6 6 4 50 5 4 4 5 0 40 6 7 8 6 3 5 7 7 7 7 4 U5 0 4 57 U6 0 58 9 45 48 6 8 43 59 59 93 3 40 47 3 56 8 4 46 58 4 6 9 5 44 46 5 60 80 6 47 60 6 63 94 7 4 49 7 57 83 U7 0 3 4 U8 0 6 67 0 33 9 58 8 7 69 3 35 3 4 57 4 9 3 4 30 68 5 5 36 5 8 56 6 6 3 70 7 4 34 7 5 59 U9 0 34 4 U0 0 53 66 37 3 50 75 35 43 48 63 3 3 9 3 5 77 4 38 40 4 49 65 5 36 30 5 55 76 6 39 4 6 5 64 7 33 3 7 54 74 PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 6 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM Map Table 8: Component-to-Module Map (Back) Component Reference Number Component Module Module Pin Number Component Reference Number Component Module Module Pin Number U 0 6 8 U 0 45 48 58 9 4 57 56 8 40 47 3 59 93 3 43 59 4 57 83 4 4 49 5 63 94 5 47 60 6 60 80 6 44 46 7 6 9 7 46 58 U5 0 4 U6 0 5 6 8 5 5 6 39 0 5 3 9 53 3 3 7 4 7 4 4 7 5 3 5 5 7 8 6 0 40 6 4 4 7 50 7 6 6 U7 0 50 75 U8 0 37 3 53 66 34 4 5 77 3 9 3 48 63 3 35 43 4 54 74 4 33 3 5 5 64 5 39 4 6 55 76 6 36 30 7 49 65 7 38 40 U9 0 9 58 U0 0 0 33 6 67 3 4 4 57 35 3 7 69 3 8 4 5 59 4 4 34 5 3 70 5 6 8 56 6 5 36 7 30 68 7 9 3 PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 7 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM Functional Block Diagram Functional Block Diagram Figure : Functional Block Diagram S# S0# S0# S0 DM0 S4# S4 DM4 0 3 4 5 6 7 S# S DM 8 9 0 3 4 5 S# S DM 6 7 8 9 0 3 S3# S3 DM3 4 5 6 7 8 9 30 3 DM CS# S# U DM CS# S# U7 DM CS# S# U DM CS# S# U9 DM CS# S# DM CS# S# DM CS# S# U6 DM CS# S# U0 DM CS# S# U5 DM CS# S# U8 S5# S5 DM5 S6# S6 DM6 3 33 34 35 36 37 38 39 40 4 4 43 44 45 46 47 48 49 50 5 5 53 54 55 S7# S7 DM7 56 57 58 59 60 6 6 63 U9 U U8 DM CS# S# DM CS# S# U7 U5 DM CS# S# DM CS# S# U U0 DM CS# S# DM CS# S# U6 Rank 0 = U, U, U7, U9, U, U, U7, U9 Rank = U5, U6, U8, U0, U5, U6, U8, U0 BA[:0] A[4/3:0] RAS# CAS# WE# CKE0 CKE ODT0 ODT RESET# BA[:0]: DDR3 SDRAM A[4/3:0] DDR3 SDRAM RAS#: DDR3 SDRAM CAS#: DDR3 SDRAM WE#: DDR3 SDRAM CKE0: Rank 0 CKE: Rank ODT0: Rank 0 ODT: Rank RST#: DDR3 SDRAM SCL U3 Temperature sensor/ SPD EEPROM EVT A0 A A SA0 SA V EVENT# SS V DDSPD V DD SDA CK0 Rank 0 CK0# CK Rank CK# Temperature sensor/spd EEPROM DDR3 SDRAM Clock, control, command, and address line terminations: CKE[:0], A[4/3:0], RAS#, CAS#, WE#, ODT[:0], BA[:0], S#[:0] DDR3 SDRAM DDR3 SDRAM V TT V TT V REFCA V REF Control, command, and address termination DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM CK CK# V DD Note:. The ball on each DDR3 component is connected to an external 40Ω ±% resistor that is tied to ground. It is used for the calibration of the component s ODT and output driver. PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 8 009 Micron Technology, Inc. All rights reserved.
General Description GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM General Description DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules use DDR architecture to achieve high-speed operation. DDR3 architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR3 modules use two sets of differential signals: S, S# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. Fly-By Topology DDR3 modules use faster clock speeds than earlier DDR technologies, making signal quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and S signals can be easily accounted for by using the write-leveling feature of DDR3. Serial Presence-Detect EEPROM Operation DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 56-byte EEPROM. The first 8 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Modules." These bytes identify module-specific timing parameters, configuration information, and physical attributes. The remaining 8 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I C bus using the DIMM s SCL (clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to, permanently disabling hardware write protection. For further information refer to Micron technical note TN-04-4, "Memory Module Serial Presence-Detect." PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 9 009 Micron Technology, Inc. All rights reserved.
Electrical Specifications Table 9: Absolute Maximum Ratings GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Symbol Parameter Min Max Units V DD V DD supply voltage relative to 0.4.975 V V IN, V OUT Voltage on any pin relative to 0.4.975 V Table 0: Operating Conditions Symbol Parameter Min Nom Max Units Notes V DD V DD supply voltage.83.35.45 V V REFCA(DC) Input reference voltage command/address bus.45.5.575 V 0.49 V DD 0.5 V DD 0.5 V DD V V REF(DC) I/O reference voltage bus 0.49 V DD 0.5 V DD 0.5 V DD V I VTT Termination reference current from V TT 600 600 ma V TT I I I OZ I VREF Termination reference voltage (DC) command/address bus Input leakage current; Any input 0V V IN V DD ; V REF input 0V V IN 0.95V (All other pins not under test = 0V) Output leakage current; 0V V OUT V DD ; and ODT are disabled; ODT is HIGH Address inputs, RAS#, CAS#, WE#, BA S#, CKE, ODT, CK, CK# 0.49 V DD - 0mV 0.5 0.5 V DD + V DD 0mV 3 0 3 µa 6 0 6 DM 4 0 4, S, S# V REF supply leakage current; V REF = V DD/ or V REFCA = V DD/ (All other pins not under test = 0V) 0 0 0 µa 6 0 6 µa V T A Module ambient operating temperature 0 70 C 3 T C DDR3 SDRAM component case operating temperature 0 95 C 3, 4, 5 Notes:. Module is backward-compatible with.5v operation. Refer to device specification for details and operation guidance.. V TT termination voltage in excess of the stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins. 3. T A and T C are simultaneous requirements. PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 0 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM Electrical Specifications 4. For further information, refer to technical note TN-00-08: Thermal Applications, available on Micron s Web site. 5. The refresh rate is required to double when 85 C < T C 95 C. PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM DRAM Operating Conditions DRAM Operating Conditions Recommended AC operating conditions are given in the DDR3 component data sheets. Component specifications are available on Micron s web site. Module speed grades correlate with component speed grades, as shown below. Table : Module and Component Speed Grades DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Component Speed Grade -G -093 -G9-07 -G6-5 -G4-5E -G -87E -G0-87 -80C -5E -80B -5 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM I DD Specifications I DD Specifications Table : DDR3 I DD Specifications and Conditions GB (Die Revision F) Values are for the MT4K8M8 DDR3 SDRAM only and are computed from values specified in the Gb (8 Meg x 8) component data sheet Parameter Symbol 600 333 066 Units Operating current 0: One bank ACTIVATE-to-PRE- CHARGE Operating current : One bank ACTIVATE-to-READto-PRECHARGE I DD0 TBD 840 744 ma I DD TBD 960 864 ma Precharge power-down current: Slow exit I DDP0 TBD 60 8 ma Precharge power-down current: Fast exit I DDP TBD 480 400 ma Precharge quiet standby current I DDQ TBD 880 70 ma Precharge standby current I DDN TBD 880 70 ma Precharge standby ODT current I DDNT TBD 680 584 ma Active power-down current I DD3P TBD 59 480 ma Active standby current I DD3N TBD 960 800 ma Burst read operating current I DD4R TBD 40 04 ma Burst write operating current I DD4W TBD 40 04 ma Refresh current I DD5B TBD 540 464 ma Self refresh temperature current: MAX T C = 85 C I DD6 TBD 96 96 ma Self refresh temperature current (SRT-enabled): MAX T C = 95 C I DD6ET TBD 44 44 ma All banks interleaved read current I DD7 TBD 960 384 ma Reset current I DD8 TBD 9 60 ma Notes:. One module rank in the active I DD, the other rank in I DDP0.. All ranks in this I DD condition. Table 3: DDR3 I DD Specifications and Conditions GB (Die Revision G) Values are for the MT4K8M8 DDR3 SDRAM only and are computed from values specified in the Gb (8 Meg x 8) component data sheet Parameter Symbol 600 333 066 Units Operating current 0: One bank ACTIVATE-to-PRE- CHARGE Operating current : One bank ACTIVATE-to-READto-PRECHARGE I DD0 696 656 66 ma I DD 86 776 736 ma Precharge power-down current: Slow exit I DDP0 9 9 9 ma Precharge power-down current: Fast exit I DDP 560 480 400 ma Precharge quiet standby current I DDQ 70 70 640 ma Precharge standby current I DDN 70 70 640 ma Precharge standby ODT current I DDNT 536 496 496 ma Active power-down current I DD3P 560 560 480 ma PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 3 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM I DD Specifications Table 3: DDR3 I DD Specifications and Conditions GB (Die Revision G) (Continued) Values are for the MT4K8M8 DDR3 SDRAM only and are computed from values specified in the Gb (8 Meg x 8) component data sheet Parameter Symbol 600 333 066 Units Active standby current I DD3N 70 70 640 ma Burst read operating current I DD4R 56 36 976 ma Burst write operating current I DD4W 96 76 06 ma Refresh current I DD5B 496 456 46 ma Self refresh temperature current: MAX T C = 85 C I DD6 8 8 8 ma Self refresh temperature current (SRT-enabled): MAX T C = 95 C I DD6ET 60 60 60 ma All banks interleaved read current I DD7 096 056 696 ma Reset current I DD8 4 4 4 ma Notes:. One module rank in the active I DD, the other rank in I DDP0.. All ranks in this I DD condition. Table 4: DDR3 I DD Specifications and Conditions 4GB (Die Revision D) Values are for the MT4K56M8 DDR3 SDRAM only and are computed from values specified in the Gb (56 Meg x 8) component data sheet Parameter Symbol 600 333 066 Units Operating current 0: One bank ACTIVATE-to-PRE- CHARGE Operating current : One bank ACTIVATE-to-READto-PRECHARGE I DD0 TBD 776 696 ma I DD TBD 896 856 ma Precharge power-down current: Slow exit I DDP0 TBD 9 9 ma Precharge power-down current: Fast exit I DDP TBD 480 400 ma Precharge quiet standby current I DDQ TBD 560 480 ma Precharge standby current I DDN TBD 59 5 ma Precharge standby ODT current I DDNT TBD 456 46 ma Active power-down current I DD3P TBD 560 480 ma Active standby current I DD3N TBD 640 560 ma Burst read operating current I DD4R TBD 376 6 ma Burst write operating current I DD4W TBD 46 56 ma Refresh current I DD5B TBD 696 66 ma Self refresh temperature current: MAX T C = 85 C I DD6 TBD 9 9 ma Self refresh temperature current (SRT-enabled): MAX T C = 95 C I DD6ET TBD 40 40 ma All banks interleaved read current I DD7 TBD 376 776 ma Reset current I DD8 TBD 4 4 ma Notes:. One module rank in the active I DD, the other rank in I DDP0.. All ranks in this I DD condition. PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 4 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM I DD Specifications Table 5: DDR3 I DD Specifications and Conditions 4GB (Die Revision H) Values are for the MT4K56M8 DDR3 SDRAM only and are computed from values specified in the Gb (56 Meg x 8) component data sheet Parameter Symbol 600 333 066 Units Operating current 0: One bank ACTIVATE-to-PRE- CHARGE Operating current : One bank ACTIVATE-to-READto-PRECHARGE I DD0 696 656 66 ma I DD 856 86 776 ma Precharge power-down current: Slow exit I DDP0 9 9 9 ma Precharge power-down current: Fast exit I DDP 59 5 43 ma Precharge quiet standby current I DDQ 67 59 5 ma Precharge standby current I DDN 688 608 544 ma Precharge standby ODT current I DDNT 5 47 43 ma Active power-down current I DD3P 75 67 59 ma Active standby current I DD3N 83 75 67 ma Burst read operating current I DD4R 336 6 096 ma Burst write operating current I DD4W 336 6 096 ma Refresh current I DD5B 66 576 536 ma Self refresh temperature current: MAX T C = 85 C I DD6 9 9 9 ma Self refresh temperature current (SRT-enabled): MAX T C = 95 C I DD6ET 40 40 40 ma All banks interleaved read current I DD7 36 06 896 ma Reset current I DD8 4 4 4 ma Notes:. One module rank in the active I DD, the other rank in I DDP0.. All ranks in this I DD condition. Table 6: DDR3 I DD Specifications and Conditions 4GB (Die Revision M) Values are for the MT4K56M8 DDR3 SDRAM only and are computed from values specified in the Gb (56 Meg x 8) component data sheet Parameter Symbol 600 333 066 Units Operating current 0: One bank ACTIVATE-to-PRE- CHARGE Operating current : One bank ACTIVATE-to-READto-PRECHARGE I DD0 576 536 496 ma I DD 696 656 66 ma Precharge power-down current: Slow exit I DDP0 9 9 9 ma Precharge power-down current: Fast exit I DDP 58 448 368 ma Precharge quiet standby current I DDQ 58 448 368 ma Precharge standby current I DDN 560 480 400 ma Precharge standby ODT current I DDNT 46 376 336 ma Active power-down current I DD3P 75 67 59 ma Active standby current I DD3N 83 75 67 ma Burst read operating current I DD4R 6 096 976 ma PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 5 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM I DD Specifications Table 6: DDR3 I DD Specifications and Conditions 4GB (Die Revision M) (Continued) Values are for the MT4K56M8 DDR3 SDRAM only and are computed from values specified in the Gb (56 Meg x 8) component data sheet Parameter Symbol 600 333 066 Units Burst write operating current I DD4W 096 976 856 ma Refresh current I DD5B 66 576 536 ma Self refresh temperature current: MAX T C = 85 C I DD6 9 9 9 ma Self refresh temperature current (SRT-enabled): MAX T C = 95 C I DD6ET 40 40 40 ma All banks interleaved read current I DD7 856 736 66 ma Reset current I DD8 4 4 4 ma Notes:. One module rank in the active I DD, the other rank in I DDP0.. All ranks in this I DD condition. PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 6 009 Micron Technology, Inc. All rights reserved.
Temperature Sensor with Serial Presence-Detect EEPROM Serial Presence-Detect GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM Temperature Sensor with Serial Presence-Detect EEPROM The temperature sensor continuously monitors the module's temperature and can be read back at any time over the I C bus shared with the SPD EEPROM. Refer to JEDEC standard No. -C page 4.7-, "Definition of the TSE00av, Serial Presence Detect with Temperature Sensor." For the latest SPD data, refer to Micron's SPD page: www.micron.com/spd. Table 7: Temperature Sensor with SPD EEPROM Operating Conditions Parameter/Condition Symbol Min Max Units Supply voltage V DDSPD 3.0 3.6 V Supply current: V DD = 3.3V I DD.0 ma Input high voltage: Logic ; SCL, SDA V IH V DDSPD x 0.7 V DDSPD + V Input low voltage: Logic 0; SCL, SDA V IL 0.5 V DDSPD x 0.3 V Output low voltage: I OUT =.ma V OL 0.4 V Input current I IN 5.0 5.0 µa Temperature sensing range 40 5 C Temperature sensor accuracy (class B).0.0 C Table 8: Temperature Sensor and SPD EEPROM Serial Interface Timing Parameter/Condition Symbol Min Max Units Time bus must be free before a new transition can start t BUF 4.7 µs SDA fall time t F 0 300 ns SDA rise time t R 000 ns Data hold time t HD:DAT 00 900 ns Start condition hold time t H:STA 4.0 µs Clock HIGH period t HIGH 4.0 50 µs Clock LOW period t LOW 4.7 µs SCL clock frequency t SCL 0 00 khz Data setup time t SU:DAT 50 ns Start condition setup time t SU:STA 4.7 µs Stop condition setup time t SU:STO 4.0 µs PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 7 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM Temperature Sensor with Serial Presence-Detect EEPROM EVENT# Pin The temperature sensor also adds the EVENT# pin (open-drain). Not used by the SPD EEPROM, EVENT# is a temperature sensor output used to flag critical events that can be set up in the sensor s configuration register. EVENT# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. Event thresholds are programmed in the 0x0 register using a hysteresis. The alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boundary register, respectively. When the alarm window is enabled, EVENT# will trigger whenever the temperature is outside the MIN or MAX values set by the user. The interrupt mode enables software to reset EVENT# after a critical temperature threshold has been detected. Threshold points are set in the configuration register by the user. This mode triggers the critical temperature limit and both the MIN and MAX of the temperature window. The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by the user and returns to the logic HIGH state only when the temperature falls below the programmed thresholds. Critical temperature mode triggers EVENT# only when the temperature has exceeded the programmed critical trip point. When the critical trip point has been reached, the temperature sensor goes into comparator mode, and the critical EVENT# cannot be cleared through software. PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 8 009 Micron Technology, Inc. All rights reserved.
GB, 4GB (x64, DR) 04-Pin.35V DDR3 SODIMM Module Dimensions Module Dimensions Figure 3: 04-Pin DDR3 SODIMM Front view 67.75 (.667) 67.45 (.656) 3.8 (0.5) MAX.0 (0.079) R (X) U U U3 U5 U6.8 (0.07) (X) U7 U8 U9 U0 0.0 (0.787) 30.5 (.87) 9.85 (.75) 6.0 (0.36).0 (0.079) Pin.0 (0.039) 63.6 (.504) 0.45 (0.08) Back view 0.60 (0.04) Pin 03. (0.043) 0.9 (0.035) U U U5 U6 U7 U8 U9 U0.55 (0.) Pin 04 3.0 (0.) Pin 39.0 (.535).0 (0.87) 4.8 (0.976) 4.0 (0.57) Notes:. All dimensions are in millimeters (inches); MAX/MIN or typical () where noted.. The dimensional diagram is for reference only. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 08-368-3900 www.micron.com/productsupport Customer Comment Line: 800-93-499 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef83ba03 ksf6c56_5x64hz Rev. D 4/3 EN 9 009 Micron Technology, Inc. All rights reserved.