Data Rate (MT/s) CL = 15 CL = 13 CL = 14

Transcription

1 DDR4 SDRAM RDIMM MTA36ASFG7PZ 6GB 6GB (x7, ECC, DR) 88-Pin DDR4 RDIMM Features Features DDR4 functionality and operations supported as defined in the component data sheet 88-pin, registered dual in-line memory module (RDIMM) Fast data transfer rates: PC4-400 or PC4-33 6GB ( Gig x 7) V DD =.0V (NOM) V PP =.5V (NOM) V DDSPD =.5V (NOM) Supports ECC error detection and correction Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Low-power auto self refresh (LPASR) On-die V REF generation and calibration Dual-rank On-board I C temperature sensor with integrated serial presence-detect (SPD) EEPROM 6 internal banks; 4 groups of 4 banks each Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) Selectable BC4 or BL8 on-the-fly (OTF) Gold edge contacts Halogen-free Fly-by topology Terminated control, command, and address bus Figure : 88-Pin RDIMM (MO-309, R/C-B) Module height: 3.5mm (.3in) Options Marking Operating temperature Commercial (0 C T OPER 95 C) None Package 88-pin DIMM (halogen-free) Z Frequency/CAS latency CL = 7(DDR4-400) -G3 CL = 5 (DDR4-33) -G Table : Key Timing Parameters Speed Grade Industry Nomenclature CL = 0, CL = 9 CL = 8 CL = 7 CL = 6 Data Rate (MT/s) CL = 5 CL = 4 CL = 3 CL = CL = CL = 0 CL = 9 -G6 PC G4 PC G3 PC G PC t RCD (ns) t RP (ns) t RC (ns) Products and specifications discussed herein are subject to change by Micron without notice.

2 Features Table : Addressing Parameter Row address Column address Device bank group address Device bank address per group Device configuration Module rank address 6GB 64K A[5:0] K A[9:0] 4 BG[:0] 4 BA[:0] 4Gb ( Gig x 4), 6 banks CS_n[:0] Table 3: Part s and Timing Parameters 6GB Modules Base device: MT40AG4, 4Gb DDR4 SDRAM Part Module Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL- t RCD- t RP) MTA36ASFG7PZ-G3 6GB Gig x 7 9. GB/s 0.83ns/400 MT/s MTA36ASFG7PZ-G 6GB Gig x GB/s 0.93ns/33 MT/s Notes:. The data sheet for the base device can be found on micron.com.. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MTA36ASFG7PZ-G3A.

3 Pin Assignments Pin Assignments The pin assignment table below is a comprehensive list of all possible pin assignments for DDR4 RDIMM modules. See the Functional Block Diagram for pins specific to this module. Table 4: Pin Assignments 88-Pin DDR4 RDIMM Front 88-Pin DDR4 RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol NC 37 V SS 73 V DD 09 V SS 45 NC V DD 53 4 V SS CK0_t 0 S4_t/ TS4_t V SS 75 CK0_c S4_c/ TS4_c 4 V SS 40 S_t/ TS_t S_c/ TS_c 46 V REFCA 8 V SS 8 CK_t 54 V SS 47 V SS CK_c 55 S5_c 76 V DD V SS V SS 0 V DD 56 S5_t 77 V TT V SS 85 S3_c V TT 57 V SS 6 V SS 4 V SS 78 EVENT_n 4 V SS S3_t PARITY S9_t/ TS9_t 8 S09_c/ TS9_c A V SS 87 V SS 3 V DD 59 V SS 44 V SS 80 V DD 6 V SS 5 S0_c BA V SS BA S0_t 89 V SS 5 A0/ AP V SS 8 RAS_n/ A6 6 V SS 8 V SS 54 V SS V DD 6 53 V SS 47 CB4 83 V DD V SS 7 NC 63 V SS 48 V SS 84 CS0_n 0 V SS 56 V SS 9 CB5 8 WE_n/ A4 3 V SS 49 CB0 85 V DD S5_t/ TS5_t 4 50 V SS 86 CAS_n/ A5 5 V SS 5 S7_t/ TS7_t S7_c/ TS7_c 7 V SS 53 V SS 89 CS_n/ NC 8 S0_t/ TS0_t 9 S0_c/ TS0_c S5_c/ TS5_c V SS 9 V DD 65 V SS 58 V SS 94 CB 30 NC 66 S6_c 87 ODT0 3 V SS V SS 3 V DD 67 S6_t 88 V DD V SS 96 S8_c 3 A3 68 V SS 5 V SS S8_t 33 V DD CB6 90 V DD V SS 98 V SS 34 A7 70 V SS 55 V SS 9 ODT/ NC 7 V SS 63 S_c 99 CB7 35 NC/ C V SS 56 CB 9 V DD S_t 00 V SS 36 V DD 7 V SS 4 57 V SS 93 CS_n/ 9 V SS 65 V SS 0 CB3 37 CS3_n/ 73 6 C0 C, NC V SS 58 RESET_n 94 V SS V SS 38 SA 74 V SS V DD V SS 67 V SS 03 CKE/ 39 V SS NC 4 V SS 60 CKE0 96 V SS 3 S6_t/ TS6_t V DD V SS 3

4 Pin Assignments Table 4: Pin Assignments (Continued) 88-Pin DDR4 RDIMM Front 88-Pin DDR4 RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol V DD S6_c/ TS6_c 69 V SS 05 NC 4 V SS 77 S7_c 6 V SS 6 ACT_n 98 V SS 34 V SS V DD S7_t BG0 99 S3_t/ T3_t 8 V SS 64 V DD 00 S3_c/ TS3_c 9 S_t/ TS_t 30 S_c/ TS_c V SS 07 BG 43 V SS 79 V SS 36 V SS ALERT_n 44 S4_c A/BC_n 0 V SS V SS 09 V DD 45 S4_t 8 V SS 66 A V SS 74 S_c 0 A 46 V SS V SS 67 V DD 03 V SS 39 SA0 75 S_t A V SS 3 68 A SA 76 V SS V DD 48 V SS 84 V DDSPD 33 V SS 69 A6 05 V SS 4 SCL A SDA V DD V PP 78 V SS 4 A4 50 V SS 86 V PP 35 V SS 7 A3 07 V SS 43 V PP V DD V PP A NC 80 V SS 6 A 5 V SS 88 V PP 4

5 Pin Descriptions Table 5: Pin Descriptions The pin description table below is a comprehensive list of all possible pins for DDR4 modules. All pins listed may not be supported on this module. See Functional Block Diagram for pins specific to this module. Symbol Type Description Ax Input Address inputs: Provide the row address for ACTIVATE commands and the column address for READ/WRITE commands in order to select one location out of the memory array in the respective bank (A0/AP, A/BC_n, WE_n/A4, CAS_n/A5, and RAS_n/A6 have additional functions; see individual entries in this table). The address inputs also provide the op-code during the MODE REGISTER SET command. A7 is only defined for x4 SDRAM. A0/AP Input Auto precharge: A0 is sampled during READ and WRITE commands to determine whether an auto precharge should be performed on the accessed bank after a READ or WRITE operation (HIGH = auto precharge; LOW = no auto precharge). A0 is sampled during a PRECHARGE command to determine whether the precharge applies to one bank (A0 LOW) or all banks (A0 HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank addresses. A/BC_n Input Burst chop: A/BC_n is sampled during READ and WRITE commands to determine if burst chop (on-the-fly) will be performed (HIGH = no burst chop; LOW = burst- chopped). See Command Truth Table in the DDR4 component data sheet. ACT_n Input Command input: ACT_n defines the ACTIVATE command being entered along with CS_n. The input into RAS_n/A6, CAS_n/A5, and WE_n/A4 are considered as row address A6, A5, and A4. See Command Truth Table. BAx Input Bank address inputs: Define the bank (with a bank group) to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be accessed during a MODE REGISTER SET command. BGx Input Bank group address inputs: Define the bank group to which a REFRESH, ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be accessed during a MODE REGISTER SET command. BG[:0] are used in the x4 and x8 configurations. x6-based SDRAM only has BG0. C0, C, C (RDIMM/LRDIMM only) CKx_t CKx_c Input Input 6GB (x7, ECC, DR) 88-Pin DDR4 RDIMM Pin Descriptions Chip ID: These inputs are used only when devices are stacked; that is, H, 4H, and 8H stacks for x4 and x8 configurations using through-silicon vias (TSVs). These pins are not used in the x6 configuration. Some DDR4 modules support a traditional DDP package, which uses CS_n, CKE, and ODT to control the second die. All other stack configurations, such as a 4H or 8H, are assumed to be single-load (master/slave) type configurations where C0, C, and C are used as chip ID selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered part of the command code. Clock: Differential clock inputs. All address, command, and control input signals are sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c. CKEx Input Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self refresh exit. After V REFCA has become stable during the power-on and initialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t, CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during self refresh. CSx_n Input Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides external rank selection on systems with multiple ranks. CS_n is considered part of the command code (CS_n and CS3_n are not used on UDIMMs). 5

6 Pin Descriptions Table 5: Pin Descriptions (Continued) Symbol Type Description ODTx Input On-die termination: ODT (registered HIGH) enables termination resistance internal to the DDR4 SDRAM. When enabled, ODT (R TT ) is applied only to each, S_t, S_c, DM_n/ DBI_n/TS_t, and TS_c signal for x4 and x8 configurations (when the TS function is enabled via the mode register). For the x6 configuration, R TT is applied to each, SU_t, SU_c, SL_t, SL_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode registers are programmed to disable R TT. PARITY Input Parity for command and address: This function can be enabled or disabled via the mode register. When enabled in MR5, the DRAM calculates parity with ACT_n, RAS_n/A6, CAS_n/A5, WE_n/A4, BG[:0], BA[:0], A[6:0]. Input parity should be maintained at the rising edge of the clock and at the same time as command and address with CS_n LOW. RAS_n/A6 CAS_n/A5 WE_n/A4 Input Command inputs: RAS_n/A6, CAS_n/A5, and WE_n/A4 (along with CS_n) define the command and/or address being entered and have multiple functions. For example, for activation with ACT_n LOW, these are addresses like A6, A5, and A4, but for a non-activation command with ACT_n HIGH, these are command pins for READ, WRITE, and other commands defined in Command Truth Table. RESET_n CMOS Input Active LOW asynchronous reset: Reset is active when RESET_n is LOW and inactive when RE- SET_n is HIGH. RESET_n must be HIGH during normal operation. SAx SCL Input Input Serial address inputs: Used to configure the temperature sensor/spd EEPROM address range on the I C bus. Serial clock for temperature sensor/spd EEPROM: Used to synchronize communication to and from the temperature sensor/spd EEPROM on the I C bus. x, CBx I/O Data input/output and check bit input/output: Bidirectional data bus. represents [3:0], [7:0], and [5:0] for the x4, x8, and x6 configurations, respectively. If cyclic redundancy checksum (CRC) is enabled via the mode register, the CRC code is added at the end of the data burst. Any one or all of 0,,, or 3 may be used for monitoring of internal V REF level during test via mode register setting MR[4] A[4] = HIGH; training times change when enabled. DM_n/DBI_n/ TS_t (DMU_n, DBIU_n), (DML_n/ DBIl_n) I/O Input data mask and data bus inversion: DM_n is an input mask signal for write data. Input data is masked when DM_n is sampled LOW coincident with that input data during a write access. DM_n is sampled on both edges of S. DM is multiplexed with the DBI function by the mode register A0, A, and A settings in MR5. For a x8 device, the function of DM or TS is enabled by the mode register A setting in MR. DBI_n is an input/output identifying whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/ output after inversion inside the DDR4 device and not inverted if DBI_n is HIGH. TS is only supported in x8 SDRAM configurations (TS is not valid for UDIMMs). SDA I/O Serial Data: Bidirectional signal used to transfer data in or out of the EEPROM or EEPROM/TS combo device. S_t S_c SU_t SU_c SL_t SL_c I/O Data strobe: Output with read data, input with write data. Edge-aligned with read data, centered-aligned with write data. For x6 configurations, SL corresponds to the data on [7:0], and SU corresponds to the data on [5:8]. For the x4 and x8 configurations, S corresponds to the data on [3:0] and [7:0], respectively. DDR4 SDRAM supports a differential data strobe only and does not support a single-ended data strobe. ALERT_n Output Alert output: Possesses functions such as CRC error flag and command and address parity error flag as output signal. If a CRC error occurs, ALERT_n goes LOW for the period time interval and returns HIGH. If an error occurs during a command address parity check, ALERT_n goes LOW until the on-going DRAM internal recovery transaction is complete. During connectivity test mode, this pin functions as an input. Use of this signal is system-dependent. If not connected as signal, ALERT_n pin must be connected to V DD on DIMMs. EVENT_n Output Temperature event: The EVENT_n pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded. This pin has no function (NF) on modules without temperature sensors. 6

7 Pin Descriptions Table 5: Pin Descriptions (Continued) Symbol Type Description TS_t TS_c (x8 DRAM-based RDIMM only) Output Termination data strobe: When enabled via the mode register, the DRAM device enables the same R TT termination resistance on TS_t and TS_c that is applied to S_t and S_c. When the TS function is disabled via the mode register, the DM/TS_t pin provides the data mask (DM) function, and the TS_c pin is not used. The TS function must be disabled in the mode register for both the x4 and x6 configurations. The DM function is supported only in x8 and x6 configurations. DM, DBI, and TS are a shared pin and are enabled/disabled by mode register settings. For more information about TS, see the DDR4 DRAM component data sheet (TS_t and TS_c are not valid for UDIMMs). V DD Supply Module power supply:.v (). V PP Supply DRAM activating power supply:.5v 0.5V / +0.50V. V REFCA Supply Reference voltage for control, command, and address pins. V SS Supply Ground. V TT Supply Power supply for termination of address, command, and control V DD /. V DDSPD Supply Power supply used to power the I C bus for SPD. RFU Reserved for future use. NC No connect: No internal electrical connection is present. NF No function: May have internal connection present, but has no function. 7

8 Map Map Table 6: -to-module Map Front Reference Module Module Pin Reference Module Module Pin U U U3 0 3 U U5 0 CB3 0 U CB CB CB U U U U U 0 68 U U U5 0 CB CB CB CB7 99 U U

9 Map Table 6: -to-module Map Front (Continued) Reference Module Module Pin Reference Module Module Pin U U Table 7: -to-module Map Back Reference Module Module Pin Reference Module Module Pin U U U U U5 0 CB0 49 U CB CB CB U U U U U U

10 Map Table 7: -to-module Map Back (Continued) Reference Module Module Pin Reference Module Module Pin U U34 0 CB CB CB CB4 47 U U U U

11 Functional Block Diagram Functional Block Diagram Figure : Functional Block Diagram A/BCS0_n A/BCS_n S0_t S0_c 0 3 S_t S_c S_t S_c S3_t S3_c S8_t S8_c CB0 CB CB CB3 S4_t S4_c S5_t S5_c S6_t S6_c S7_t S7_c CS_n S_t S_c U CS_n S_t S_c U CS_n S_t S_c U3 CS_n S_t S_c U4 CS_n S_t S_c U5 CS_n S_t S_c U7 CS_n S_t S_c U8 CS_n S_t S_c U9 CS_n S_t S_c U0 CS_n S_t S_c U9 CS_n S_t S_c U37 CS_n S_t S_c U36 CS_n S_t S_c U35 CS_n S_t S_c U5 CS_n S_t S_c U33 CS_n S_t S_c U3 CS_n S_t S_c U3 CS_n S_t S_c U30 S9_t S9_c S0_t S0_c S_t S_c 0 3 S_t S_c S7_t S7_c CB4 CB5 CB6 CB7 S3_t S3_c S4_t S4_c S5_t S5_c S6_t S6_c CS_n S_t S_c U CS_n S_t S_c U CS_n S_t S_c U3 CS_n S_t S_c U4 CS_n S_t S_c U5 CS_n S_t S_c U7 CS_n S_t S_c U8 CS_n S_t S_c U9 CS_n S_t S_c U0 CS_n S_t S_c U38 CS_n S_t S_c U8 CS_n S_t S_c U7 CS_n S_t S_c U6 CS_n S_t S_c U34 CS_n S_t S_c U4 CS_n S_t S_c U3 CS_n S_t S_c U CS_n S_t S_c U CS0_n CS_n BA[:0] BG[:0] ACT_n A[7, 3:0] RAS_n/A6 CAS_n/A5 WE_n/A4 CKE0 CKE ODT0 ODT PAR_IN C[:0] ALERT_CONN SA0 SA SA SCL SDA RESET_CONN U6 Rank 0: U U5, U7 U5, U7 U0 Rank : U 38 A/BCS_n[:0], A/BBA[:0]A/BBG[:0], A/BACT_n, A/BA[7, 3:0], A/B-RAS_n/A6, A/B-CAS_n/A5, A/B-WE_n/A4, A/BCKE[:0], A/BODT[:0] VDDSPD VDD VTT VREFCA VPP CK_t CK_c SCL R E G I S T E R & P L L Command, control, address, and clock line terminations: CK[3:0]_t CK[3:0]_c U6 CK[:0]_t CK[:0]_c SPD EEPROM/ Temperature sensor EVT A0 A A SA0 SA SA EVENT# A/BCS0_n: Rank 0 A/BCS_n: Rank A/BBA[:0]: DDR4 SDRAM A/BBG[:0]: DDR4 SDRAM A/BACT_n: DDR4 SDRAM A/BA[7,3:0]: DDR4 SDRAM A/B-RAS_n/A6: DDR4 SDRAM A/B-CAS_n/A5: DDR4 SDRAM A/B-WE_n/A4: DDR4 SDRAM A/BCKE0: Rank 0 A/BCKE: Rank A/BODT0: Rank 0 A/BODT: Rank A/BPAR: DDR4 SDRAM C[:0]: DDR4 SDRAM ALERT_DRAM: DDR4 SDRAM DDR4 SDRAM DDR4 SDRAM RESET_DRAM: DDR4 SDRAM DDR4 SDRAM SDA DDR4 SDRAM, Register Control, command and address termination DDR4 SDRAM, Register DDR4 SDRAM, Register VTT SPD EEPROM/Temp Sensor, Register DDR4 SDRAM VDD Note:. The ball on each DDR4 component is connected to an external 40Ω ±% resistor that is tied to ground. It is used for the calibration of the component s ODT and output driver.

12 General Description 6GB (x7, ECC, DR) 88-Pin DDR4 RDIMM General Description High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with two or four internal memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM devices have four internal bank groups consisting of four memory banks each, providing a total of 6 banks. 6-bit-wide DDR4 SDRAM devices have two internal bank groups consisting of four memory banks each, providing a total of eight banks. DDR4 SDRAM modules benefit from DDR4 SDRAM's use of an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bitwide, four-clock data transfer at the internal DRAM core and eight corresponding n-bitwide, one-half-clock-cycle data transfers at the I/O pins. DDR4 modules use two sets of differential signals: S_t and S_c to capture data and CK_t and CK_c to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. Fly-By Topology DDR4 modules use faster clock speeds than earlier DDR technologies, making signal quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and S signals can be easily accounted for by using the write-leveling feature of DDR4.

13 Address Mapping to DRAM Address Mapping to DRAM Address Mirroring To achieve optimum routing of the address bus on DDR4 multi rank modules, the address bus will be wired as shown in the table below, or mirrored. For quad rank modules, ranks and 3 are mirrored and ranks 0 and are non-mirrored. Highlighted address pins have no secondary functions allowing for normal operation when crosswired. Data is still read from the same address it was written. However, Load Mode operations require a specific address. This requires the controller to accommodate for a rank that is "mirrored." Systems may reference DDR4 SPD to determine if the module has mirroring implemented or not. See the JEDEC DDR4 SPD specification for more details. Table 8: Address Mirroring Edge Connector Pin DRAM Pin, Non-mirrored DRAM Pin, Mirrored A0 A0 A0 A A A A A A A3 A3 A4 A4 A4 A3 A5 A5 A6 A6 A6 A5 A7 A7 A8 A8 A8 A7 A9 A9 A9 A0 A0 A0 A A A3 A3 A3 A A A A A4 A4 A4 A5 A5 A5 A6 A6 A6 A7 A7 A7 BA0 BA0 BA BA BA BA0 BG0 BG0 BG BG BG BG0 Registering Clock Driver Operation Registered DDR4 SDRAM modules use a registering clock driver device consisting of a register and a phase-lock loop (PLL). The device complies with the JEDEC DDR4 RCD0 Specification. 3

14 Registering Clock Driver Operation To reduce the electrical load on the host memory controller's command, address, and control bus, Micron's RDIMMs utilize a DDR4 registering clock driver (RCD). The RCD presents a single load to the controller while redriving signals to the DDR4 SDRAM devices, which helps enable higher densities and increase signal integrity. The RCD also provides a low-jitter, low-skew PLL that redistributes a differential clock pair to multiple differential pairs of clock outputs. Control Words Parity Operations Rank Addressing The RCD device(s) used on DDR4 RDIMMs and LRDIMMs contain configuration registers known as control words, which the host uses to configure the RCD based on criteria determined by the module design. Control words can be set by the host controller through either the DRAM address and control bus or the I C bus interface. The RCD I C bus interface resides on the same I C bus interface as the module temperature sensor and EEPROM. The RCD includes a parity-checking function that can be enabled or disabled in control word RC0E. The RCD receives a parity bit at the DPAR input from the memory controller and compares it with the data received on the qualified command and address inputs; it indicates on its open-drain ALERT_n pin whether a parity error has occurred. If parity checking is enabled, the RCD forwards commands to the SDRAM when no parity error has occurred. If the parity error function is disabled, the RCD forwards sampled commands to the SDRAM regardless of whether a parity error has occurred. Parity is also checked during control word WRITE operations unless parity checking is disabled. The chip select pins (CS_n) on Micron's modules are used to select a specific rank of DRAM. The RDIMM is capable of selecting ranks in one of three different operating modes, dependant on setting DA[:0] bits in the DIMM configuration control word located within the RCD. Direct DualCS mode is utilized for single- or dual-rank modules. For quad-rank modules, either direct or encoded QuadCS mode is used. 4

15 Temperature Sensor With SPD EEPROM Operation Thermal Sensor Operations 6GB (x7, ECC, DR) 88-Pin DDR4 RDIMM Temperature Sensor With SPD EEPROM Operation The integrated thermal sensor continuously monitors the temperature of the module PCB directly below the device and updates the temperature data register. Temperature data may be read from the bus host at any time, which provides the host real-time feedback of the module's temperature. Multiple programmable and read-only temperature registers can be used to create a custom temperature-sensing solution based on system requirements and JEDEC JC-4.. EVENT_n Pin The temperature sensor also adds the EVENT_n pin (open-drain), which requires a pullup to V DDSPD. EVENT_n is a temperature sensor output used to flag critical events that can be set up in the sensor s configuration registers. EVENT_n is not used by the serial presence-detect (SPD) EEPROM. EVENT_n has three defined modes of operation: interrupt, comparator, and TCRIT. In interrupt mode, the EVENT_n pin remains asserted until it is released by writing a to the clear event bit in the status register. In comparator mode, the EVENT_n pin clears itself when the error condition is removed. Comparator mode is always used when the temperature is compared against the TCRIT limit. In TCRIT only mode, the EVENT_n pin is only asserted if the measured temperature exceeds the TCRIT limit; it then remains asserted until the temperature drops below the TCRIT limit minus the TCRIT hysteresis. SPD EEPROM Operation DDR4 SDRAM modules incorporate SPD. The SPD data is stored in a 5-byte, JEDEC JC-4.4-compliant EEPROM that is segregated into four 8-byte, write-protectable blocks. The SPD content is aligned with these blocks as shown in the table below. Block Range Description h 07Fh Configuration and DRAM parameters h 0FFh Module parameters h 3Fh Reserved (all bytes coded as 00h) h 7Fh Manufacturing information h FFh End-user programmable The first 384 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR4 SDRAM Modules." The remaining 8 bytes of storage are available for use by the customer. The EEPROM resides on a two-wire I C serial interface and is not integrated with the memory bus in any manner. It operates as a slave device in the I C bus protocol, with all operations synchronized by the serial clock. Transfer rates of up to MHz are achievable at.5v (NOM). Micron implements reversible software write protection on DDR4 SDRAM-based modules. This prevents the lower 384 bytes (bytes 0 to 383) from being inadvertently programmed or corrupted. The upper 8 bytes remain available for customer use and are unprotected. 5

16 Electrical Specifications Table 9: Absolute Maximum Ratings 6GB (x7, ECC, DR) 88-Pin DDR4 RDIMM Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Symbol Parameter Min Max Units Notes V DD V DD supply voltage relative to V SS V V D V D supply voltage relative to V SS V V PP Voltage on V PP pin relative to V SS V V IN, V OUT Voltage on any pin relative to V SS V Table 0: Operating Conditions Symbol Parameter Min Nom Max Units Notes V DD V DD supply voltage V V PP DRAM activating power supply V V REFCA(DC) Input reference voltage command/address bus 0.49 V DD 0.5 V DD 0.5 V DD V 3 I VTT Termination reference current from V TT ma V TT Termination reference voltage (DC) command/address bus I I Input leakage current; any input excluding ; 0V < V IN <.V 0.49 V DD - 0mV 0.5 V DD 0.5 V DD + 0mV V 4 µa 5 I I Input leakage current; 3 3 µa 6, 7 I I/O leakage; 0V < V IN < V DD 4 4 µa 7 I OZpd Output leakage current; V OUT = V DD ; is disabled 5 µa I OZpu I VREFCA Output leakage current; V OUT = V SS ; and ODT are disabled; ODT is disabled with ODT input HIGH V REFCA leakage; V REFCA = V DD / (after DRAM is initialized) 50 µa µa 7 Notes:. V D balls on DRAM are tied to V DD.. V PP must be greater than or equal to V DD at all times. 3. V REFCA must not be greater than 0.6 V DD. When V DD is less than 500mV, V REF may be less than or equal to 300mV. 4. V TT termination voltages in excess of specification limit adversely affect command and address signals' voltage margins and reduce timing margins. 5. Command and address inputs are terminated to V DD / in the registering clock driver. Input current is dependent on termination resistance set in the registering clock driver. 6. Tied to ground. Not connected to edge connector. 7. Multiply by number of DRAM die on module. 6

17 Electrical Specifications Table : Thermal Characteristics Symbol Parameter/Condition Value Units Notes T C Commercial operating case temperature 0 to 85 C,, 3 T C >85 to 95 C,, 3, 4 T OPER Normal operating temperature range 0 to 85 C 5, 7 T OPER Extended temperature operating range (optional) >85 to 95 C 5, 7 T STG Non-operating storage temperature -55 to 00 C 6 RH STG Non-operating Storage Relative Humidity (non-condensing) 5 to 95 % NA Change Rate of Storage Temperature 0 C/hour Notes:. Maximum operating case temperature; T C is measured in the center of the package.. A thermal solution must be designed to ensure the DRAM device does not exceed the maximum T C during operation. 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum T C during operation. 4. If T C exceeds 85 C, the DRAM must be refreshed externally at X refresh, which is a 3.9µs interval refresh rate. 5. The refresh rate must double when 85 C < T OPER 95 C. 6. Storage temperature is defined as the temperature of the top/center of the DRAM and does not reflect the storage temperatures of shipping trays. 7. For additional information, refer to technical note TN-00-08: "Thermal Applications" available at micron.com. 7

18 DRAM Operating Conditions DRAM Operating Conditions Recommended AC operating conditions are given in the DDR4 component data sheets. specifications are available at micron.com. Module speed grades correlate with component speed grades, as shown below. Table : Module and Speed Grades DDR4 components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Speed Grade -G G4-083E -G G -093E -G9-07E Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the edge connector of the module, not at the DRAM. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. 8

19 I DD Specifications I DD Specifications Table 3: DDR4 I DD Specifications and Conditions 6GB (Die Revision A) Values are for the MT40AG4 DDR4 SDRAM only and are computed from values specified in the 4Gb ( Gig x 4) component data sheet Parameter Symbol Units One bank ACTIVATE-PRECHARGE current I DD ma One bank ACTIVATE-PRECHARGE, word line boost, I PP current I PP0 6 6 ma One bank ACTIVATE-READ-PRECHARGE current I DD ma Precharge standby current I DDN ma Precharge standby ODT current I DDNT 60 5 ma Precharge power-down current I DDP ma Precharge quite standby current I DDQ ma Active standby current I DD3N 4 68 ma Active standby I PP current I PP3N ma Active power-down current I DD3P ma Burst read current I DD4R ma Burst read I D current I D4R ma Burst write current I DD4W ma Burst refresh current ( x REF) I DD5B ma Burst refresh I PP current ( x REF) I PP5B ma Self refresh current: Normal temperature range (0 85 C) I DD6N ma Self refresh current: Extended temperature range (0 95 C) I DD6E ma Self refresh current: Reduced temperature range (0 45 C) I DD6R ma Auto self refresh current (5 C) I DD6A ma Auto self refresh current (45 C) I DD6A ma Auto self refresh current (75 C) I DD6A ma Bank interleave read current I DD ma Bank interleave read I PP current I PP ma Maximum power-down current I DD ma Notes:. One module rank in the active I DD/PP, the other rank in I DDP/PP3N.. All ranks in this I DD/PP condition. 9

20 Registering Clock Driver Specifications 6GB (x7, ECC, DR) 88-Pin DDR4 RDIMM Registering Clock Driver Specifications Table 4: Registering Clock Driver Electrical Characteristics DDR4 RCD0 devices or equivalent Parameter Symbol Pins Min Nom Max Units DC supply voltage V DD.4..6 V DC reference voltage V REF V REFCA 0.49 V DD 0.5 V DD 0.5 V DD V DC termination voltage High-level input voltage Low-level input voltage DRST_n pulse width AC high-level output voltage AC low-level output voltage AC differential output high measurement level (for output slew rate) AC differential output low measurement level (for output slew rate) V TT V REF - 40mV V REF V REF + 40mV V V IH. CMOS DRST_n 0.65 V DD V DD V V IL. CMOS V DD V t IN- IT_Power_stable V OH(AC).0 µs All outputs except ALERT_n V TT + (0.5 V DD ) V V OL(AC) V TT + (0.5 x V DD ) V V OHdiff(AC) Yn_t - Yn_c, BCK_t - BCK_c 0.3 V DD mv V OLdiff(AC) 0.3 V DD mv Note:. Timing and switching specifications for the register listed are critical for proper operation of DDR4 SDRAM RDIMMs. These are meant to be a subset of the parameters for the specific device used on the module. See the JEDEC RCD0 specification for complete operating electrical characteristics. Registering clock driver parametric values are specified for device default control word settings, unless otherwise stated. The RC0A control word setting does not affect parametric values. 0

21 Temperature Sensor With SPD EEPROM 6GB (x7, ECC, DR) 88-Pin DDR4 RDIMM Temperature Sensor With SPD EEPROM The temperature sensor continuously monitors the module's temperature and can be read back at any time over the I C bus shared with the serial presence-detect (SPD) EE- PROM. Refer to JEDEC JC-4.4 EE004 and TSE004 device specifications for complete details. SPD Data For the latest SPD data, refer to Micron's SPD page: micron.com/spd. Table 5: Temperature Sensor With SPD EEPROM Operating Conditions Parameter/Condition Symbol Min Nom Max Units Supply voltage V DDSPD.5 V Input low voltage: logic 0; all inputs V IL 0.5 V DDSPD 0.3 V Input high voltage: logic ; all inputs V IH V DDSPD 0.7 V DDSPD V Output low voltage: 3mA sink current V DDSPD > V V OL 0.4 V Input leakage current: (SCL, SDA) V IN = V DDSPD or V SSSPD I LI ±5 µa Output leakage current: V OUT = V DDSPD or V SSSPD, SDA in High-Z I LO ±5 µa Table 6: Temperature Sensor and EEPROM Serial Interface Timing Parameter/Condition Symbol Min Max Units Clock frequency f SCL khz Clock pulse width HIGH time t HIGH 60 ns Clock pulse width LOW time t LOW 500 ns Detect clock LOW timeout t TIMEOUT 5 35 ms SDA rise time t R 0 ns SDA fall time t F 0 ns Data-in setup time t SU:DAT 50 ns Data-in hold time t HD:DI 0 ns Data out hold time t HD:DAT ns Start condition setup time t SU:STA 60 ns Start condition hold time t HD:STA 60 ns Stop condition setup time t SU:STO 60 ns Time the bus must be free before a new transition can start t BUF 500 ns Write time t W 5 ms Warm power cycle time off t POFF ms Time from power on to first command t INIT 0 ms

22 Module Dimensions Module Dimensions Figure 3: 88-Pin DDR4 RDIMM Front view (5.55) 33. (5.44) 3.9 (0.53) MAX U U U3 U4 U5 U6 U7 U8 U9 U (0.03) R (8X).50 (0.098) D (X) 4.8 (0.89) U U3 U5 U U4 U6 U7 U8 U9 U0 9.5 (0.374) 6. (0.63) 3.40 (.36) 3.0 (.4).0 (0.087) 3.35 (0.3) (X) Pin 7.5 (.84) 0.85 (0.033) 0.60 (0.036) 0.75 (0.030) R Pin 44.5 (0.059).3 (0.05) 6.65 (4.99) Back view.5 (0.049) x 45 (X) U U U3 U4 U5 U6 U7 U8 U9 4.6 (0.57) 8.0 (0.35) 3.5 (0.4) U30 U3 U3 U33 U34 U36 U38 U35 U37 Pin (0.4) 5.95 (0.34) 0. (0.4) Pin (0.90).95 (0.9) 5.5 (.0) 8.9 (.4) 3.0 (0.8) (4X) 0.5 (0.097) 56.0 (.) 64.6 (.54) Notes:. All dimensions are in millimeters (inches); MAX/MIN or typical () where noted.. The dimensional diagram is for reference only S. Federal Way, P.O. Box 6, Boise, ID , Tel: Sales inquiries: Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.