DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WE# RAS# A0 A1 A2 A3

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1 MEG x 6 MT4CM6C3, MT4LCM6C3 For the latest data sheet revisions, please refer to the Micron Web site: FEATURES JEDEC- and industry-standard x6 timing, functions, pinouts, and packages High-performance, low-power CMOS silicon-gate process Single power supply (+3.3 ±.3 or 5 ±.5) All inputs, outputs and clocks are TTL-compatible Refresh modes: -ONLY, CAS#-BEFORE- (CBR) and HIDDEN Optional self refresh (S) for low-power data retention BYTE WRITE and BYTE READ access cycles,24-cycle refresh ( row, column addresses) FAST-PAGE-MODE (FPM) access OPTIONS MARKING oltage 3.3 LC 5 C Packages Plastic SOJ (4 mil) Plastic TSOP (4 mil) DJ TG Timing 5ns access -5 6ns access -6 Refresh Rates Standard Refresh (6ms period) None Self Refresh (28ms period) S 2 Operating Temperature Range Commercial ( o C to +7 o C) None Extended (-2 o C to +8 o C) ET 3 Part Number Example: MT4LCM6C3DJ-5 NOTE:. The third field distinguishes the low voltage offering: LC designates CC = 3.3 and C designates CC = Contact factory for availability. 3. Available only on MT4CM6C3 (5) KEY TIMING PARAMETERS SPEED t RC t RAC t PC t AA t CAC t RP -5 84ns 5ns 2ns 25ns 5ns 3ns -6 ns 6ns 35ns 3ns 5ns 4ns CC DQ DQ DQ2 DQ3 CC DQ4 DQ5 DQ6 DQ7 A A A2 A3 CC PIN ASSIGNMENT (Top iew) 42-Pin SOJ SS DQ5 DQ4 DQ3 DQ2 SS DQ DQ DQ9 DQ8 CASL# CASH# OE# A9 A8 A7 A6 A5 A4 SS CC DQ DQ DQ2 DQ3 CC DQ4 DQ5 DQ6 DQ7 A A A2 A3 CC 44/5-Pin TSOP NOTE: The # symbol indicates signal is active LOW. MEG x 6 PART NUMBERS PART NUMBER SUPPLY PACKAGE REFRESH MT4LCM6C3DJ SOJ Standard MT4LCM6C3DJ-6 S 3.3 SOJ Self MT4LCM6C3TG TSOP Standard MT4LCM6C3TG-6 S 3.3 TSOP Self MT4CM6C3DJ-6 5 SOJ Standard MT4CM6C3TG-6 5 TSOP Standard GENERAL DESCRIPTION The Meg x 6 DRAM is a randomly accessed, solidstate memory containing 6,777,26 bits organized in a x6 configuration. The Meg x 6 DRAM has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function identically to a single CAS# on other DRAMs in that either CASL# or CASH# will generate an internal CAS#. The CAS# function and timing are determined by the first CAS# (CASL# or CASH#) to transition LOW and SS DQ5 DQ4 DQ3 DQ2 SS DQ DQ DQ9 DQ8 CASL# CASH# OE# A9 A8 A7 A6 A5 A4 SS Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

2 MEG x 6 GENERAL DESCRIPTION (continued) the last CAS# to transition back HIGH. Use of only one of the two results in a BYTE access cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ-DQ7), and CASH# transitioning LOW selects an access cycle for the upper byte (DQ8-DQ5). Each bit is uniquely addressed through the 2 address bits during READ or WRITE cycles. These are entered ten bits (A-A9) at a time. is used to latch the first ten bits and CAS# the latter ten bits. The CAS# function is determined by the first CAS# (CASL# or CASH#) to transition LOW and the last one to transition back HIGH. The CAS# function also determines whether the cycle will be a refresh cycle (-ONLY) or an active cycle (READ, WRITE, or READ-WRITE) once goes LOW. The CASL# and CASH# inputs internally generate a CAS# signal that functions identically to a single CAS# input on other DRAMs. The key difference is that each CAS# input (CASL# and CASH#) controls its corre- sponding DQ tristate logic (in conjunction with OE# and ). CASL# controls DQ-DQ7 and CASH# controls DQ8-DQ5. The two CAS# controls give the Meg x 6 DRAM BYTE WRITE cycle capabilities. A logic HIGH on dictates read mode, while a logic LOW on dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of or CAS, whichever occurs last. Taking LOW will initiate a WRITE cycle, selecting DQ-DQ5. If goes LOW prior to CAS# going LOW, the output pin(s) remain open (High-Z) until the next CAS# cycle. If goes LOW after CAS# goes LOW and data reaches the output pins, data-out (Q) is activated and retains the selected cell data as long as CAS# and OE# remain LOW (regardless of or ). This late pulse results in a READ-WRITE cycle. The 6 data inputs and 6 data outputs are routed through 6 pins using common I/O. Pin direction is controlled by OE# and. FUTIONAL BLOCK DIAGRAM CASL# CASH# CAS# -IN BUFFER DQ NO. 2 CLOCK GENERATOR 6 DQ5 A A A2 A3 A4 A5 A6 A7 A8 A9 COLUMN- ADDRESS BUFFER REFRESH CONTROLLER REFRESH COUNTER - ADDRESS BUFFERS () DECODER,24 COLUMN DECODER,24 SENSE AMPLIFIERS I/O GATING,24 x 6 6,24 x,24 x 6 MEMORY ARRAY -OUT BUFFER 6 OE# NO. CLOCK GENERATOR DD SS 2 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

3 MEG x 6 FAST PAGE MODE ACCESS (continued) The MT4LCM6C3 must be refreshed periodically in order to retain stored data. FAST PAGE MODE ACCESS FAST-PAGE-MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a row-address-defined (A-A9) page boundary. The FAST-PAGE-MODE cycle is always initiated with a row address strobed in by, followed by a column address strobed in by CAS#. Additional columns may be accessed by providing valid column addresses, strobing CAS# and holding LOW, thus executing faster memory cycles. Returning HIGH terminates the FAST-PAGE-MODE operation. Returning and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standbylevel. The chip is also preconditioned for the next cycle during the HIGH time. Memory cell data is retained in its correct state by maintaining power and executing any cycle (READ, WRITE) or REFRESH cycle ( ONLY, CBR or HIDDEN) so that all,24 combinations of addresses (A-A9) are executed at least every 6ms (28ms on the S version), regardless of sequence. The CBR REFRESH cycle will also invoke the refresh counter and controller for row-address control. BYTE ACCESS CYCLE The BYTE WRITEs and BYTE READs are determined by the use of CASL# and CASH#. Enabling CASL# will select a lower byte access (DQ-DQ7), while enabling CASH# will select an upper byte access (DQ-DQ5). Enabling both CASL# and CASH# selects a WORD WRITE cycle. The Meg x 6 DRAM may be viewed as two Meg x 8 DRAMs that have common input controls, with the exception of the CAS# inputs. Figure illustrates the BYTE WRITE and WORD WRITE cycles. Figure 2 illustrates BYTE READ and WORD READ cycles. WORD WRITE LOWER BYTE WRITE CASL# CASH# LOWER BYTE (DQ-DQ7) OF WORD STORED INPUT INPUT STORED STORED INPUT INPUT STORED UPPER BYTE (DQ8-DQ5) OF WORD ADDRESS ADDRESS = NOT EFFECTIE (DON'T CARE) Figure WORD and BYTE WRITE Example 3 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

4 MEG x 6 Additionally, both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE on the other byte are not allowed during the same cycle. However, an EARLY WRITE on one byte and a LATE WRITE on the other byte, after a CAS# precharge has been satisfied, are permissible. DRAM REFRESH Preserve correct memory cell data by maintaining power and executing any cycle (READ, WRITE) or REFRESH cycle (-ONLY, CBR or HIDDEN) so that all,24 combinations of addresses are executed within t REF (MA), regardless of sequence. The CBR and ETENDED and SELF REFRESH cycles will invoke the internal refresh counter for automatic addressing. An optional self refresh mode is available on the S version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding LOW for the specified t RASS. The S option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 28ms, or 25µs per row, when using a distributed CBR REFRESH. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving HIGH for a minimum time of t RPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the LOWto-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller utilizes a -ONLY or burst CBR refresh sequence, all,24 rows must be refreshed using a minimum t RC refresh rate prior to resuming normal operation. STANDBY Returning and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the HIGH time. WORD READ LOWER BYTE READ CASL# CASH# LOWER BYTE (DQ-DQ7) OF WORD STORED OUTPUT OUTPUT STORED STORED OUTPUT OUTPUT STORED UPPER BYTE (DQ8-DQ5) OF WORD ADDRESS ADDRESS Z = High-Z Figure 2 WORD and BYTE READ Example 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

5 MEG x 6 ABSOLUTE MAIMUM RATINGS* oltage on CC Pin Relative to SS to TO +7 oltage on, Inputs or I/O Pins Relative to SS to TO +7 Operating Temperature T A (commercial)... C to +7 C T A (extended "ET") C to +8 C Storage Temperature (plastic) C to +5 C Power Dissipation... W *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes:, 5, 6; notes can be found on page 9); CC (MIN) CC CC (MA) PARAMETER/CONDITION NOTES SUPPLY OLTAGE CC INPUT HIGH OLTAGE: alid Logic ; All inputs, I/Os and any IH CC + INPUT LOW OLTAGE: alid Logic ; All inputs, I/Os and any INPUT LEAKAGE CURRENT: Any input at IN ( IN CC +.3); II µa All other pins not under test = OUTPUT HIGH OLTAGE: IOUT = -2mA OH OUTPUT LOW OLTAGE: IOUT = 2mA OL.4.4 OUTPUT LEAKAGE CURRENT: Any output at OUT [ OUT CC (MA)]; IOZ µa DQ is disabled and in High-Z state 5 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

6 MEG x 6 ICC OPERATING CONDITIONS AND MAIMUM LIMITS (Notes:, 2, 3, 5, 6; notes can be found on page 9); CC (MIN) CC CC (MA) PARAMETER/CONDITION SYMBOL SPEED UNITS NOTES STANDBY CURRENT: TTL ICC ALL 2 ma ( = CAS# = IH) STANDBY CURRENT: CMOS (non- S version only) ICC2 ALL 5 5 µa ( = CAS# = other inputs = CC -.2) STANDBY CURRENT: CMOS ( S version only) ICC2 ALL 5 5 µa ( = CAS# = other inputs = CC -.2) OPERATING CURRENT: Random READ/WRITE Average power supply current ICC ma 23 (, CAS#, address cycling: t RC = t RC [MIN]) OPERATING CURRENT: FAST PAGE MODE -5 2 Average power supply current ICC4-6 9 ma 23 ( =, CAS#, address cycling: t PC = t PC [MIN]) REFRESH CURRENT: -ONLY Average power supply current ICC ma ( cycling, CAS# = IH: t RC = t RC [MIN]) REFRESH CURRENT: CBR Average power supply current ICC ma 4, 7 (, CAS#, address cycling: t RC = t RC [MIN]) REFRESH CURRENT: Extended ( S version only) Average power supply current: CAS# =.2 or CBR cycling; ICC7 ALL 3 3 µa 4, 7 = t RAS (MIN); = CC -.2; A-A, OE# and DIN = CC -.2 or.2 (DIN may be left open) REFRESH CURRENT: Self ( S version only) Average power supply current: CBR with ICC8 ALL 3 3 µa 4, 7 t RASS (MIN) and CAS# held LOW; = CC -.2; A-A, OE# and DIN = CC -.2 or.2 (DIN may be left open) CAPACITAE (Note: 2; notes can be found on page 9); PARAMETER SYMBOL MA UNITS Input Capacitance: Addresses CI 5 pf Input Capacitance:, CASL#, CASH#,, OE# CI2 7 pf Input/Output Capacitance: DQ CIO 7 pf 6 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

7 MEG x 6 AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9,,, 2; notes can be found on page 9); CC (MIN) CC CC (MA) AC CHARACTERISTICS PARAMETER NOTES Access time from column address t AA 25 3 ns Column-address hold time (referenced to ) t AR ns Column-address setup time t ASC ns 27 Row-address setup time t ASR ns Column address to delay time t AWD ns 8 Access time from CAS t CAC 5 5 ns 29 Column-address hold time t CAH 8 ns 27 CAS# pulse width t CAS 8,, ns 32, 35 CAS# LOW to Don t Care during Self Refresh t CHD 5 5 ns CAS# hold time (CBR Refresh) t CHR 8 ns 4, 28 Last CAS# going LOW to first CAS# to return HIGH t CLCH ns 3 CAS# to output in Low-Z t CLZ ns 26, 29 CAS# precharge time t CP 8 5 ns 3 Access time from CAS# precharge t CPA ns 28 CAS# to precharge time t CRP 5 5 ns 28 CAS# hold time t CSH ns 28 CAS# setup time (CBR Refresh) t CSR 5 5 ns 4, 27 CAS# to delay time t CWD ns 8, 27 WRITE command to CAS# lead time t CWL 8 ns 23, 29 Data-in hold time t DH 8 ns 9, 29 Data-in setup time t DS ns 9, 29 Output disable t OD 2 5 ns 7, 26, 29 Output enable t OE 2 5 ns 22 OE# hold time from during t OEH 8 ns 2 READ-MODIFY-WRITE cycle Output buffer turn-off delay t OFF 2 5 ns, 7, 23 OE# setup prior to during HIDDEN Refresh cycle t ORD ns FAST-PAGE-MODE READ or WRITE cycle time t PC 2 25 ns 3 FAST-PAGE-MODE READ-WRITE cycle time t PRWC ns 3 Access time from t RAC 5 6 ns to column-address delay time t RAD 9 2 ns 2 Row-address hold time t RAH 9 ns pulse width t RAS 5, 6, ns pulse width (FAST PAGE MODE) t RASP 5 25, 6 25, ns pulse width (Self Refresh) t RASS µs Random READ or WRITE cycle time t RC 84 4 ns to CAS# delay time t RCD 4 ns 4, 27 READ command hold time (referenced to CAS) t RCH ns 6, 28 READ command setup time t RCS ns 27 Refresh period (,24 cycles) t REF 6 6 ms Refresh period (,24 cycles) S version t REF ms precharge time t RP 3 4 ns to CAS# precharge time t RPC 5 5 ns precharge time (Self Refresh) t RPS 9 5 ns READ command hold time (referenced to ) t RRH ns 6 hold time t RSH 3 5 ns 36 READ-WRITE cycle time t RWC 6 4 ns 7 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

8 MEG x 6 AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9,,, 2; notes can be found on page 9); CC (MIN) CC CC (MA) AC CHARACTERISTICS PARAMETER NOTES to delay time t RWD ns 8 WRITE command to lead time t RWL 3 5 ns Transition time (rise or fall) t T ns WRITE command hold time t WCH 8 ns 36 WRITE command hold time (referenced to ) t WCR ns command setup time t WCS ns 8, 27 WRITE command pulse width t WP 5 5 ns hold time (CBR Refresh) t WRH 8 ns setup time (CBR Refresh) t WRP 8 ns 8 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

9 MEG x 6 NOTES. All voltages referenced to SS. 2. This parameter is sampled. CC = +3.3 or 5.; f = MHz. 3. ICC is dependent on output loading. Specified values are obtained with minimum cycle time and the output open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range ( C T A 7 C) for commercial and (-2 C T A 8 C) for extended ET is ensured. 6. An initial pause of µs is required after powerup, followed by eight refresh cycles (- ONLY or CBR), before proper device operation is ensured. The eight cycle wake-ups should be repeated any time the t REF refresh requirement is exceeded. 7. AC characteristics assume t T = 5ns. 8. IH (MIN) and (MA) are reference levels for measuring timing of input signals. Transition times are measured between IH and (or between and IH). 9. In addition to meeting the transition rate specification, all input signals must transit between IH and (or between and IH) in a monotonic manner.. If CAS# = IH, data output is High-Z.. If CAS# =, data output may contain data from the last valid READ cycle. 2. Measured with a load equivalent to two TTL gates, pf and OL =.8 and OH = If CAS# is LOW at the falling edge of, Q will be maintained from the previous cycle. To initiate a new cycle and clear the Q buffer, CAS# must be pulsed HIGH for t CP. 4. The t RCD (MA) limit is no longer specified. t RCD (MA) was specified as a reference point only. If t RCD was greater than the specified t RCD (MA) limit, then access time was controlled exclusively by t CAC ( t RAC [MIN] no longer applied). With or without the t RCD limit, t AA and t CAC must always be met. 5. The t RAD (MA) limit is no longer specified. t RAD (MA) was specified as a reference point only. If t RAD was greater than the specified t RAD (MA) limit, then access time was controlled exclusively by t AA ( t RAC and t CAC no longer applied). With or without the t RAD (MA) limit, t AA, t RAC, and t CAC must always be met. 6. Either t RCH or t RRH must be satisfied for a READ cycle. 7. t OFF (MA) defines the time at which the output achieves the open circuit condition; it is not a reference to OH or OL. 8. t WCS, t RWD, t AWD, and t CWD are restrictive operating parameters in LATE WRITE and READ- MODIFY-WRITE cycles only. If t WCS ³ t WCS (MIN), the cycle is an EARLY WRITE cycle and the data out-put will remain an open circuit throughout the entire cycle. If t RWD ³ t RWD (MIN), t AWD ³ t AWD (MIN) and t CWD ³ t CWD (MIN), the cycle is a READ WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of Q (at access time and until CAS# or OE# goes back to IH) is indeterminate. OE# held HIGH and taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. 9. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 2. During a READ cycle, if OE# is LOW then taken HIGH before CAS# goes HIGH, Q goes open. If OE# is tied permanently LOW, LATE WRITE and READ-MODIFY-WRITE operations are not permissible and should not be attempted. 2. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, = LOW and OE# = HIGH. 22. All other inputs at.2 or CC Column address changed once each cycle. 24. LATE WRITE and READ-MODIFY-WRITE cycles must have both t OD and t OEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS# remains LOW and OE# is taken back LOW after t OEH is met. If CAS# goes HIGH prior to OE# going back LOW, the DQs will remain open. 25. The DQs open during READ cycles once t OD or t OFF occur. 26. The 3ns minimum is a parameter guaranteed by design. 27. The first CASx edge to transition LOW. 28. The last CASx edge to transition HIGH. 29. Output parameter (DQx) is referenced to corresponding CAS# input; DQ-DQ7 by CASL# and DQ8-DQ5 by CASH#. 3. Last falling CASx edge to first rising CASx edge. 3. Last rising CASx edge to next cycle s last rising CASx edge. 9 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

10 MEG x 6 NOTES (continued) 32. Last rising CASx edge to first falling CASx edge. 33. First DQs controlled by the first CASx to go LOW. 34. Last DQs controlled by the last CASx to go HIGH. 35. Each CASx must meet minimum pulse width. 36. Last CASx to go LOW. 37. All DQs controlled, regardless CASL# and CASH#. 38. If OE# is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not permissible and should not be attempted. Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

11 MEG x 6 READ CYCLE t RC t RAS t RP IH t CSH t RSH t RRH t CRP t RCD t CAS t CLCH CASL#/CASH# IH t RAD t AR tcah t ASR t RAH t ASC ADDR IH COLUMN t RCS t RCH IH t AA t RAC t CAC t OFF t CLZ DQ IOH IOL ALID toe tod OE# IH DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 3 ns t AR ns t ASC ns t ASR ns t CAC 5 5 ns t CAH 8 ns t CAS 8,, ns t CLCH ns t CLZ ns t CRP 5 5 ns t CSH ns t OD 2 5 ns t OFF 2 5 ns t RAC 5 6 ns t RAD 9 2 ns t RAH 9 ns t RAS 5, 6, ns t RC 84 4 ns t RCD 4 ns t RCH ns t RCS ns t RP 3 4 ns t RRH ns t RSH 3 5 ns t OE 2 5 ns Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

12 MEG x 6 EARLY WRITE CYCLE t RC t RAS trp IH t CSH t RSH t CRP t RCD t CAS t CLCH CASL#/CASH# IH t AR t RAD t ASR t RAH t ASC t CAH ADDR IH COLUMN t CWL t RWL t WCR t WCS t WCH t WP IH t DS t DH DQ IOH IOL ALID OE# IH DON T CARE UNDEFINED TIMING PARAMETERS t AR ns t ASC ns t ASR ns t CAH 8 ns t CAS 8,, ns t CLCH ns t CRP 5 5 ns t CSH ns t CWL 8 ns t DH 8 ns t DS ns t RAD 9 2 ns t RAH 9 ns t RAS 5, 6, ns t RC 84 4 ns t RCD 4 ns t RP 3 4 ns t RSH 3 5 ns t RWL 3 5 ns t WCH 8 ns t WCR ns t WCS ns t WP 5 5 ns 2 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

13 MEG x 6 READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) t RWC t RAS trp IH t CSH t RSH t CRP t RCD t CAS t CLCH CASL#/CASH# IH t AR t RAD t ASR t RAH t ASC t CAH ADDR IH COLUMN t RWD t CWL t RCS t CWD t AWD t RWL t WP IH t AA t RAC t CAC t DS t DH t CLZ DQ IOH IOL ALID D OUT ALID D IN t OE t OD t OEH OE# IH DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 3 ns t AR ns t ASC ns t ASR ns t AWD ns t CAC 5 5 ns t CAH 8 ns t CAS 8,, ns t CLCH ns t CLZ ns t CRP 5 5 ns t CSH ns t CWD ns t CWL 8 ns t DH 8 ns t DS ns t OD 2 5 ns t OE 2 5 ns t OEH 8 ns t RAC 5 6 ns t RAD 9 2 ns t RAH 9 ns t RAS 5, 6, ns t RCD 4 ns t RCS ns t RP 3 4 ns t RSH 3 5 ns t RWC 6 4 ns t RWD ns t RWL 3 5 ns t WP 5 5 ns 3 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

14 MEG x 6 FAST-PAGE-MODE READ CYCLE t RASP t RP IH t CSH t PC t RSH t CRP t RCD t CAS, t CLCH t CP t CAS, t CLCH t CP t CAS, t CLCH t CP CASL#/CASH# IH t AR t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH ADDR IH COLUMN COLUMN COLUMN t RCS t RCS t RRH t RCS t RCH t RCH t RCH IH t AA t AA t AA t RAC t CPA t CPA t CAC t OFF t CAC t OFF t CAC t OFF t CLZ t CLZ t CLZ DQ IOH IOL ALID ALID ALID t OE t OD t OE t OD t OE t OD OE# IH DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 3 ns t AR ns t ASC ns t ASR ns t CAC 5 5 ns t CAH 8 ns t CAS 8,, ns t CLCH ns t CLZ ns t CP 8 5 ns t CPA ns t CRP 5 5 ns t CSH ns t OD 2 5 ns t OE 2 5 ns t OFF 2 5 ns t PC 2 25 ns t RAC 5 6 ns t RAD 9 2 ns t RAH 9 ns t RASP 5 25, 6 25, ns t RCD 4 ns t RCH ns t RCS ns t RP 3 4 ns t RRH ns t RSH 3 5 ns 4 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

15 MEG x 6 FAST-PAGE-MODE EARLY WRITE CYCLE t RASP t RP IH t CSH t PC t RSH t CRP t RCD t CAS, t CLCH t CP t CAS, t CLCH t CP t CAS, t CLCH t CP CASL#/CASH# IH t AR t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH ADDR IH COLUMN COLUMN COLUMN t CWL t CWL t CWL t WCS t WCH t WCS t WCH t WCS t WCH t WP t WP t WP IH t WCR t RWL t DS t DH t DS t DH t DS t DH DQ IOH IOL ALID ALID ALID OE# IH DON T CARE UNDEFINED TIMING PARAMETERS t AR ns t ASC ns t ASR ns t CAH 8 ns t CAS 8,, ns t CLCH ns t CP 8 5 ns t CRP 5 5 ns t CSH ns t CWL 8 ns t DH 8 ns t DS ns t PC 2 25 ns t RAD 9 2 ns t RAH 9 ns t RASP 5 25, 6 25, ns t RCD 4 ns t RP 3 4 ns t RSH 3 5 ns t RWL 3 5 ns t WCH 8 ns t WCR ns t WCS ns t WP 5 5 ns 5 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

16 MEG x 6 FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) t RASP t RP IH t CRP t CSH NOTE t PC t PRWC t RCD t CAS, t CLCH t CP t CAS, t CLCH t RSH t CP t CAS, t CLCH t CP CASL#/CASH# IH t AR t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH ADDR IH COLUMN COLUMN COLUMN t RWD t RWL t RCS t CWL t CWL t CWL t WP t AWD t WP t AWD t AWD t WP t CWD t CWD t CWD IH t AA t AA t AA t RAC t DS t DH t CPA t DS t DH t CPA t DS t DH t CAC t CLZ t CAC t CLZ t CAC t CLZ DQ IOH IOL ALID D OUT ALID D IN ALID D OUT ALID D IN ALID D OUT ALID D IN t OE t OD t OE t OD t OE t OD OEH OE# IH DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 3 ns t AR ns t ASC ns t ASR ns t AWD ns t CAC 5 5 ns t CAH 8 ns t CAS 8,, ns t CLCH ns t CLZ ns t CP 8 5 ns t CPA ns t CRP 5 5 ns t CSH ns t CWD ns t CWL 8 ns t DH 8 ns t DS ns t OD 2 5 ns t OE 2 5 ns t OEH 8 ns t PC 2 25 ns t PRWC ns t RAC 5 6 ns t RAD 9 2 ns t RAH 9 ns t RASP 5 25, 6 25, ns t RCD 4 ns t RCS ns t RP 3 4 ns t RSH 3 5 ns t RWD ns t RWL 3 5 ns t WP 5 5 ns NOTE:. t PC is for LATE WRITE only. 6 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

17 MEG x 6 FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RASP t RP IH t RSH t CSH t PC t CRP t RCD t CAS t CP t CAS t CP CASL#/CASH# IH t AR t RAD t ASR t RAH t ASC t CAH t ASC t CAH ADDR IH COLUMN COLUMN t CWL t RCS t RWL t WP t WCS t WCH IH t CAC t CLZ NOTE t OFF t DS t DH Q OH OL t AA ALID ALID OE# IH trac DON T CARE UNDEFINED TIMING PARAMETERS t AA 25 3 ns t AR ns t ASC ns t ASR ns t CAC 5 5 ns t CAH 8 ns t CAS 8,, ns t CLZ ns t CP 8 5 ns t CRP 5 5 ns t CSH ns t CWL 8 ns t DH 8 ns t DS ns t OFF 2 5 ns t PC 2 25 ns t RAC 5 6 ns t RAD 9 2 ns t RAH 9 ns t RASP 5 25, 6 25, ns t RCD 4 ns t RCS ns t RP 3 4 ns t RSH 3 5 ns t RWL 3 5 ns t WCH 8 ns t WCS ns t WP 5 5 ns NOTE:. t PC is for LATE WRITE only. 7 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

18 MEG x 6 -ONLY REFRESH CYCLE (OE# and = DON T CARE) t RC t RAS t RP IH t CRP t RPC CASL#/CASH# IH t ASR t RAH ADDR IH Q OH OL CBR REFRESH CYCLE (Addresses and OE# = DON T CARE) t RP t RAS NOTE t RP t RAS IH t RPC t CP t CSR t CHR t RPC t CSR tchr CASL#/CASH# IH DQ OH OL t WRP t WRH t WRP t WRH IH DON T CARE UNDEFINED TIMING PARAMETERS t ASR ns t CHR 8 ns t CP 8 5 ns t CRP 5 5 ns t CSR 5 5 ns t RAH 9 ns t RAS 5 6, ns t RC 84 4 ns t RP 3 4 ns t RPC 5 5 ns t WRH 8 ns t WRP 8 ns NOTE:. End of CBR REFRESH cycle. 8 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

19 MEG x 6 HIDDEN REFRESH CYCLE ( = HIGH; OE# = LOW) TIMING PARAMETERS t AA 25 3 ns t AR ns t ASC ns t ASR ns t CAC 5 5 ns t CAH 8 ns t CHR 8 ns t CLZ ns t CRP 5 5 ns t OD 2 5 ns t OE 2 5 ns t OFF 2 5 ns t ORD ns t RAC 5 6 ns t RAD 9 2 ns t RAH 9 ns t RAS 5, 6, ns t RCD 4 ns t RP 3 4 ns t RSH 3 5 ns NOTE:. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, is LOW and OE# is HIGH. 9 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

20 MEG x 6 SELF REFRESH CYCLE (Addresses and OE# = DON T CARE) t RP t RASS ( ) ( ) NOTE t RPS NOTE 2 IH t RPC ( ( t RPC ( ( ) ) ) ) t CP t CSR t CHD t CP CAS# IH ( ) ( ) ( ) ( ) DQ OH OL IH ( ( ) ) t WRP t WRH ( ( ) ) ( ) ( ) t WRP t WRH DON T CARE UNDEFINED TIMING PARAMETERS t CHD 5 5 ns t CLCH ns t CP 8 5 ns t CSR 5 5 ns t RASS µs t RP 3 4 ns t RPC 5 5 ns t RPS 9 5 ns t WRH 8 ns t WRP 8 ns NOTE:. Once t RASS (MIN) is met and remains LOW, the DRAM will enter self refresh mode. 2. Once t RPS is satisfied, a complete burst of all rows should be executed if -only or burst CBR refresh is used. 2 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

21 MEG x 6 42-PIN PLASTIC SOJ (4 mil).79 (27.4).73 (27.25).45 (.29).399 (.3).445 (.3).435 (.5) PIN # INDE.5 (.27) TYP. (25.4).32 (.8).26 (.66).48 (3.76).38 (3.5).95 (2.4).8 (2.2) SEATING PLANE.37 (.94) MA DAMBAR PROTRUSION.2 (.5).5 (.38).38 (9.65).36 (9.4).3 (.76) MIN NOTE:. All dimensions in inches (millimeters) MA or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is." per side. 2 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.

22 MEG x 6 44/5-PIN PLASTIC TSOP (4 mil) (2.4).822 (2.88).29 (.75) TYP SEE DETA A.467 (.86).459 (.66).42 (.2).398 (.) PIN # INDE.3 (.8) TYP.8 (.45).2 (.3) 25.7 (.8).5 (.3).47 (.2) MA.4 (.) SEATING PLANE.8 (.2).2 (.5) DETA A.32 (.8) TYP. (.25).24 (.6).6 (.4) NOTE:. All dimensions in inches (millimeters) MA or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is." per side. 8 S. Federal Way, P.O. Box 6, Boise, ID , Tel: prodmktg@micron.com, Internet: Customer Comment Line: Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc. 22 Meg x 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. D5_5_B.p65 Rev. B; Pub 3/ 2, Micron Technology, Inc.