Reconfig'09 Cancun, Mexico



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Transcription:

Reconfig'09 Cancun, Mexico New OPBHW Interface for Real-Time Partial Reconfiguration of FPGA Julien Delorme, Amor Nafkha, Pierre Leray, Christophe Moy SUPELEC/IETR 10 December 2009 SUPELEC - Campus de Rennes - France SCEE Signal, Communications et Electronique Embarquée IETR UMR CNRS 6164 Institut d'electronique et Télécommunications de Rennes

Experiments on Partial Reconfiguration of FPGA Prototyping PR since 2003 Developed our own design flow Virtex devices based on Xilinx tools (beyond usual use) Application domain: Software defined radio SDR domain is extremely demanding in both processing power and real-time flexibility PR has been foreseen for a while as an enabling technology for SDR Xilinx decided to develop this technology for SDR market Christophe MOY - SUPELEC - 10 December 2009 2

SDR-oriented publications on Partial Reconfiguration 1. Dominique NUSSBAUM, Karim KALFALLAH, Raymond KNOPP, Christophe MOY, Amor NAFKHA, Pierre LERAY, Julien DELORME, Jacques PALICOT, Jerome MARTIN, Fabien CLERMIDY, Bertrand MERCIER, Renaud PACALET "Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques" DSD 09, 12th Euromicro Conference on Digital System Design, 27-29 Aug. 2009, Patras, Greece 2. Christophe MOY, Amor NAFKHA, Pierre LERAY, Julien DELORME, Jacques PALICOT, Dominique NUSSBAUM, Karim KALFALLAH, Hervé CALLEWWAERT, Jérôme MARTIN, Fabien CLERMIDY, Bertrand MERCIER, Renaud PACALET "IDROMel: An Open Platform Addressing Advanced SDR Challenges" SDR Forum Technical Conference'08, 27-30 November 2008, Washington DC, USA 3. Julien DELORME, Jérôme MARTIN, Amor NAFKHA, Christophe MOY, Fabien CLERMIDY, Pierre LERAY, Jacques PALICOT A FPGA partial reconfiguration design approach for cognitive radio based on NoC architecture NEWCAS'08, 22-25 juin 2008, Montréal Canada 4. Amor NAFKHA, Julien DELORME, Renaud SEGUIER, Christophe MOY, Jacques PALICOT "A heterogeneous reconfigurable platform for cognitive radio systems" 5th Karlsruhe Workshop on Software Radios, WSR'08, Karlsruhe, Allemagne, Mars 2008 5. Loïg GODARD, Hongzhi WANG, Christophe MOY, Pierre LERAY "Common Operators Design on Dynamically Reconfigurable Hardware for SDR Systems" SDR Forum Technical Conference 07, Denver (USA), 5-9 November 2007 6. Jean-Philippe DELAHAYE, Pierre LERAY, Christophe MOY "Designing a Reconfigurable Processing Datapath for SDR over Heterogeneous Reconfigurable Platforms" SDR Forum Technical Conference 07, Denver (USA), 5-9 November 2007 7. Jean-Philippe DELAHAYE, Jacques PALICOT, Christophe MOY, Pierre LERAY Partial Reconfiguration of FPGAs for Dynamical Reconfiguration of a Software Radio Platform IST Mobile and Wireless Communications Summit'07, 1-5 July 2007, Budapest, Hungary 8. Jean-Philippe DELAHAYE, Pierre LERAY, Christophe MOY, Jacques PALICOT "Managing Dynamic Partial Reconfiguration on Heterogeneous SDR Platforms" SDR Forum Technical Conference 05, Anaheim (USA), November 2005 - outstanding paper award Christophe MOY - SUPELEC - 10 December 2009 3

PR real-time implementation demos E2R-phase 2: European research program Sundance platform (DSP+FPGA+ADAC) RT modulation switching (DSP+FPGA PR) demos in 2005 and 2006 IDROMel: French research program NoC context (based on CEA FAUST chip) integration in a NoC HW and protocol context real-time reconfiguration of ultra high data rate radio PHY modules (up to 100 Mbps) in 2007 Christophe MOY - SUPELEC - 10 December 2009 4

PR is coming in Xilinx tools but ISE v11 OPBHW controller far less than possible technological capabilities First step: IP_8 8 bits version (for Virtex 2) gain of 124 in reconfiguration time Second step: IP_DMA bits version (for Virtex 4 & 5) max technological capabilities Virtex V - 400 MB/s @ 100 MHz OPBHW IP_8 Multiplexer and byte reverse Registers B R A M 8 IP_DMA SRAM ctrl Christophe MOY - SUPELEC - 10 December 2009 5 SRAM

Proof of concept Example of a bitstream of 25 kb (encod.+intrl.) note that minimizing bitsream size is also a work in itself (parameterization for instance) 6250 bits words 62.5 µs @ 100 MHz init overhead (register loading): 5 µs total reconfiguration time of 67.5 µs validated also @125 MHz (500 MB/s) 55 µs Real-time 4G radio adaptation on a video stream application interfaces compatible with all ML5xx boards (only depends on memory indeed) Christophe MOY - SUPELEC - 10 December 2009 6

See you at the poster PR = Combining HW processing power with SW flexibility AC Group Automatics & Communication PR design - Xilinx Virtex devices - SRAM - external RAM - microblaze - BusMacro before ISE v11 PR advantages - small size of the bitstream - fast reconfiguration (starting from a few µs) - less memory-demanding for storage SCEE team Signal Communication & Embedded Electronics New OPBHW Interface for Real-Time Partial Reconfiguration of FPGA Julien Delorme, Amor Nafkha, Pierre Leray, Christophe Moy Partial Reconfiguration principles - only a sub-part of a FPGA is reconfigured - while the rest of the component still works - opens the SW flexibility to the HW performance - any time custom design for (computing and space) efficiency - low bandwidth overhead for Over-The-Air bitstream download in SDR context Reconfig'09 Conference Cancun, Mexico 8-11 December 2009 SUPELEC / IETR Avenue de la Boulaie CS 47601 F-35576 Cesson-Sevigné CEDEX, France contact: christophe.moy@supelec.fr OPB RS2 OPB EMC PRM LED Switchs GPIO FPGA OPB HW Bus OPB PR design secrets - specific and original design flow - ISE with a modular approach - 1 project per module for static modules - 1 project per configuration for PR modules - PlanAhead - specification of PR and static modules - physical allocation of modules with floorplanning tool - partial bitstreams generation for PR modules - design alternatives: trade-off between efficiency and design ease - IP design approach for minimizing reconfigurable area and bistreams size - bitstream generation (difference-based partial bitstream) - basic PR introduction in current CAD tools (ISE v11) now interfaces OPBHW XILINX ISE v11 B R A M IP_8 Multiplexer and byte reverse 8 SUPELEC Virtex 2 to 5 IP_DMA SRAM ctrl Registers SUPELEC Virtex 4 & 5 SRAM Results Reconfiguration duration Reconfiguration time (in µs) 10000 9000 8000 7000 6000 5000 4000 3000 2000 PR Reconfiguration performance comparison 8372 gain of 124 in reconfiguration time 2722 Proof of concept demonstrator - video streaming (no video interruption) - 4G real-time SDR (radio) application (100 Mbps) - baseband IPs reconfiguration in a NoC context - NoC based on FAUST chip from CEA Host video stream sent Host video stream received 1000 0 Size Nb slices Nb FlipFlops Nb LUTs Nb BRAMs IST Mobile Summit 06 4-8 June 2006 Mykonos, GREECE ACKNOWLEDGMENTS: This work was supported by the European Commission in the framework of the FP7 Network of Excellence in Wireless COMmunications NEWCOM++ (contract no. 216715). 67,5 OPBHW IP_8 IP_DMA OPBHW 131 153 210 1 PR IP management Max of technological capabilities: Virtex V - 400 MB/s @ 100 MHz 8 28 43 45 0 DMA 35 58 71 0 Ethernet FPGA ASIC FPGA ASIC INSTITUT D ÉLECTRONIQUE ET DE TÉLÉCOMMUNICATIONS DE RENNES Christophe MOY - SUPELEC - 10 December 2009 7

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