pplications l Dual SO-8 MOSFET for POL converters in desktop, servers, graphics cards, game consoles and set-top box l Lead-Free Benefits l Very Low R DS(on) at 4.5V V GS l Ultra-Low Gate Impedance l Fully Characterized valanche Voltage and Current l 20V V GS Max. Gate Rating IRF89PbF HEXFET Power MOSFET SO-8 PD -95673 V DSS R DS(on) max I D 20V 3.4m:@V GS = V S G S2 G2 2 3 Top View 8 7 6 4 5 D D D2 D2 bsolute Maximum Ratings Parameter Max. Units V DS Drain-to-Source Voltage 20 V V GS Gate-to-Source Voltage ± 20 I D @ T = 25 C Continuous Drain Current, V GS @ V I D @ T = 70 C Continuous Drain Current, V GS @ V 8.3 I DM Pulsed Drain Current c 82 P D @T = 25 C Power Dissipation 2.0 W P D @T = 70 C Power Dissipation Linear Derating Factor.3 0.06 W/ C T J Operating Junction and -55 to 50 C Storage Temperature Range T STG Thermal Resistance Parameter Typ. Max. Units R θjl Junction-to-Drain Lead 20 C/W R θj Junction-to-mbient fg 62.5 Notes through are on page www.irf.com 8//04
IRF89PbF Static @ T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV DSS Drain-to-Source Breakdown Voltage 20 V ΒV DSS / T J Breakdown Voltage Temp. Coefficient 0.05 V/ C R DS(on) Static Drain-to-Source On-Resistance.7 3.4 mω 4.6 8.3 V GS(th) Gate Threshold Voltage.65 2.55 V V GS = 4.5V, I D = 8.0 e V DS = V GS, I D = 250µ V GS(th) / T J Gate Threshold Voltage Coefficient -4.8 mv/ C I DSS Drain-to-Source Leakage Current.0 µ V DS = 6V, V GS = 0V 50 V DS = 6V, V GS = 0V, T J = 25 C I GSS Gate-to-Source Forward Leakage 0 n V GS = 20V Gate-to-Source Reverse Leakage -0 V GS = -20V gfs Forward Transconductance 24 S V DS = V, I D = 8.2 Q g Total Gate Charge 7.4 Q gs Pre-Vth Gate-to-Source Charge 2.4 V DS = V Q gs2 Post-Vth Gate-to-Source Charge 0.80 nc V GS = 4.5V Q gd Gate-to-Drain Charge 2.5 I D = 8.2 Q godr Gate Charge Overdrive.7 See Fig. 6 Q sw Switch Charge (Q gs2 Q gd ) 3.3 Q oss Output Charge 4.4 nc V DS = V, V GS = 0V t d(on) Turn-On Delay Time 6.2 V DD = V, V GS = 4.5V t r Rise Time ns I D = 8.2 t d(off) Turn-Off Delay Time 9.7 Clamped Inductive Load t f Fall Time 4. C iss Input Capacitance 960 V GS = 0V C oss Output Capacitance 300 pf V DS = V C rss Reverse Transfer Capacitance 60 ƒ =.0MHz valanche Characteristics Parameter Typ. Max. Units E S Single Pulse valanche Energy d 9 mj I R valanche Current c 8.2 Diode Characteristics Parameter Min. Typ. Max. Units I S Continuous Source Current 2.5 (Body Diode) I SM Pulsed Source Current 82 (Body Diode)c V SD Diode Forward Voltage.0 V t rr Reverse Recovery Time 7 26 ns Q rr Reverse Recovery Charge 6.5 9.7 nc Conditions V GS = 0V, I D = 250µ Reference to 25 C, I D = m V GS = V, I D = e Conditions MOSFET symbol D showing the integral reverse G S p-n junction diode. T J = 25 C, I S = 8.2, V GS = 0V e T J = 25 C, I F = 8.2, V DD = V di/dt = 0/µs e 2 www.irf.com
I D, Drain-to-Source Current (Α) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current () I D, Drain-to-Source Current () IRF89PbF 0 VGS TOP V 8.0V 5.5V 4.5V 3.5V 3.0V 2.8V BOTTOM 2.5V 0 VGS TOP V 8.0V 5.5V 4.5V 3.5V 3.0V 2.8V BOTTOM 2.5V 0. 2.5V 60µs PULSE WIDTH Tj = 25 C 0.0 0. 0 V DS, Drain-to-Source Voltage (V) 2.5V 60µs PULSE WIDTH Tj = 50 C 0. 0 V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics 0.5 I D = V GS = V T J = 50 C.0 T J = 25 C 0. V DS = V 60µs PULSE WIDTH 2 3 4 5 6 V GS, Gate-to-Source Voltage (V) 0.5-60 -40-20 0 20 40 60 80 0 20 40 60 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature www.irf.com 3
I SD, Reverse Drain Current () I D, Drain-to-Source Current () C, Capacitance(pF) V GS, Gate-to-Source Voltage (V) IRF89PbF 000 V GS = 0V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd 6.0 5.0 I D = 8.2 V DS = 6V V DS = V 4.0 00 C iss 3.0 C oss 2.0 C rss.0 0 0 0.0 0 2 3 4 5 6 7 8 9 V DS, Drain-to-Source Voltage (V) Q G Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 0.00 00.00 T J = 50 C 0 OPERTION IN THIS RE LIMITED BY R DS (on).00 0µsec T J = 25 C 0. V GS = 0V 0.0 0.2 0.4 0.6 0.8.0.2.4.6 V SD, Source-to-Drain Voltage (V) 0. T = 25 C Tj = 50 C Single Pulse msec msec 0 0 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating rea 4 www.irf.com
I D, Drain Current () V GS(th) Gate threshold Voltage (V) IRF89PbF 2.5 9 8 7 6 5 2.0 I D = 250µ 4 3.5 2 0 25 50 75 0 25 50 T, mbient Temperature ( C).0-75 -50-25 0 25 50 75 0 25 50 T J, Temperature ( C ) Fig 9. Maximum Drain Current vs. mbient Temperature Fig. Threshold Voltage vs. Temperature 0 D = 0.50 Thermal Response ( Z thj ) 0. 0.0 0.20 0. 0.05 0.02 0.0 R R 2 R 3 R R 2 R 3 τ J τ J τ τ τ 2 τ 3 τ 2 τ 3 Ci= τi/ri Ci= τi/ri SINGLE PULSE ( THERML RESPONSE ) Notes:. Duty Factor D = t/t2 E-006 E-005 0.000 0.00 0.0 0. 0 t, Rectangular Pulse Duration (sec) R 4 R 4 τ 4 τ 4 R 5 R 5 τ 5 τ 5 τ C τ C Ri ( C/W) τi (sec).2647 0.00009 2.045 0.000776 8.970 0.88739 23.45 0.757700 6.803 25.000 2. Peak Tj = P dm x Zthja Tc Fig. Maximum Effective Transient Thermal Impedance, Junction-to-mbient www.irf.com 5
R DS(on), Drain-to -Source On Resistance (mω) E S, Single Pulse valanche Energy (mj) IRF89PbF 40.00 30.00 I D = 80 70 60 I D TOP 3.4 4.9 BOTTOM 8.2 50 20.00 T J = 25 C 40 30.00 T J = 25 C 20 0.00 3 4 5 6 7 8 9 V GS, Gate -to -Source Voltage (V) Fig 2. On-Resistance vs. Gate Voltage 0 25 50 75 0 25 50 Starting T J, Junction Temperature ( C) Fig 3. Maximum valanche Energy vs. Drain Current Current Regulator Same Type as D.U.T. V (BR)DSS 5V tp 50KΩ R G V DS 20V VGS tp L D.U.T I S 0.0Ω DRIVER - V DD I S 2V V GS.2µF 3m.3µF D.U.T. V - DS Fig 4. Unclamped Inductive Test Circuit and Waveform L D I G I D Current Sampling Resistors Fig 5. Gate Charge Test Circuit V DS V DD - V DS 90% D.U.T % V GS Pulse Width < µs Duty Factor < 0.% V GS t d(on) t r t d(off) t f Fig 6. Switching Time Test Circuit Fig 7. Switching Time Waveforms 6 www.irf.com
IRF89PbF - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-pplied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 5. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Vds Id Vgs Vgs(th) Qgs Qgs2 Qgd Qgodr Fig 6. Gate Charge Waveform www.irf.com 7
IRF89PbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q and Q2. Power losses in the high side switch Q, also called the Control FET, are impacted by the R ds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q are given by; P loss = P conduction P switching P drive P output This can be expanded and approximated by; P loss = ( I 2 rms R ds(on ) ) I Q gd V in f I Q gs 2 V in f i g ( ) Q g V g f Q oss 2 V in f This simplified loss equation includes the terms Q gs2 and Q oss which are new to Power MOSFET data sheets. Q gs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Q gs and Q gs2, can be seen from Fig 6. Q gs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to I dmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q. Q oss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure shows how Q oss is formed by the parallel combination of the voltage dependant (nonlinear) capacitance s C ds and C dg when multiplied by the power supply input buss voltage. i g Synchronous FET The power loss equation for Q2 is approximated by; * P loss = P conduction P drive P output ( ) P loss = I rms 2 R ds(on) ( ) Q g V g f Q oss 2 V f in Q V f rr in *dissipated primarily in Q. ( ) For the synchronous MOSFET Q2, R ds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Q oss and reverse recovery charge Q rr both generate losses that are transfered to Q and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and V in. s Q turns on and off there is a rate of change of drain voltage dv/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current. The ratio of Q gd /Q gs must be minimized to reduce the potential for Cdv/dt turn on. Figure : Q oss Characteristic 8 www.irf.com
IRF89PbF SO-8 Package Outline Dimensions are shown in milimeters (inches) E 6 6X D 5 8 7 6 5 2 3 4 e B H 0.25 [.0] INCHES DIM MIN MX.0532.0040.0688.0098 b.03.020 MILLIMETERS MIN MX.35.75 0. 0.25 0.33 0.5 c.0075.0098 0.9 0.25 D E.89.497.968.574 4.80 3.80 5.00 4.00 e.050 BSIC.27 BSIC e.025 BSIC 0.635 BSIC H.2284.2440 5.80 6.20 K.0099.096 0.25 0.50 L.06.050 0.40.27 y 0 8 0 8 e C y K x 45 8X b 0.25 [.0] C B 0. [.004] 8X L 7 8X c NOT ES :. DIMENSIONING & TOLERNCING PER SME Y4.5M-994. 2. CONTROLLING DIMENS ION: MILLIMETER 3. DIMENSIONS RE SHOWN IN MILLIMETERS [INCHES ]. 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS -02. 5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.5 [.006]. 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.0]. 7 DIMENSION IS THE LENGTH OF LED FOR SOLDERING TO S UBS TRTE. 6.46 [.255] 3X.27 [.050] F OOT PRINT 8X 0.72 [.028] 8X.78 [.070] SO-8 Part Marking Information (Lead-Free) EXMPLE: THIS IS N IRF7 (MOSFET) INTERNTIONL RECTIFIER LOGO XXXX F7 DTE CODE (YWW) P = DES IGNTES LED-FREE PRODUCT (OPTIONL) Y = LST DIGIT OF T HE YER WW = WEE K = S S EMB LY S ITE CODE LOT CODE PRT NUMBER www.irf.com 9
IRF89PbF SO-8 Tape and Reel Dimensions are shown in milimeters (inches) TERMINL NUMBER 2.3 (.484 ).7 (.46 ) 8. (.38 ) 7.9 (.32 ) FEED DIRECTION NOTES:. CONTROLLING DIMENSION : MILLIMETER. 2. LL DIMENSIONS RE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EI-48 & EI-54. 330.00 (2.992) MX. NOTES :. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EI-48 & EI-54. 4.40 (.566 ) 2.40 (.488 ) Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.57mH, R G = 25Ω, I S = 8.2. ƒ Pulse width 400µs; duty cycle 2%. When mounted on inch square copper board. R θ is measured at T J of approximately 90 C. Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR s Web site. IR WORLD HEDQURTERS: 233 Kansas St., El Segundo, California 90245, US Tel: (3) 252-75 TC Fax: (3) 252-7903 Visit us at www.irf.com for sales contact information. 08/04 www.irf.com