V DSS R DS(on) max Qg. 30V 3.2mΩ 36nC

Transcription

1 PD Applications l Optimized for UPS/Inverter Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Industrial use Benefits l Very Low RDS(on) at 4.5V l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current l Lead-Free HEXFET Power MOSFET V DSS R DS(on) max Qg 30V 3.2mΩ 36nC D S D G TO-220AB G D S Gate Drain Source Absolute Maximum Ratings V DS I T C = 25 C I T C = C I T C = 25 C I DM P C = 25 C P C = C T J T STG Drain-to-Source Voltage Gate-to-Source Voltage Parameter Continuous Drain V (Silicon Limited) Continuous Drain V (Silicon Limited) Continuous Drain V (Package Limited) Pulsed Drain Current c Maximum Power Dissipation h Maximum Power Dissipation h Linear Derating Factor Operating Junction and Storage Temperature Range Soldering Temperature, for seconds Mounting torque, 6-32 or M3 screwi Thermal Resistance Units Parameter Typ. Max. Units R θjc Junction-to-Case h 1.11 R θcs Case-to-Sink, Flat Greased Surface 0.5 C/W R θja Junction-to-Ambient g 62 Max. 30 ± f to (1.6mm from case) lbfxin (1.1Nxm) V A W W/ C C Notes through are on page /22/09

2 T J = 25 C (unless otherwise specified) Parameter Min. Typ. Max. Units BV DSS Drain-to-Source Breakdown Voltage 30 V ΒV DSS / T J Breakdown Voltage Temp. Coefficient 17 mv/ C R DS(on) Static Drain-to-Source On-Resistance mω = 4.5V, I D = 32A e (th) Gate Threshold Voltage V V (th) / T DS =, I D = µa J Gate Threshold Voltage Coefficient -7.7 mv/ C I DSS Drain-to-Source Leakage Current 1.0 V DS = 24V, = 0V µa V DS = 24V, = 0V, T J = 125 C I GSS Gate-to-Source Forward Leakage = 20V na Gate-to-Source Reverse Leakage - = -20V gfs Forward Transconductance 190 S V DS = 15V, I D = 32A Q g Total Gate Charge Q gs1 Pre-Vth Gate-to-Source Charge 9.1 V DS = 15V Q gs2 Post-Vth Gate-to-Source Charge 4.2 nc Q gd Gate-to-Drain Charge 13 Q godr Gate Charge Overdrive 13 Q sw Switch Charge (Q gs2 Q gd ) 17.2 Q oss Output Charge 21 nc R G Gate Resistance Ω t d(on) Turn-On Delay Time 23 t r Rise Time 92 t d(off) Turn-Off Delay Time 25 ns t f Fall Time 36 C iss Input Capacitance 51 C oss Output Capacitance 960 pf C rss Reverse Transfer Capacitance 440 Avalanche Characteristics Parameter Typ. Max. Units E AS Single Pulse Avalanche Energyd 3 mj I AR Avalanche Currentc 32 A E AR Repetitive Avalanche Energy c 14 mj Diode Characteristics Parameter Min. Typ. Max. Units Conditions = 0V, I D = 250µA Reference to 25 C, I D = 1mA = V, I D = 40A e = 4.5V I D = 32A V DS = 16V, = 0V V DD = 15V, = 4.5Ve I D = 32A R G = 1.8Ω = 0V V DS = 15V ƒ = 1.0MHz Conditions I S Continuous Source Current MOSFET symbol 150f (Body Diode) showing the A I SM Pulsed Source Current integral reverse 620 (Body Diode)c p-n junction diode. V SD Diode Forward Voltage 1.0 V T J = 25 C, I S = 32A, = 0V e t rr Reverse Recovery Time ns T J = 25 C, I F = 32A, V DD = 15V Q rr Reverse Recovery Charge nc di/dt = 200A/µs e t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LSLD) 2

3 I D, Drain-to-Source Current (A) R DS(on), Drain-to-Source On Resistance (Normalized) I D, Drain-to-Source Current (A) I D, Drain-to-Source Current (A) 0 VGS TOP V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V BOTTOM 3.0V 0 VGS TOP V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V BOTTOM 3.0V 3.0V 60µs PULSE WIDTH Tj = 25 C V DS, Drain-to-Source Voltage (V) 3.0V 60µs PULSE WIDTH Tj = 175 C V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 0 T J = 25 C T J = 175 C 2.0 I D = 78A = V V DS = 15V 60µs PULSE WIDTH , Gate-to-Source Voltage (V) T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature 3

4 I SD, Reverse Drain Current (A) I D, Drain-to-Source Current (A) C, Capacitance (pf), Gate-to-Source Voltage (V) = 0V, f = 1 MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd I D = 32A V DS = 24V V DS = 15V C iss 8.0 C oss C rss V DS, Drain-to-Source Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 0 00 T J = 175 C OPERATION IN THIS AREA LIMITED BY R DS (on) 0 1msec µsec T 1 J = 25 C = 0V V SD, Source-to-Drain Voltage (V) 1 Tc = 25 C Tj = 175 C Single Pulse msec DC 0 1 V DS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage Fig 8. Maximum Safe Operating Area 4

5 I D, Drain Current (A) (th), Gate Threshold Voltage (V) Limited By Package I D = µa I D = 250µA I D = 1.0mA T C, Case Temperature ( C) T J, Temperature ( C ) Fig 9. Maximum Drain Current vs. Case Temperature Fig. Threshold Voltage vs. Temperature Thermal Response ( Z thjc ) C/W D = SINGLE PULSE ( THERMAL RESPONSE ) τ J τ J τ 1 τ 1 τ 2 τ 2 τ 3 τ 3 Ci= τi/ri Ci i/ri R 1 R 2 R 3 R 1 R 2 R 3 Ri ( C/W) τi (sec) R 4 R Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc Tc E-006 1E t 1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 5 τ 4 τ 4 τ C τ

6 R DS(on), Drain-to -Source On Resistance (m Ω) E AS, Single Pulse Avalanche Energy (mj) I D = 40A I D TOP 11A 18A BOTTOM 32A T J = 125 C T J = 25 C , Gate -to -Source Voltage (V) Starting T J, Junction Temperature ( C) Fig 12. On-Resistance vs. Gate Voltage Fig 13c. Maximum Avalanche Energy vs. Drain Current 15V V DS R D V DS L DRIVER D.U.T. R G R G 20V tp D.U.T IAS 0.01Ω - V DD A Pulse Width 1 µs Duty Factor 0.1 % - V DD Fig 13a. Unclamped Inductive Test Circuit tp V (BR)DSS Fig 14a. Switching Time Test Circuit V DS 90% % t d(on) t r t d(off) t f I AS Fig 14b. Switching Time Waveforms Fig 13b. Unclamped Inductive Waveforms 6

7 - D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer - Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD - Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple 5% I SD * = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET Power MOSFETs Current Regulator Same Type as D.U.T. Id Vds 12V.2µF 50KΩ.3µF Vgs D.U.T. V - DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgodr Qgd Qgs2 Qgs1 Fig 16. Gate Charge Test Circuit Fig 17. Gate Charge Waveform 7

8 TO-220AB Package Outline (Dimensions are shown in millimeters (inches)) TO-220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at: 8

9 TO-220AB Part Marking Information (;$03/( 7,6,6$1,5) /27&2'( $66(0%/('21::,17($66(0%/</,1(& 1RWH3LQDVVHPEO\OLQHSRVLWLRQ LQGLFDWHV/HDG)UHH,17(51$7,21$/ 5(&7,),(5 /2*2 $66(0%/< /27&2'( 3$57180%(5 '$7(&2'( <($5 :((. /,1(& Note: For the most current drawing please refer to IR website at: Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting T J = 25 C, L = 0.61mH, R G = 25Ω, I AS = 32A. ƒ Pulse width 400µs; duty cycle 2%. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 78A. When mounted on 1" square PCB (FR-4 or G- Material). For recommended footprint and soldering techniques refer to application note #AN-994. R θ is measured at T J approximately 90 C. This is only applied to TO-220AB pakcage. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information.04/