W/ C V GS Gate-to-Source Voltage ± 30 dv/dt Peak Diode Recovery e V/ns T J. mj I AR

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1 PD 9675 Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dv/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dv/dt and di/dt Capability l LeadFree G D S V DSS HEXFET Power MOSFET 5V R DS(on) typ. max. 4.8m: 5.9m: I D (Silicon Limited) 7 D S D G TO247AC G D S Gate Drain Source Absolute Maximum Ratings Symbol Parameter Max. Units I T C = 25 C Continuous Drain Current, V V (Silicon Limited) 7 I T C = C Continuous Drain Current, V V (Silicon Limited) 2 A I DM Pulsed Drain Current c 684 P C = 25 C Maximum Power Dissipation 57 W Linear Derating Factor 3.45 W/ C V GS GatetoSource Voltage ± 3 V dv/dt Peak Diode Recovery e 8.5 V/ns T J Operating Junction and 55 to 75 T STG Storage Temperature Range Soldering Temperature, for seconds 3 C (.6mm from case) Mounting torque, 632 or M3 screw lbxin (.Nxm) Avalanche Characteristics E AS (Thermally limited) Single Pulse Avalanche Energy d 763 mj I AR Avalanche Currentc See Fig. 4, 5, 22a, 22b, A E AR Repetitive Avalanche Energy f mj Thermal Resistance Symbol Parameter Typ. Max. Units R θjc JunctiontoCase j.29 R θcs CasetoSink, Flat Greased Surface.24 R θja JunctiontoAmbient ij 4 C/W 9/8/8

2 (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units V (BR)DSS DraintoSource Breakdown Voltage 5 V V (BR)DSS / T J Breakdown Voltage Temp. Coefficient.7 V/ C R DS(on) Static DraintoSource OnResistance mω V GS(th) Gate Threshold Voltage V I DSS I GSS DraintoSource Leakage Current GatetoSource Forward Leakage 2 GatetoSource Reverse Leakage 25 µa na R G Internal Gate Resistance. Ω (unless otherwise specified) Symbol Parameter Min. Typ. Max. Units Conditions gfs Forward Transconductance 62 S V DS = 5V, I D = 3A Q g Total Gate Charge I D = 3A Q gs GatetoSource Charge 52 Q gd GatetoDrain ("Miller") Charge 55 Q sync Total Gate Charge Sync. (Q g Q gd ) 96 t d(on) TurnOn Delay Time 27 t r Rise Time 9 t d(off) TurnOff Delay Time 47 t f Fall Time 84 C iss Input Capacitance 47 C oss Output Capacitance 977 C rss Reverse Transfer Capacitance 23 C oss eff. (ER) Effective Output Capacitance (Energy Related) h 897 C oss eff. (TR) Effective Output Capacitance (Time Related)g 272 Diode Characteristics Symbol Parameter Min. Typ. Max. Units Conditions I S Continuous Source Current MOSFET symbol D 7 A (Body Diode) showing the I SM Pulsed Source Current integral reverse G 684 A (Body Diode)c S pn junction diode. V SD Diode Forward Voltage.3 V, I S = 3A, V GS = V f t rr Reverse Recovery Time V R = V, ns 33 I F = 3A Q rr Reverse Recovery Charge 55 di/dt = A/µs f nc 758 I RRM Reverse Recovery Current 8.8 A t on Forward TurnOn Time Intrinsic turnon time is negligible (turnon is dominated by LSLD) nc ns pf Conditions V GS = V, I D = 25µA Reference to 25 C, I D = 5mAc V GS = V, I D = 3A f V DS = V GS, I D = 25µA V DS =5V, V GS = V V DS = 5V, V GS = V, V GS = 2V V GS = 2V V DS = 75V V GS = V f I D = 3A, V DS =V, V GS = V f V DD = 98V I D =3A R G =.Ω V GS = V f V GS = V V DS = 5V ƒ =.MHz, (See Fig 5) V GS = V, V DS = V to 2V h(seefig.) V GS = V, V DS = V to 2V g Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by T Jmax, starting, L =.44mH R G = 25Ω, I AS = 3A, V GS =V. Part not recommended for use above this value. ƒ I SD 3A, di/dt 36A/µs, V DD V (BR)DSS, T J 75 C. Pulse width 4µs; duty cycle 2%. C oss eff. (TR) is a fixed capacitance that gives the same charging time as C oss while V DS is rising from to 8% V DSS. C oss eff. (ER) is a fixed capacitance that gives the same energy as C oss while V DS is rising from to 8% V DSS. When mounted on " square PCB (FR4 or G Material). For recom mended footprint and soldering techniques refer to application note #AN994. ˆ R θ is measured at T J approximately 9 C. 2

3 C, Capacitance (pf) V GS, GatetoSource Voltage (V) I D, DraintoSource Current (A) R DS(on), DraintoSource On Resistance (Normalized) I D, DraintoSource Current (A) I D, DraintoSource Current (A) VGS TOP 5V V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V VGS TOP 5V V 8.V 7.V 6.V 5.5V 5.V BOTTOM 4.5V. 6µs PULSE WIDTH Tj = 25 C 4.5V.. V DS, DraintoSource Voltage (V) 4.5V 6µs PULSE WIDTH Tj = 75 C. V DS, DraintoSource Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics T J = 75 C I D = 3A V GS = V 2..5 V DS = 5V 6µs PULSE WIDTH V GS, GatetoSource Voltage (V) Fig 3. Typical Transfer Characteristics T J, Junction Temperature ( C) Fig 4. Normalized OnResistance vs. Temperature V GS = V, f = MHZ C iss = C gs C gd, C ds SHORTED C rss = C gd C oss = C ds C gd C iss I D = 3A V DS = 2V V DS = 75V VDS= 3V C oss C rss V DS, DraintoSource Voltage (V) Q G, Total Gate Charge (nc) Fig 5. Typical Capacitance vs. DraintoSource Voltage Fig 6. Typical Gate Charge vs. GatetoSource Voltage 3

4 Energy (µj) E AS, Single Pulse Avalanche Energy (mj) V (BR)DSS, I D, Drain Current (A) DraintoSource Breakdown Voltage (V) I SD, Reverse Drain Current (A) I D, DraintoSource Current (A) T J = 75 C OPERATION IN THIS AREA LIMITED BY R DS (on) µsec msec DC msec V GS = V Tc = 25 C Tj = 75 C Single Pulse V SD, SourcetoDrain Voltage (V) Fig 7. Typical SourceDrain Diode Forward Voltage.. V DS, DraintoSource Voltage (V) Fig 8. Maximum Safe Operating Area Id = 5mA T C, Case Temperature ( C) Fig 9. Maximum Drain Current vs. Case Temperature T J, Temperature ( C ) Fig. DraintoSource Breakdown Voltage I D TOP 2.5A 29.3A BOTTOM 3A V DS, DraintoSource Voltage (V) Starting T J, Junction Temperature ( C) Fig. Typical C OSS Stored Energy Fig 2. Maximum Avalanche Energy vs. DrainCurrent 4

5 E AR, Avalanche Energy (mj) Avalanche Current (A) Thermal Response ( Z thjc ) C/W... D = SINGLE PULSE ( THERMAL RESPONSE ) τ J τ J τ τ τ 2 τ 3 τ 2 τ 3 Ci= τi/ri Ci i/ri R R 2 R 3 R R 2 R 3. E6 E5.... t, Rectangular Pulse Duration (sec) Fig 3. Maximum Effective Transient Thermal Impedance, JunctiontoCase τ C τ Ri ( C/W) τi (sec) Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc Tc Duty Cycle = Single Pulse. Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 5 C and Tstart =25 C (Single Pulse).5. Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Τj = 25 C and Tstart = 5 C...E6.E5.E4.E3.E2.E tav (sec) Fig 4. Typical Avalanche Current vs.pulsewidth TOP Single Pulse BOTTOM.% Duty Cycle I D = 3A Notes on Repetitive Avalanche Curves, Figures 4, 5: (For further info, see AN5 at Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of T jmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long ast jmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 6a, 6b. 4. P D (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (.3 factor accounts for voltage increase during avalanche). 6. I av = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed T jmax (assumed as 25 C in Figure 4, 5). t av = Average time in avalanche. D = Duty cycle in avalanche = t av f Z thjc (D, t av ) = Transient thermal resistance, see Figures 3) Starting T J, Junction Temperature ( C) Fig 5. Maximum Avalanche Energy vs. Temperature P D (ave) = /2 (.3 BV I av ) = DT/ Z thjc I av = 2DT/ [.3 BV Z th ] E AS (AR) = P D (ave) t av 5

6 Q RR (A) I RR (A) Q RR (A) V GS(th), Gate threshold Voltage (V) I RR (A) I F = 68A V R = V I D = 25µA I D =.ma ID =.A T J, Temperature ( C ) Fig 6. Threshold Voltage vs. Temperature di F /dt (A/µs) Fig. 7 Typical Recovery Current vs. di f /dt I F = 3A V R = V I F = 68A V R = V di F /dt (A/µs) Fig. 8 Typical Recovery Current vs. di f /dt di F /dt (A/µs) Fig. 9 Typical Stored Charge vs. di f /dt I F = 3A V R = V di F /dt (A/µs) Fig. 2 Typical Stored Charge vs. di f /dt 6

7 D.U.T ƒ Circuit Layout Considerations Low Stray Inductance Ground Plane Low Leakage Inductance Current Transformer Reverse Recovery Current Driver Gate Drive Period P.W. D.U.T. I SD Waveform Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt D = P.W. Period V GS =V V DD * R G dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. Device Under Test V DD ReApplied Voltage Body Diode Inductor Curent Current Forward Drop Ripple 5% I SD * V GS = 5V for Logic Level Devices Fig 2. Peak Diode Recovery dv/dt Test Circuit for NChannel HEXFET Power MOSFETs 5V tp V (BR)DSS V DS L DRIVER R G 2V V GS tp D.U.T IAS.Ω V DD A I AS Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms V DS R D V DS V GS D.U.T. 9% R G V DD VV GS Pulse Width µs Duty Factor. % % V GS t d(on) t r t d(off) t f Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms Current Regulator Same Type as D.U.T. Vds Id 5KΩ Vgs 2V.2µF.3µF V GS D.U.T. V DS Vgs(th) 3mA I G I D Current Sampling Resistors Qgs Qgs2 Qgd Qgodr Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform 7

8 TO247AC Package Outline Dimensions are shown in millimeters (inches) TO247AC Part Marking Information I r)qv h r iy yv rƒ v v v qvph r GrhqA rr GPBP 2! TO247AC package is not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 9245, USA Tel: (3) TAC Fax: (3) Visit us at for sales contact information. 9/28 8

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