Storage Temperature Range Soldering Temperature, for 10 seconds 300 (1.6mm from case )
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1 PD IRLR/U2905PbF Logic-Leve Gate Drive Utra Low On-Resistance Surface Mount (IRLR2905) Straight Lead (IRLU2905) dvanced Process Technoogy Fast Switching Fuy vaanche Rated Lead-Free G HEXFET Power MOSFET D S V DSS = 55V R DS(on) = 0.027Ω I D = 42 Description Fifth Generation HEXFETs from Internationa Rectifier utiize advanced processing techniques to achieve the owest possibe on-resistance per siicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are we known for, provides the designer with an extremey efficient device for use in a wide variety of appications. The D-PK is designed for surface mounting using vapor phase, infrared, or wave sodering techniques. The straight ead version (IRFU series) is for through-hoe mounting appications. Power dissipation eves up to 1.5 watts are possibe in typica surface mount appications. bsoute Maximum Ratings Therma Resistance D-Pak TO-252 I-Pak TO-251 Parameter Max. Units I T C = 25 C Continuous Drain Current, V V 42 I T C = 0 C Continuous Drain Current, V V 30 I DM Pused Drain Current 160 P C = 25 C Power Dissipation 1 W Linear Derating Factor 0.71 W/ C V GS Gate-to-Source Votage ± 16 V E S Singe Puse vaanche Energy 2 mj I R vaanche Current 25 E R Repetitive vaanche Energy 11 mj dv/dt Peak Diode Recovery dv/dt ƒ 5.0 V/ns T J Operating Junction and -55 to 175 T STG Storage Temperature Range Sodering Temperature, for seconds 300 (1.6mm from case ) C Parameter Typ. Max. Units R θjc Junction-to-Case 1.4 R θj Case-to-mbient (PCB mount)** 50 C/W R θj Junction-to-mbient 1 ** When mounted on 1" square PCB (FR-4 or G- Materia ). For recommended footprint and sodering techniques refer to appication note #N /7/04
2 Eectrica T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage 55 V V GS = 0V, I D = 250µ V (BR)DSS/ T J Breakdown Votage Temp. Coefficient V/ C Reference to 25 C, I D = 1m V GS = V, I D = 25 R DS(on) Static Drain-to-Source On-Resistance W V GS = 5.0V, I D = V GS = 4.0V, I D = 21 V GS(th) Gate Threshod Votage V V DS = V GS, I D = 250µ g fs Forward Transconductance 21 S V DS = 25V, I D = 25 I DSS Drain-to-Source Leakage Current 25 V DS = 55V, V GS = 0V µ 250 V DS = 44V, V GS = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage 0 V GS = 16V n Gate-to-Source Reverse Leakage -0 V GS = -16V Q g Tota Gate Charge 48 I D = 25 Q gs Gate-to-Source Charge 8.6 nc V DS = 44V Q gd Gate-to-Drain ("Mier") Charge 25 V GS = 5.0V, See Fig. 6 and 13 t d(on) Turn-On Deay Time 11 V DD = 28V t r Rise Time 84 I ns D = 25 t d(off) Turn-Off Deay Time 26 R G = 3.4Ω, V GS = 5.0V t f Fa Time 15 R D = 1.1Ω, See Fig. L D Interna Drain Inductance 4.5 nh Between ead, 6mm (0.25in.) L S Interna Source Inductance 7.5 G from package and center of die contact C iss Input Capacitance 1700 V GS = 0V C oss Output Capacitance 400 pf V DS = 25V C rss Reverse Transfer Capacitance 150 ƒ = 1.0MHz, See Fig. 5 D S Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 42 (Body Diode) showing the G I SM Pused Source Current integra reverse 160 (Body Diode) p-n junction diode. S V SD Diode Forward Votage 1.3 V T J = 25 C, I S = 25, V GS = 0V t rr Reverse Recovery Time ns T J = 25 C, I F = 25 Q rr Reverse RecoveryCharge nc di/dt = 0/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S L D ) Notes: Repetitive rating; puse width imited by max. junction temperature. ( See fig. 11 ) V DD = 25V, starting T J = 25 C, L =470µH R G = 25Ω, I S = 25. (See Figure 12) ƒ I SD 25, di/dt 270/µs, V DD V (BR)DSS, T J 175 C Puse width 300µs; duty cyce 2%. Cacuated continuous current based on maximum aowabe junction temperature; Package imitation current = 20. This is appied for I-PK, L S of D-PK is measured between ead and center of die contact. Uses IRLZ44N data and test conditions. 2
3 I D, Drain-to-Source Current () 00 0 VGS TOP 15V 12V V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V I D, Drain-to-Source Current () 00 0 VGS TOP 15V 12V V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V 2.5V 20µs PULSE WIDTH 1 T J = 25 C V DS, Drain-to-Source Votage (V) 20µs PULSE WIDTH 1 T J = 175 C V DS, Drain-to-Source Votage (V) Fig 1. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, Drain-to-Source Current () 00 0 T = 25 C J T = 175 C J V DS= 25V 20µs PULSE WIDTH V GS, Gate-to-Source Votage (V) R DS(on), Drain-to-Source On Resistance (Normaized) I D = 41 V GS = V T J, Junction Temperature ( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized On-Resistance Vs. Temperature 3
4 C, Capacitance (pf) 2800 V GS = 0V, f = 1MHz C iss = C gs C gd, C ds SHORTED 2400 C rss = Cgd C = C C C iss oss ds gd Coss 800 C rss V DS, Drain-to-Source Votage (V) V GS, Gate-to-Source Votage (V) I D = 25 V DS = 44V V DS = 28V FOR TEST CIRCUIT SEE FIGURE Q, Tota Gate Charge (nc) G Fig 5. Typica Capacitance Vs. Drain-to-Source Votage Fig 6. Typica Gate Charge Vs. Gate-to-Source Votage I SD, Reverse Drain Current () 00 0 T = 175 C J T = 25 C J V GS = 0V V SD, Source-to-Drain Votage (V) I D, Drain Current () 00 OPERTION IN THIS RE LIMITED BY RDS(on) 0 µs 0µs 1ms T C = 25 C ms T J = 175 C Singe Puse V DS, Drain-to-Source Votage (V) Fig 7. Typica Source-Drain Diode Forward Votage Fig 8. Maximum Safe Operating rea 4
5 50 LIMITED BY PCKGE V DS R D I D, Drain Current () R G V GS 5V Puse Width 1 µs Duty Factor 0.1 % D.U.T. Fig a. Switching Time Test Circuit - V DD V DS 90% T C, Case Temperature ( C) Fig 9. Maximum Drain Current Vs. Case Temperature % V GS t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Therma Response (Z thjc ) D = SINGLE PULSE (THERML RESPONSE) Notes: 1. Duty factor D = t 1 / t Peak T J= P DM x Z thjc TC t 1, Rectanguar Puse Duration (sec) PDM t1 t2 Fig 11. Maximum Effective Transient Therma Impedance, Junction-to-Case 5
6 15V V DS L DRIVER R G 20V D.U.T I S - V DD tp 0.01Ω Fig 12a. Uncamped Inductive Test Circuit V (BR)DSS tp E S, Singe Puse vaanche Energy (mj) TOP BOTTOM Fig 12c. Maximum vaanche Energy Vs. Drain Current ID V DD = 25V Starting T J, Junction Temperature ( C) I S Fig 12b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF V Q GS Q GD D.U.T. V - DS V G V GS 3m Charge I G I D Current Samping Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6
7 Peak Diode Recovery dv/dt Test Circuit D.U.T ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - - R G dv/dt controed by R G Driver same type as D.U.T. I SD controed by Duty Factor "D" D.U.T. - Device Under Test - V DD Driver Gate Drive Period P.W. D = P.W. Period V GS =V * D.U.T. I SD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt V DD Re-ppied Votage Inductor Curent Body Diode Forward Drop Rippe 5% I SD * V GS = 5V for Logic Leve Devices Fig 14. For N-Channe HEXFETS 7
8 D-Pak (TO-252) Package Outine Dimensions are shown in miimeters (inches) D-Pak (TO-252) Part Marking Information EXMPLE: THIS IS N IRFR120 WITH SSEMBLY LOT CODE 1234 SSEMBLED ON WW 16, 1999 IN THE SSEMBLY LINE "" Note: "P" in assemby ine position indicates "Lead-Free" INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRFU PRT NUMBER DTE CODE YER 9 = 1999 WEEK 16 LINE OR INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRFU PRT NUMBER DTE CODE P = DESIGNTES LED-FREE PRODUCT (OPTIONL) YER 9 = 1999 WEEK 16 = SSEMBLY SITE CODE 8
9 I-Pak (TO-251) Package Outine Dimensions are shown in miimeters (inches) I-Pak (TO-251) Part Marking Information EXMPLE: THIS IS N IRFU120 WITH SSEMBLY LOT CODE 5678 SSEMBLED ON WW 19, 1999 IN THE SSEMBLY LINE "" Note: "P" in assemby ine position indicates "Lead-Free" INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRFU PRT NUMBER DTE CODE YER 9 = 1999 WEEK 19 LINE OR INTERNTIONL RECTIFIER LOGO SSEMBLY LOT CODE IRFU PRT NUMBER DTE CODE P = DES IGNT E S LE D-F REE PRODUCT (OPTIONL) YER 9 = 1999 WEEK 19 = SSEMBLY SITE CODE 9
10 D-Pak (TO-252) Tape & Ree Information Dimensions are shown in miimeters (inches) TR TRR TRL 16.3 (.641 ) 15.7 (.619 ) 16.3 (.641 ) 15.7 (.619 ) 12.1 (.476 ) 11.9 (.469 ) FEED DIRECTION 8.1 (.318 ) 7.9 (.312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. LL DIMENSIONS RE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EI-481 & EI INCH NOTES : 1. OUTLINE CONFORMS TO EI mm IR WORLD HEDQURTERS: 233 Kansas St., E Segundo, Caifornia 90245, US Te: (3) TC Fax: (3) Visit us at for saes contact information. Data and specifications subject to change without notice. 12/04
11 Note: For the most current drawings pease refer to the IR website at:
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l LogicLevel Gate rive l dvanced Process Technology l ynamic dv/dt Rating l 75 C Operating Temperature l Fast Switching l Fully valanche Rated escription Fifth Generation HEXFETs from International Rectifier
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