APPENDIX-I. Synchronous communication creation



Similar documents
More Verilog. 8-bit Register with Synchronous Reset. Shift Register Example. N-bit Register with Asynchronous Reset.

Let s put together a Manual Processor

Chapter 8. Sequential Circuits for Registers and Counters

ECE232: Hardware Organization and Design. Part 3: Verilog Tutorial. Basic Verilog

Modeling Sequential Elements with Verilog. Prof. Chien-Nan Liu TEL: ext: Sequential Circuit

Sistemas Digitais I LESI - 2º ano

16-bit ALU, Register File and Memory Write Interface

ECE 3401 Lecture 7. Concurrent Statements & Sequential Statements (Process)

List of Experiment. 8. To study and verify the BCD to Seven Segments DECODER.(IC-7447).

DEPARTMENT OF INFORMATION TECHNLOGY

Lab #5: Design Example: Keypad Scanner and Encoder - Part 1 (120 pts)

5 Combinatorial Components. 5.0 Full adder. Full subtractor

Binary Adders: Half Adders and Full Adders

ECE 451 Verilog Exercises. Sept 14, James Barnes

Using Ladder Logic Instructions to Communicate with an Ethernet IP Nexus Unit

Understanding Logic Design

Moving from C++ to VBA

COMBINATIONAL CIRCUITS

A single register, called the accumulator, stores the. operand before the operation, and stores the result. Add y # add y from memory to the acc

United States Naval Academy Electrical and Computer Engineering Department. EC262 Exam 1

Fondamenti di C++ - Cay Horstmann 1

MS Visual C++ Introduction. Quick Introduction. A1 Visual C++

The irnetbox Manager User Guide

如 何 在 C#.2005 中 使 用 ICPDAS I/O Card 的 DLL 檔 案

Application Note 120 Communicating Through the 1-Wire Master

CHAPTER 3 Boolean Algebra and Digital Logic

LAB #4 Sequential Logic, Latches, Flip-Flops, Shift Registers, and Counters

QUIZ-II QUIZ-II. Chapter 5: Control Structures II (Repetition) Objectives. Objectives (cont d.) 20/11/2015. EEE 117 Computer Programming Fall

NEW adder cells are useful for designing larger circuits despite increase in transistor count by four per cell.

LFSR BASED COUNTERS AVINASH AJANE, B.E. A technical report submitted to the Graduate School. in partial fulfillment of the requirements

Digital Design Verification

Lesson 12 Sequential Circuits: Flip-Flops

Chapter 5 :: Memory and Logic Arrays

Computer organization

CS 61C: Great Ideas in Computer Architecture Finite State Machines. Machine Interpreta4on

Digital Logic Design Sequential circuits

Subnetting,Supernetting, VLSM & CIDR

Anybus OPC Server. Application Note. Doc.Id. SCM Rev HMS Industrial Networks AB

Understanding Verilog Blocking and Non-blocking Assignments

U-HID Pac-LED64 PacDrive U-HID LEDs

BINARY CODED DECIMAL: B.C.D.

PFB366 Profibus-DP Gateway User Manual

Introduction to Programming (in C++) Loops. Jordi Cortadella, Ricard Gavaldà, Fernando Orejas Dept. of Computer Science, UPC

Example. Introduction to Programming (in C++) Loops. The while statement. Write the numbers 1 N. Assume the following specification:

SSC - Communication and Networking Java Socket Programming (II)

Idle Data Analysis & Charts for the Draft 3 ENERGY STAR Computer Server Specification 10/31//08

Ethernet Module Manual

Systems I: Computer Organization and Architecture

Lesson 10: Video-Out Interface

UvA facelab 5 extension for Presentation

Digital Electronics Part I Combinational and Sequential Logic. Dr. I. J. Wassell

ARM Thumb Microcontrollers. Application Note. Software ISO 7816 I/O Line Implementation. Features. Introduction

CIA405.lib. Contents. WAGO-I/O-PRO 32 Library

Prefix AggregaNon. Company X and Company Y connect to the same ISP, and they are assigned the prefixes:

MS Active Sync: Sync with External Memory Files

Below is a diagram explaining the data packet and the timing related to the mouse clock while receiving a byte from the PS-2 mouse:

DIGITAL DESIGN FLOW OPTIONS

CDA 3200 Digital Systems. Instructor: Dr. Janusz Zalewski Developed by: Dr. Dahai Guo Spring 2012

PCM Encoding and Decoding:

Chapter 13: Verification

Two's Complement Adder/Subtractor Lab L03

Training Document for Comprehensive Automation Solutions Totally Integrated Automation (T I A) MODULE E05

Multipliers. Introduction

COMPUTER SCIENCE 1999 (Delhi Board)

Logic in Computer Science: Logic Gates

A Step by Step Guide for Building an Ozeki VoIP SIP Softphone

Micro800 Programmable Controllers: Getting Started with CIP Client Messaging

PLC-ANALYZER pro 5. PLC-Driver Siemens SIMATIC S5 Industrial Ethernet TCP/IP. Driver-Addendum. The logic analyzer for programmable logic controls

Chapter 7D The Java Virtual Machine

Modeling Registers and Counters

First Java Programs. V. Paúl Pauca. CSC 111D Fall, Department of Computer Science Wake Forest University. Introduction to Computer Science

AlazarTech SDK Programmer s Guide. Version May 28, 2010

Develop a Dallas 1-Wire Master Using the Z8F1680 Series of MCUs

Preparing the Windows version of the software for use

EZ-ZONE RMA & EtherNet/IP Configuration & Startup Using an Allen-Bradley CompactLogix PLC EtherNet/IP Fundamentals

3.5. cmsg Developer s Guide. Data Acquisition Group JEFFERSON LAB. Version

Lotus Notes 6.x Client Installation Guide for Windows. Information Technology Services. CSULB

Xilinx ISE. <Release Version: 10.1i> Tutorial. Department of Electrical and Computer Engineering State University of New York New Paltz

Computer Organization and Components

CA ARCserve and CA XOsoft r12.5 Best Practices for protecting Microsoft SQL Server

Name: Class: Date: 9. The compiler ignores all comments they are there strictly for the convenience of anyone reading the program.

CCNA Discovery Networking for Homes and Small Businesses Student Packet Tracer Lab Manual

Application Note AN0008. Data Logging Extension. For. Venus 8 GPS Receiver

Registers & Counters

Diploma in Computer Hardware Maintenance and Network Technologies(DCHMNT)

MBP_MSTR: Modbus Plus Master 12

Experiment # 9. Clock generator circuits & Counters. Eng. Waleed Y. Mousa

Binary full adder. 2-bit ripple-carry adder. CSE 370 Spring 2006 Introduction to Digital Design Lecture 12: Adders

Verification & Design Techniques Used in a Graduate Level VHDL Course

L5354 ControlNet Communications Interface

DB19. 4-Bit Parallel Adder/ Subtractor. Digital Lab Experiment Board Ver. 1.0

AKD EtherNet/IP Communication

Using SolarWinds Orion for Cisco Assessments

Commissioning IDENTControl Compact IC-KP2-2HB17-2V1D Profinet Protocol with a Siemens S7 PLC

Transcription:

130 Synchronous communication creation module rom8*8(y,in); output [7:0] y; input [2:0] in; reg [2:0] ROM [7:0]; assign y=rom[in]; initial $readme mb( rom_data.txt,rom,0,7); module module fs32_test(); reg [2:0] testvectors[8:0]; reg clk; reg [10:0]N,err; reg a,b,c; fs d_t,e_t; fs32 DUT(a,b,c,d_t,e_t); initial begin $readmemb( testvectors_fs32.txt,testvectors); N=0;err=0; always begin clk=0; #50; clk=1; #50; APPENDIX-I always @(posedge clk)begin a=testvectors[n][0]; b=testvectors[n][1]; c=testvectors[n][2]; always @(nedge clk)begin N=N+1; $display( inputs %b%b%b-output %b%b,a,b,c,d_t,e_t); always @(N)begin if(n==100 testvectors[n}===3 bx)begin $display( Completed %d tests with %d errors,n,err); $finish; module module fs32(x,y,bin,diff,bout); input x; input y; input bin; output diff; output bout; assign diff=x^y^bin;

131 assign bout=(y&bin) ((y bin)&(~x)); module 2. RA One s and Two s complement module module complement s (d, clk, q); input d; input clk; output q; flip [N-1:0] q1; dff dff1(d,clk,q1[0]); dff dff1(q1[0],clk,q1[1]); dff dff1(q1[1],clk,q1[2]); dff dff1(q1[n-1],clk,q); dff dff1(q1[n],clk q) module module dff(d,clk,q); input d; input clk; output q; reg q; always @(posedge clk) q=d; module (i) Adder and subtractor module fa(a,b,cin,sum,cout); input [N:0]a; input [N:0]b; input cin; output [N:0] sum; output cout; fa[n-1:0] c1; fa fa1(a[0],b[0],cin, sum[0],c1[0]); fa fa2(a[1],b[1],c1[0], sum[1],c1[1]); fa fa(a[n-1],b[n-1],c1[1], sum[n-1],c1[n-1]); fa fa4(a[n],b[n],c1[n-1], sum[n],cout); module module fa (a,b,cin,sum,cout); input a; input b; input cin; output sum; output cout; fa s1,c1,c2; xor xor1(s1,a,b); xor xor2(sum,s1,cin); and and1(c1,a,b); and and2(c2,s1,cin); or or1(cout,c1,c2); module

132 Resolving host in self-healing hardware APPENDIX-II namespace NetPinger public partial class IPScanForm : Form private IPScanner _scanner; private class HostSorterByIP : IComparer public int Compare(object x, object y) byte[ ] bytes1 =(IPScanHostState)((ListViewItem)x).Tag).Address.GetAddressBytes(); byte[ ] bytes2 = ((IPScanHostState)((ListViewItem)y).Tag).Address.GetAddressBytes(); int i = bytes1.length - 1; for (; i > 0 && bytes1[i] == bytes2[i]; i--); return bytes1[i] - bytes2[i]; }} public IPScanForm() InitializeComponent(); _scanner = new IPScanner((int)_spnConcurrentPings.Value, (int)_spnpingsperscan.value, _cbcontinuousscan.checked, (int)_spntimeout.value, (int)_spnttl.value, _cbdontfragment.checked, (int)_spnbuffersize.value); _scanner.onalivehostfound += new IPScanner.AliveHostFoundDelegate(_scanner_OnAliveHostFound); _scanner.onstartscan += new IPScanner.ScanStateChangeDelegate(_scanner_OnStartScan); _scanner.onstopscan += new IPScanner.ScanStateChangeDelegate(_scanner_OnStopScan); _scanner.onrestartscan += new IPScanner.ScanStateChangeDelegate(_scanner_OnRestartScan); _scanner.onscanprogressupdate += new IPScanner.ScanProgressUpdateDelegate(_scanner_OnScanProgressUpdate); _lvalivehosts.listviewitemsorter = new HostSorterByIP(); _cmbrangetype.selectedindex = 0; } private void _scanner_onalivehostfound(ipscanner scanner, IPScanHostState host) if (InvokeRequired) BeginInvoke(new IPScanner.AliveHostFoundDelegate(_scanner_OnAliveHostFound), scanner, host); return; } ListViewItem item = new ListViewItem(); item.tag = host; item.backcolor = Color.GreenYellow; item.subitems.add(host.address.tostring()); item.subitems.add(""); item.subitems.add(""); item.subitems.add(""); _lvalivehosts.items.add(item); _lvalivehosts.sort(); host.onhostnameavailable += new IPScanHostState.HostNameAvailableDelegate(host_OnHostNameAvailable); host.onstatechange += new IPScanHostState.StateChangeDelegate(host_OnStateChange); if (!host.istesting())

133 item.imageindex = (int)host.qualitycategory; item.subitems[2].text = host.avgresponsetime.tostring("f02") + " ms"; item.subitems[3].text = ((float)(host.losscount) / host.pingscount).tostring("p"); item.subitems[4].text = host.hostname; } 2. Power analysis of self-healing hardware with IP Scanner #region IPScanRange Public class IPScanRange #region Start Private IPAddress_start; Public IPAddress Start get return_start;}} public IPScanner(int concurrentpings, int pingsperscan, bool continuousscan); public IPScanner(int concurrentpings, int pingsperscan, bool continuousscan, int timeout); public IPScanner(int concurrentpings, int pingsperscan, bool continuousscan, int timeout, int ttl, bool dontfragment, int pingbuffersize); IPScanRange(IPAddress start, IPAddress ); IPScanRange(IPAddress start, int subnet); #region

134 Appix-III Data synchronizing function of master module Double_5 S y = zeros(1,5); y(1) = 112; y(2) = 111.9991999; y(3) = 154524; y(4) = 11147.9991999; y(5) = 11241521.123455789; uint16 S y=uint16(1120); uint8_2 S y = uint8(zeros(1,2)); y(1) = uint8(hex2dec('aa')); y(2) = uint8(hex2dec('ff')); uint16_9 s y = uint16(zeros(1,9)); y(1) = uint16(hex2dec('aaff')); y(2) = uint16(hex2dec('ff00')); y(3) = uint16(hex2dec('55f0')); y(4) = uint16(hex2dec('aaaa')); y(5) = uint16(hex2dec('ffff')); y(6) = uint16(hex2dec('f520')); y(7) = uint16(hex2dec('aabc')); y(8) = uint16(hex2dec('ffed')); y(9) = uint16(hex2dec('f052')); uint32_10 S y = uint32(zeros(1,10)); y(1) = uint32(hex2dec('ee33aaff')); y(2) = uint32(hex2dec('ff001423')); y(3) = uint32(hex2dec('f0d5a400')); y(4) = uint32(hex2dec('aaaa1111')); y(5) = uint32(hex2dec('ffffbbbb'));

135 y(6) = uint32(hex2dec('f520aaaa')); y(7) = uint32(hex2dec('aabe4a6c')); y(8) = uint32(hex2dec('ffed2563')); y(9) = uint32(hex2dec('f052aaaa')); y(10) = uint32(1234567890); double_2 S y=zeros(1,2); y(1)=1; y(2)=1; double_2 Receive function [x, y] = fcn(u) x = u(2); y = u(1); double_5 Receive y = uint8(abs(u(1) - 112) < 1e-6 && abs(u(2) - 111.9991999) < 1e-6 &&... abs(u(3) - 154524) < 1e-6 && abs(u(4) - 11147.9991999) < 1e-6 &&... abs(u(5) - 11241521.123455789) < 1e-6); u(1) = 0; u(2) = 0; u(3) = 0; u(4) = 0; u(5) = 0; unit16 Receive y = uint8(uint16(1120)== u); u = uint16(0); Uint8_2 Receive y = uint8(uint8(hex2dec('aa')) == u(1) && uint8(hex2dec('ff')) == u(2)); Uint16_9 Receive

136 y = uint8(u(1) == uint16(hex2dec('aaff')) && u(2) == uint16(hex2dec('ff00')) &&... u(3) == uint16(hex2dec('55f0')) && u(4) == uint16(hex2dec('aaaa')) &&... u(5) == uint16(hex2dec('ffff')) && u(6) == uint16(hex2dec('f520')) &&... u(7) == uint16(hex2dec('aabc')) && u(8) == uint16(hex2dec('ffed')) &&... u(9) == uint16(hex2dec('f052'))); u(3)=0; u(4)=0; u(5)=0; u(6)=0; u(7)=0; u(8)=0; u(9)=0; uint32_10 Receive y = uint8(u(1) == uint32(hex2dec('ee33aaff')) && u(2) == uint32(hex2dec('ff001423')) &&... u(3) == uint32(hex2dec('f0d5a400')) && u(4) == uint32(hex2dec('aaaa1111')) &&... u(5) == uint32(hex2dec('ffffbbbb')) && u(6) == uint32(hex2dec('f520aaaa')) &&... u(7) == uint32(hex2dec('aabe4a6c')) && u(8) == uint32(hex2dec('ffed2563')) &&... u(9) == uint32(hex2dec('f052aaaa')) && u(10) == uint32(1234567890)); u(3)=0; u(4)=0; u(5)=0; u(6)=0; u(7)=0; u(8)=0; u(9)=0; u(10)=0; AND function y = fcn(t,u,v,w,z) if(uint8(t) && uint8(z) && uint8(u) && uint8(v) && uint8(w)) y=uint8(1); else y=uint8(0);

137 Appix-IV Data synchronizing function of slave module Double_5 S y = double(zeros(1,5)); y(1) = double(112); y(2)= double(111.9991999); y(3) = double(154524); y(4)= double(11147.9991999); y(5) = double(11241521.123455789); uint16 S y=uint16(1120); uint8_2 S y = uint8(zeros(1,2)); y(1) = uint8(hex2dec('aa')); y(2) = uint8(hex2dec('ff')); uint16_9 S y = uint16(zeros(1,9)); y(1) = uint16(hex2dec('aaff')); y(2) = uint16(hex2dec('ff00')); y(3) = uint16(hex2dec('55f0')); y(4) = uint16(hex2dec('aaaa')); y(5) = uint16(hex2dec('ffff')); y(6) = uint16(hex2dec('f520')); y(7) = uint16(hex2dec('aabc')); y(8) = uint16(hex2dec('ffed')); y(9) = uint16(hex2dec('f052')); uint32_10 y = uint32(zeros(1,10)); y(1) = uint32(hex2dec('ee33aaff')); y(2) = uint32(hex2dec('ff001423')); y(3) = uint32(hex2dec('f0d5a400')); y(4) = uint32(hex2dec('aaaa1111')); y(5) = uint32(hex2dec('ffffbbbb')); y(6) = uint32(hex2dec('f520aaaa')); y(7) = uint32(hex2dec('aabe4a6c'));

138 y(8) = uint32(hex2dec('ffed2563')); y(9) = uint32(hex2dec('f052aaaa')); y(10) = uint32(1234567890); double_2 S function y = fcn(u,v ) y = zeros(1,2); y(1) = u; y(2) = v; double_5 Receive y = uint8(abs(u(1) - double(112)) < 1e-6 && abs(u(2) - double(111.9991999)) < 1e-6 &&... abs(u(3) - double(154524)) < 1e-6 && abs(u(4) - double(11147.9991999)) < 1e-6 &&... abs(u(5) - double(11241521.123455789)) < 1e-6); u(3)=0; u(4)=0; u(5)=0; uint16 Receive y = uint8(uint16(1120)== u); u = uint16(0); uint8_3 Receive y = uint8(uint8(hex2dec('aa')) == u(1) && uint8(hex2dec('ff')) == u(2)); unit16_9 Receive y = uint8(u(1) == uint16(hex2dec('aaff')) && u(2) == uint16(hex2dec('ff00')) &&... u(3) == uint16(hex2dec('55f0')) && u(4) == uint16(hex2dec('aaaa')) &&... u(5) == uint16(hex2dec('ffff')) && u(6) == uint16(hex2dec('f520')) &&... u(7) == uint16(hex2dec('aabc')) && u(8) == uint16(hex2dec('ffed')) &&... u(9) == uint16(hex2dec('f052')));

139 u(3)=0; u(4)=0; u(5)=0; u(6)=0; u(7)=0; u(8)=0; u(9)=0; uint32_10 Receive y = uint8(u(1) == uint32(hex2dec('ee33aaff')) && u(2) == uint32(hex2dec('ff001423')) &&... u(3) == uint32(hex2dec('f0d5a400')) && u(4) == uint32(hex2dec('aaaa1111')) &&... u(5) == uint32(hex2dec('ffffbbbb')) && u(6) == uint32(hex2dec('f520aaaa')) &&... u(7) == uint32(hex2dec('aabe4a6c')) && u(8) == uint32(hex2dec('ffed2563')) &&... u(9) == uint32(hex2dec('f052aaaa')) && u(10) == uint32(1234567890)); u(3)=0; u(4)=0; u(5)=0; u(6)=0; u(7)=0; u(8)=0; u(9)=0; u(10)=0; double_2 Receive function [x, y] = fcn(u) x = uint8(u(1)); y = uint8(u(2)); AND function y = fcn(t,u,v,w,z) if(uint8(t) && uint8(z) && uint8(u) && uint8(v) && uint8(w)) y=uint8(1); else y=uint8(0);

2026 © DocPlayer.net Privacy Policy | Terms of Service | Feedback  | Do Not Sell My Personal Information