ovon-neumann Architecture oinstruction execution in Von Neumann Architecture ovon Neumann Architecture s limitation oharvard Architecture 1
VON NEUMANN ARCHITECTURE Von Neumann, a mathematician and early computer scientist described a design architecture for electronic digital computer. He was the first to spell out the requirements for a general purpose electronic computer. The architecture is still alive in the basis of modern computers 2
VON NEUMANN ARCHITECTURE To Von Neumann, the key to building a general purpose device was in its ability to store the instructions (along with data and temporary results) in it. In a special purpose machine the computational procedure could be part of the hardware. In General purpose computers instructions must be changeable. Instruction are encoded into numeric form and stored in memory 3
VON NEUMANN ARCHITECTURE Major organs of Von Neumann architecture: Memory o The arithmetic logic unit o The control unit o The memory o The input-output devices Control Unit ALU Input / Output 4
VON NEUMANN ARCHITECTURE Von Neumann general purpose computer is a programmable machine that: o Store a set of coded instruction along with data in its memory. o Respond to instructions in a well defined manner(sequential or told otherwise). 5
INSTRUCTION AND PROGRAM o Set of instruction is called program. o Memory can be loaded with new programs. An instruction is a binary coded command to perform a specific task: o Arithmetic and Logic Instruction. o Looping and decision making. o Transfer of data. o Transfer of control. 6
EXECUTION OF INSTRUCTION Instruction execution in Von Neumann computer oget the coded instruction. odecode the instruction. oget the operand. operform the desired operation. ocommunicate the results back. 7
COMPONENTS OF VON NEUMANN COMPUTER o Memory: to store program and data. o Program Counter: to execute instructions in order. oinstruction Decoder: to decode the binary coded instructions. oarithmetic Logic Unit: to perform logical and arithmetic operations. oinputs/outputs: to give the results back i. Store Respond a set to of instructions coded instruction a well along defined with manner(sequential data in its memory. told oregisters: Temporary data storage otherwise). Instruction Decoder Memory ALU Program counter Input / Outputs 8
INSTRUCTION FORMAT Instruction Format Opcode Operand1 Operand2 0 3 4 15 Instruction: Add with register Opcode : 0011 or 3 Operand : address of memory location, register or constant 9
VON NEUMANN ARCHITECTURE CPU Memory Execution unit ALU Registers Both data and instructions at the same system bus IO units BU System bus IR PC Controller Control unit
EXECUTION UNIT The number of bits in the execution unit usually denotes the processor s size For example an 8-bit processor stores 8-bits in registers and performs 8-bit operations in the ALU. The execution unit comprise: - ALU Aritmethic Logic Unit Performs arithmetic (+-*/) and logical calculations - Registers Intermediate storing of results BU Processor Execution unit ALU Registers IR PC Controller Controller unit
2 N is the number of adressable memory positions Address (N-1:0) Bus unit Processor Execution unit Data (M-1:0) ALU Registers Control Request Acknowlege Read/Write Etc. System bus Unique signals for each processor bus BU IR PC Controller Control unit
CONTROL UNIT, REGISTERS The control unit comprise of: - IR, the instruction register stores the instruction that is executed - PC, the program counter stores the adress to the executing instruction - Controller, controls the other parts (registers, bus unit och execution unit BE Processor Execution unit ALU Registers IR PC Controller Control unit
Memory 10: 23: $55 INSTRUCTION EXECUTION ADD $23,reg1 Data (opcode) 0011 (03) from memory, equalizes the instruction ADD 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 03 $23,reg1 Processor Execution unit ALU Registers Set the address bus to 10, the control bus to read IO units BU Read data from address 10 of program space. IR: 03 PC: 10 Controller Control unit Fetch instruction
Memory 10: 23: $55 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 03 $23,reg1 IO units INSTRUCTION EXECUTION ADD $23,reg1 ADD $23,reg1 is the instruction that is to be executed BU ADD $23,reg1 Processor Execution unit ALU Control unit Registers Decode the machine code 3 to an instruction IR: 03 PC: 10 Controller Instruction decoder $3 Fetch instr. Decode instr.
Memory 10: 23: $55 INSTRUCTION EXECUTION Data ($55) from memory 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 03 $23,reg1 ADD $23,reg1 Processor Execution unit ALU Value from reg1 Registers Set the address bus to $23, the control bus to read IO units Read data from address $23 BU Control unit Fetch instr. Decode instr. Fetch operand ADD $23,reg1 IR PC: 10 Controller
INSTRUCTION EXECUTION ADD $23,reg1 Memory 10: 23: $55 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 03 $23,reg1 The content in memory position ($23)=55 is added with the content in reg1: reg1 +$55 Processor Exekveringsenhet ALU Registers IO units Add reg1 and value from memory BU IR PC: 10 Controller Control unit Fetch instr. Decode instr. Fetch operand Execute
Memory 10: 23: $55 INSTRUCTION EXECUTION ADD $23,reg1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 03 $23,reg1 The result of the addition is written to register reg1 reg1 +$55 => reg1 Processor Exececution unit ALU Registers IO units Save the result in register reg1 BU IR PC: 10 Controller Control unit Fetch instr. Decode instr. Fetch operand Execute Write result
INSTRUCTION EXECUTION ADD $23,reg1 Processor Memory 10: $73 (ADD $23,reg1) 23: $55 Execution unit ALU Registers IO units BU IR PC: 10 Controller Control unit Fetch instr. Decode instr. Fetch operand Execute Write result
VON NEUMANN LIMITATION The shared bus between the program memory and data memory leads to the Von Neumann bottleneck. Because program memory and data memory cannot be accessed at the same time, throughput is much smaller than the rate at which the CPU can work. The CPU is continuously forced to wait for needed data to be transferred to or from memory. For example if we try to read an operand at the same time as we try to read an instruction. This is not possible in the von Neumann architecture since we only have one system bus and cannot address two memory positions simultaneously. 20
Other Architectures HARVARD ARCHITECTURE In the Harvard architecture this is solved by having two separate system buses: oone for instructions oone for data odata and instructions can be loaded simultaneously, which improves the efficiency. Means more I/O signals. omore expensive processor. ouses more power. Is used internally in modern 32-bit microprocessors and RISC processors. Program Memory CPU Program system Bus Computer Memory Data system Bus IOs 21
MICROPROCESSOR SYSTEM DESIGN General Purpose Computer e.g PC A general-purpose computer, such as a personal computer (PC), is designed to be flexible and to meet a wide range of end-user needs. Embedded Systems An embedded system is designed and optimized to perform a specific task very efficiently. They are different in: o Resources o Real time. o Robustness o Outer world interaction (IOs) o Program structure 22
MICROPROCESSOR SYSTEM DESIGN Embedded Systems Microprocessor based systems: An embedded system is designed and optimized to perform a specific task very efficiently. A microprocessor is an integrated implementation of central processing unit portion (CPU). Use separate integrated circuits for memory and peripherals. 23
MICROPROCESSOR SYSTEM DESIGN Embedded Systems Microcontroller based systems: A microcontroller brings together a microprocessor core and a rich collection of peripherals and IO capability into single integrated circuit. An embedded system is designed and optimized to perform a specific task very efficiently. Reduces cost and size. Timers, ADC, DAC, DIO, serial and parallel communication channels, DMA 24
INSTRUCTION ADDRESSING MODES Instruction Architecture Opcode Operand1 Operand2 0 3 4 15 Instruction: Add with register Opcode : 0011 or 3 Operand : address of memory location, register or constant RISC vs CISC Addressing modes 25
Components in a microprocessor system PROCESSOR TYPES: CISC (Complex Instruction Set Computer) othe primary goal of CISC architecture is to complete a task in as few lines of assembly as possible. othis is achieved by building processor hardware that is capable of understanding and executing a series of operations. o"mult. When executed, this instruction loads the two values into separate registers, multiplies the operands in the execution unit, and then stores the product in the appropriate register. Thus, the entire task of multiplying two numbers can be completed with one instruction: omult 2:3, 5:2 26
Components in a microprocessor system REDUCED INSTRUCTION SET COMPUTING RISC (Reduced Instruction Set Computer) orisc processors only use simple instructions that can be executed within one clock cycle. o Thus, the "MULT" command described above could be divided into three separate commands: oload, which moves data from the memory bank to a register, oprod, which finds the product of two operands located within the registers. ostore, which moves data from a register to the memory banks. oa programmer would need to code four lines of assembly: LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A 27
Components in a microprocessor system MEMORY: To store data or instructions the computer system uses a socalled primary memory The executable program code and data is stored in main memory. The primary memory is divided in two main parts The memory can be seen as a number of post boxes o RAM o ROM 28
Von Neumann Architecture MICROCONTROLLERS What does a computer system comprise: oprocessor (CPU, Central Processing Unit) omemory operipheral units, I/O osystem bus, to communicate with peripheral units If we have a chip that comprise all this it is often called a Micro Controller CPU Primary Memory RAM ROM I/O unit The outer world/ The user 29
Components in a microprocessor system PROCESSOR SYSTEM BUS Data bus ocommunication channel to move data to and from CPU and peripheral units. Address bus oused to point out which memory position or IO port that is to be read or written. Control signals o Used to signal when a data transaction starts and stops. o For example signals if a transaction is a read or write operation. 30
REFERENCES Lecture slides: Benny Thörnberg, Mattias O Nils Video Lecture: Prof. Anshul Kumar http://www.computersciencelab.com/computerhistory/history.htm Webopedia http://www.world-war-2-planes.com/american-world-war-2-planes.html (slide 12) http://www.anvari.org/cols/typewritter_ascii_art/steam_engine_number_3.html (slide 10) http://www.old-computers.com/history/detail.asp?n=61 (slide 15) http://www.freewebs.com/computingstudies/s1_ut_systems/s1utsystems_07.ht m http://www.computer-museum.org/index.html http://www.ucdsb.on.ca/school/sla/aboutus/pages/examschedule.aspx http://www.youtube.com/watch?v=aqbymrs3ocs Camera Pills Use MEMS Micro Reed Sensors to Activate the Battery http://en.wikipedia.org/wiki http://www-cs-faculty.stanford.edu/~eroberts/courses/soco/projects/risc/risccisc/ 31