COMPUTER ARCHITECTURE. Input/Output

Transcription

1 HUMBOLDT-UNIVERSITÄT ZU BERLIN INSTITUT FÜR INFORMATIK COMPUTER ARCHITECTURE Lecture 17 Input/Output Sommersemester 2002 Leitung: Prof. Dr. Miroslaw Malek CA - XVII - I/O - 1

2 INPUT/OUTPUT Input/Output problem Secondary memory technology (magnetic, optical) I/O device selection (addressing) I/O protocols Data transfer mechanism Synchronization mechanism (Readings: Chapter 6 of HVZ.) CA - XVII - I/O - 2

3 INPUT/OUTPUT Historically a neglected subject within computer architecture Many benchmarks ignore I/O Getting attention in the last few years Increasing gap between CPU, Memory and I/O speeds A bottleneck in high-end machines Relative cost of "peripherals" is increasing (Very Large Scale Insanity) Cost distribution! CA - XVII - I/O - 3

4 INPUT/OUTPUT PROBLEM Factors that make interfacing difficult The encoding of the transmitted word must be that which is employed by the I/O device. Operating Rates The CPU and Main Memory operate at many times the speed of I/O devices Timing and Control Exchange of status signals between CPU and device. Rate of transmission from device to CPU or vice-versa. Communication Link (Word Length) There are at least 25 different word lengths used in computers. The word lengths vary from 4 to 128 bits. The separation (or combination) of words (because of word length) into characters, bytes or other units presents a "word assembly" problem. CA - XVII - I/O - 4

5 WORD-LENGTH DIFFERENCES The output "word" must be the correct word length for the output device. Transmission by: Serial-by-Bit Serial-by-Character (Byte) - (quasiparallel) Serial-by-Word - (parallel) Device 1 Computer or DEVICE 1 DEVICE 2 Input device Device 2 Output device or Computer T1 T2 T3 T x CA - XVII - I/O - 5

6 Device Operating Speed Device Proximity to Processor Local Remote DESIGN Design depends on Link Cost Remote (Communications Cost/Speed) Control is embedded in message train Parallel: Prevention of Skewing Serial: Clocking and Synchronization Errors Factors Prevention CA - XVII - I/O - 6

7 IN SUMMARY AN INPUT/OUTPUT PROBLEM INVOLVES ENCODING/CODES OPERATING RATES TIMING AND CONTROL COMMUNICATION LINK STRUCTURES (WORD LENGTH) ERRORS CA - XVII - I/O - 7

8 TIMING AND CONTROL Central processor may simultaneously communicate with one or more of its external devices. seldom with all usually in no set pattern (randomness) different speeds required for different devices CA - XVII - I/O - 8

9 TYPICAL SEQUENCE OF CPU Select desired external device Determine the device's status Signal device to connect itself to the processor Receive acknowledgment from device that it is connected Request device to initiate input (or output) and begin data exchange Recognize "ready signal". Each data unit is read (or output) by the device and the device signals completion of the step by giving a "ready to exchange next data unit" signal Repeat previous operation until an end of message condition is detected Logically disconnect CA - XVII - I/O - 9

10 FACTORS CONTRIBUTING TO ERRORS (1) ENVIRONMENT DIRT, MOISTURE (OPTICAL, MAGNETIC, MECHANICAL) TEMPERATURE/HUMIDITY ELECTROMAGNETIC RADIATION ELECTRIC POWER SURGES COMPONENT AGING CIRCUIT PARAMETERS DRIFT MECHANICAL WEAR SKEW CA - XVII - I/O - 10

11 FACTORS CONTRIBUTING TO ERRORS (2) SYSTEM "BUGS UNANTICIPATED SEQUENCE OF INSTRUCTIONS AND CODE COMBINATIONS INCORRECT MEMORY ALLOCATION, I/O BUFFER SIZE EXCEEDED INCOMPLETELY PLANNED AND TESTED SYSTEM MODULE COMBINATIONS USER MISTAKES MISSEQUENCING OF PROGRAMS INCORRECT PROCEDURES INCORRECT MOUNTING OF STORAGE MEDIA CA - XVII - I/O - 11

12 INPUT/OUTPUT ORGANIZATION ADDRESSING Input/Output Function Select I/O Device Exchange Data "units" with Device (Data Transfer) Synchronize (Coordinate) timing of I/O operations Addressing of I/O Devices Each Device assigned Identification code, or Address Within address capability of the machine Usually block assignment Logical circuits (Memory not enable) CPU sends address on address line, Device responds Data Transfer CA - XVII - I/O - 12

13 DATA TRANSFER 1 Program controlled I/O addressable buffer register Use normal op-codes Interface Address Decoding Control Circuits Data Register, Status Register 2 Block transfer of data to Main Memory space. Direct Memory Access (DMA) Concept is to provide circuitry to transfer data, a word at a time, consistent with the device speed and automatically sequence the transfer using registers in the DMA controller. 3 I/O Using DMA requires a program Load registers Load function (Read/Write) Issue GO command CA - XVII - I/O - 13

14 DATA TRANSFER (continued) 4 Connection of DMA (control with memory means memory has to be shared between CPU and I/O devices) A memory bus controller must be provided to coordinate memory usage Cycle stealing is the process of interweaving I/O priorities between microoperations in the execution of an instruction CA - XVII - I/O - 14

15 SYNCHRONIZATION POLLING The CPU must have some means to coordinate its external devices The CPU has to know the status of devices and when events occur Basically two methods are used; Polling (status checking) and interrupts Polling (status checking) Data Lines Control Lines Check Status (1) Holding Input (2) Ready for Output CA - XVII - I/O - 15

16 INTERRUPTS General term used in a loose sense for any infrequent or exceptional event that causes a CPU to make a temporary transfer of control from its current program to another program that services the event I/O interrupt are used to: request CPU to initiate a new I/O operation signal completion of I/O operation signal occurrence of hardware / software errors Frees CPU from "polling" duties CA - XVII - I/O - 16

17 INTERRUPT A typical interrupt sequence is as follows: The CPU executes a program sequence A special signal, Interrupt Request, is received by the CPU The CPU acknowledges the interrupt and stops execution,(usually after an instruction cycle) of its current program and stores registers in memory (at a minimum the Program Counter (PC) and the Prorgram Status Word (PSW) The CPU's program counter (PC) is set to a new address where an Interrupt Service Routine resides The CPU performs execution as normal Note: that another interrupt sequence could be initiated while the CPU is performing the service routine Interrupt masks may be set to prevent the latter from occurring CA - XVII - I/O - 17

18 INTERRUPT (continued) The CPU may return to the original program sequence when a special return from interrupt (RTI) instruction is executed. In such case the registers saved in Step c are restored and the program counter (PC) address is then held when the interrupt was acknowledged at Step c The concept of an Interrupt is general. Interrupts may be initiated from Internal operation codes Arithmetic or logical errors External events Interrupts greatly facilitate operating systems where control needs to be transferred back to the operating system when various events occur Several interrupts may happen within a short period of time and we need methods of handling the interrupts through priority systems CA - XVII - I/O - 18

19 SIMPLE INTERRUPT STRUCTURE to control logic for automatic subroutine jump CAR 1 0 Device number encoder S R Enable interrupt flip flop 0 1 R ENI S Channel interrupt flip flop ENI - enable interrupt CPU Channel AND other control units Device selector decoder Device command decoder 0 1 R S OR other control units Device flip flop interrupt Device request Channel Device Control unit CA - XVII - I/O - 19

20 INTERRUPT HANDLING There are several types and sources of interrupts They have different priorities Need to screen interrupts use INTEnable; INTDisable commands Need to service acknowledged interrupt first identify interrupting device Vectored interrupt: IO device provides address of interrupt service routine (and other information) Automatically disable other interrupts before starting interrupt service routine What if interrupting device hangs? Nested interrupts - a higher priority interrupt can be acknowledged and serviced from within the routine of a lower priority interrupt CA - XVII - I/O - 20

21 A SYSTEM WITH VECTORED I/O INTERRUPTS CPU INT REQ 3 INT REQ 2 INT REQ 1 INT REQ 0 Data bus IO port 0 IO port 1 IO port 2 IO port 3 IO device A Output device B Input device C CA - XVII - I/O - 21

22 LOCATION OF THE INTERRUPT SERVICING PROGRAM IN MAIN MEMORY G o to 4 G o to 2 0 G o to G o to D e v ic e A in p u t ro u tin e D e v ic e A o u tp u t ro u tin e D e v ic e B s e rv ic e ro u tin e D e v ic e C s e rv ic e ro u tin e CA - XVII - I/O - 22

23 I/O Bus DEVICE CONTROL UNIT TYPICAL I/O INTERFACE device selector bus data and status bus I/O control bus Address lines Data lines Control lines Address decoder Data and status register Control circuit I/O Interface Input devices FUNCTIONS (I/O) SELECT I/O DEVICE EXCHANGE "DATA UNITS" WITH DEVICE (DATA TRANSFER) SYNCHRONIZE (COORDINATE) TIMING OF I/O OPERATIONS. CA - XVII - I/O - 23

24 DEVICE CONTROL UNIT There are four types of I/O buses to all I/O control devices I/O Data Bus Data I/O Data Register (IODR) I/O Device Selector Bus Device Code Selector Circuit I/O Command Bus CommandDecoder Available Status Bus Line through which timing signals are sent to CPU Usually, I/O Data Bus is combined with the Available Status Bus Device Selector Decoder (AND gate with inverters) Device Command Decoder Logical Decoder to select function CA - XVII - I/O - 24

25 DEVICE CONTROL UNIT (cont.) Device Available Flip Flop Sets the available Status bus to 0" while Device operation logic is on Sets the Status bus to "1" when sensor on the device indicates action is completed Status codes Device Ready Busy Disconnected Power Not On Operation Completed Parity Error Detected during transmission Tape not mounted etc. I/O Channels Selector (High Speed) Multiplexer (Byte) Block Multiplexers Channel Programs Control Words Registers CA - XVII - I/O - 25

26 I/O PROCESSING METHODS MEMORY CPU CHANNEL CONTROL UNIT I/O 1. Program controlled 2. Direct Memory Access (DMA) 3. Selector 4. Character Mux (Byte) 5. Block mux (Burst) CA - XVII - I/O - 26

27 PROGRAMMED I/O Begin LDA OSEL 1 DEVICE CODE STA SELECT SELECT DEVICE REGISTER LDA # -10 STA CNT SET COUNT=-10 WAIT TST OSTATUS CHECK OUTPUT STATUS REGISTER, BPL WAIT IF STATUS PLUS WAIT STATUS WORD LDA CHAR+ PICK UP CHARACTER, INCREMENT ADDRESS STA OBUFF STORE CHARACTER IN OUTPUT BUFFER INC CNT CNT=CNT+1, = -9 ETC. BNZ WAIT OUTPUT NEXT CHARACTER (BRANCH NON ZERO) END HALT END OF OUTPUT CA - XVII - I/O - 27

28 TYPICAL I/O INTERFACE I/O 1 CPU MEMORY I/O n I/O BUS CA - XVII - I/O - 28

29 IO operation initiated by CPU DMA ACCESS Example: to transfer a block of data, need four instructions: Load MAR Load word count Read/Write GO On task completion DMA informs CPU through an interrupt IO operation initiated by I/O device DMA request sent to CPU Request granted at the next DMA breakpoint DMA must have (occasional) control of system bus CA - XVII - I/O - 29

30 CYCLE STEALING Both CPU and DMA controller need the system bus to access memory. Who gets priority? DMA block transfer: an entire block is transferred in a single continuous burst needed for magnetic-disk drives etc. Where data transmission cannot be stopped or slowed down without loss of data supports maximum IO data-transmission rate may starve CPU for relatively long periods Cycle stealing DMA steals memory cycles from CPU, transferring one or a few words at a time before returning control Thus memory and CPU bus transactions are interwoven Reduces interference in CPU's activities Reduces I/O transfer rate CA - XVII - I/O - 30

31 BUS ORGANIZATION FOR DIRECT MEMORY ACCESS A) Single-bus structure Bus CPU Main memory Memory address counter register Word counter DMA controller device Memory data buffer Control register and circuits CA - XVII - I/O - 31

32 BUS ORGANIZATION FOR DIRECT MEMORY ACCESS B) Two-bus structure with a "floating" DMA controller Main memory Memory bus CPU DMA controller I/O device I/O device I/O Bus CA - XVII - I/O - 32

33 CIRCUITRY REQUIRED FOR DIRECT MEMORY ACCESS (DMA) Address Main memory Data AR AC DC IOAR IODR IR CPU Control unit DMA request DMA acknowledge Control unit I/O device CA - XVII - I/O - 33

34 DMA AND INTERRUPT BREAKPOINTS DURING AN INSTRUCTION CYCLE Instruction cycle CPU cycle Fetch instruction Decode instruction Fetch operand Execute instruction Store result DMA breakpoints Interrupt breakpoint CA - XVII - I/O - 34

35 I/O BUSSES Data Bus Control Unit Available Status Bus Command Bus Selector Bus Control Unit I/O Selector Decoder S0 S1 S2 S3 S4 S5 Detect (D) D = S5 S4 S3 S2 S1 S0 CA - XVII - I/O - 35

36 I/O SUBSYSTEMS IN MAINFRAMES Main memory banks Memory control unit Channel 1 Channel Channel Channel Magnetic disk control unit Magnetic disk control unit Printer and reader control unit Tape storage control unit etc. Disk unit 1 Disk unit 1 Printer 1 Disk unit 2 Disk unit 2 Printer 2 To tape units Disk unit N Disk unit N CA - XVII - I/O - 36

37 ORGANIZATION OF A SELECTOR CHANNEL Device address register Byte count register Memory data address register Parallel to byte serial conversion Memory data buffer To I/O control units Byte-serial interface Channel control 16, 32 or 64 bits parallel interface To main memory CA - XVII - I/O - 37

38 ORGANIZATION OF A MULTIPLEXOR CHANNEL Subchannel 1 To I/O Control Units Subchannel n Subchannel 1 Character Buffer Status Hardwired memory address Memory data buffer Channel control to Main Memory CA - XVII - I/O - 38

39 CONVENTIONAL COMPUTER ARCHITECTURE Main Memory Central processor Console Human Operator CPU Multiplexor Channel Selector Channel Selector Channel Channel bus IFC IFC... IFC IFC... IFC MCS IFC... IFC L L M H IFC H H H H H H H IFC - Interface Controller MCS - Multi Channel Switch L - Low-speed device M - medium-speed device H - High-speed device CA - XVII - I/O - 39

40 TYPES OF CHANNELS Selector - exclusive I/O path for a single High-speed (H) program selected device Character Multiplexor - momentary I/O path for a single Medium-speed (M) program selected device (Burst Mode) or - time shared character interleaved path for several Low-speed (L) devices (Byte Mode). Block Multiplexor - momentary exclusive path to a single High-speed (H) device (Selector Mode) or - provides a time shared, block interleave path for several High-speed (H) or buffer devices (Multiplex Mode) CA - XVII - I/O - 40

41 CHARACTER MULTIPLEXOR I/O A A A A B B B B C C C C Byte Multiplex Mode C A B C C A B C To Main Memory I/O A A A A B B B B C C C C Byte Burst Mode C C C C C C C C To Main Memory CA - XVII - I/O - 41

42 Functions INPUT/OUTPUT INSTRUCTIONS 1. Select a particular device. 2. Specify the first address in memory to or from which data are to be transferred. 3. Specify the number of words which are to be transferred. 4. Select the read or write (R/W) function. Instructions EXTERNAL FUNCTION X The contents of address X contains the code for one of the I/O devices which is connected to the I/O register and also a code for the operation to be performed. READ X Transfer the contents of the I/O register to memory location X. CONNECT X This is another form of the external function instruction. If a machine has several channels, this instruction may also specify which channel is used as well as the device to be connected and the function. CA - XVII - I/O - 42

43 INPUT/OUTPUT INSTRUCTIONS (cont.) DISCONNECT X This disconnects the device from the computer and terminates the I/O operation. COPY STATUS X Transfer the contents of the I/O control register, IOCR, to memory location X. This contains the status of the I/O device. STATUS REQUEST X This requests the status of a device to be placed into the IOCR. The COPY STATUS X instruction then transfers the status to a location in memory where it can be examined by a program. READ X,Y Transfer X number of words from a device which has been connected to the CPU by a previous CONNECT X instruction into consecutive memory locations starting with location Y. This instruction is usually used with a computer which has a direct memory access type of channel. CA - XVII - I/O - 43

44 USE PRIORITY ARBITRATION CIRCUIT CPU INTR0 INTR1 Device 1 Device 2 Device p INTA1 INTAp Priority arbiration circuit CA - XVII - I/O - 44

45 THE INTEL 8255 PROGRAMMABLE PERIPHERAL INTERFACE CIRCUIT 8080 data bus 8-bit Data internal buffer bus A 4 C A CPU address lines READ WRITE A A 0 1 Control logic Control register C B B IO devices Data buffers CA - XVII - I/O - 45

46 TYPICAL BUS STANDARDS VME bus Future Bus Multibus II IPI SCSI Bus width (signals) Address/data Not multiplexed Multiplexed Multiplexed N/A N/A multiplexed Data width 16 to 32 bits 32 bits 32 bits 16 bits 8 bits (primary) Transfer size Single or multiple Single or multiple Single or multiple Single or multiple Single or multiple Number of bus Multiple Multiple Multiple Single Multiple masters Split transaction No Optional Optional Optional Optional Clocking Asynchronous Asynchronous Synchronous Asynchronous Either Bandwidth, 0-ns access memory, single word 25.0 MB/sec 37.0 MB/sec 25.0 MB/sec 5.0 MB/sec or 1.5 MB/sec Bandwidth, 150-ns access memory, single word 12.9 MB/sec 15.5 MB/sec 10.0 MB/sec 25.0 MB/sec 5.0 MB/sec or 1.5 MB/sec CA - XVII - I/O - 46

47 Bandwidth, 0-ns access memory, multiple words (infinite block length) Bandwidth, 150- ns access memory, multiple words (infinite block length) Maximum number of devices Maximum bus TYPICAL BUS STANDARDS (cont.) VME bus Future Bus Multibus II IPI SCSI 27.9 MB/sec 95.2 MB/sec 40.0 MB/sec 25.0 MB/sec 5.0 MB/sec or 1.5 MB/sec 13.6 MB/sec 20.8 MB/sec 13.5 MB/sec 25.0 MB/sec 5.0 MB/sec or 1.5 MB/sec meter 0.5 meter 0.5 meter 50 meters 25 meters length Standard IEEE 1014 IEEE ANSI/IEEE 1296 ANSI X3.129 ANSI X3.131 The first three were defined originally as CPU-memory buses and the last two as I/O buses. For the CPUmemory buses the bandwidth calculations assume a fully loaded bus and are given to both single-word transfers and block transfers of unlimited length; measurements are shown both ignoring memory latency and assuming 150-ns access time. Bandwidth assumes the average distance of a transfer is on-third of the backplane length. (Data in the first three columns is from Borril [1986]), the Bandwidth for the I/O buses is given as their maximum data transfer rate. There are new bus technologies on the PC-Market nowadays, such as PCI and AGP buses. CA - XVII - I/O - 47

48 SUMMARY - matching CPU and I/O speeds remains to be a problem - adding separate CPU s on channels ad devices - remarkable technology advances (e.g., flat screen displays, but a 100 year old keyboard remains to be a popular input device) - I/O remains to be the most expensive part of computer systems Current challenges - further miniaturization - access to information at any place and time at high speeds (e.g., wearable computers) - development of new I/O devices, new sensors,... CA - XVII - I/O - 48