A Power Efficient Multiplexer and Flip-Flop Design Using Modified NAND Gate Radhika.T 1, Lakshmisree P.V 2 1 PG Scholar,M.Tech VLSI Design, t.radhika1@gmail.com,n.c.e.r.c,pampady, Thrissur,Kerala, India 2 Assistant Professor/ ECE, lakshmisri.venu@gmail.com, N.C.E.R.C, Pampady, Thrissur, Kerala, India Abstract The design of CMOS VLSI circuits is becoming more complex as the leakage power consumption is posing a serious issue nowadays. Technological modification, reduction of threshold voltage and device geometry contributes to leakage power. In the proposed approach two digital circuits have been designed. A JK Master-Slave Flip-flop and 4*1 MUX designed using 2 Input NAND combining Gate sleepy stack with RBB and Dual Threshold CMOS(DTCMOS) and dynamic power consumption has been measured with sleep switches on and static power consumption has been measured by switching off the sleep switches. On comparison with conventional 4*1 multiplexer a maximum of 40% decrement is achieved in dynamic power consumption and 69% decrement in power consumption when circuit is in ideal state. For JK master-slave flip-flop 15% reduction in dynamic power consumption and 99% saving in static power consumption is achieved. All simulations have been done on 65nm technology with dual threshold transistors. Keywords: Reverse body bias, Dual threshold Transistor, Sleepy stack, Power Delay Product. 1. Introduction The reduction of technology to micron level has made leakage power a serious issue for design of CMOS VLSI circuits [1]. The major cause of leakage power is threshold voltage variations [2] and device geometry. Supply voltage scaling has improved the energy per operation as dynamic power is approximately proportional to square of supply voltage. Higher operating frequencies and higher transistor densities trigger Dynamic power consumption. Whereas reduced gate length, oxide thickness and threshold voltage cause an exponential rise in leakage power consumption. In near future power consumption due to leakage will domain over dynamic power consumption. Designing the circuit to have equal input and output rise and fall time the short circuit power consumption can be reduced. For designs with feature size larger than 1m dynamic power consumption is dominant. The load capacitance decrements when the feature size decreases due to technology reduction. The minimization of load capacitance reduces the dynamic power drastically as load capacitance is a major part of clocking network. Thus minimization of size reduces the supply voltage. Voltage scaling technique however has increased delay as supply voltage almost advance to threshold voltage for designs with feature size larger than 1um.Lealkage power minimization by varying threshold is by varying the substrate bias voltage[3]. However with this technique stacking cannot be done and it incurs higher delay. 2. Existing Work Existing method for power consumption for multiplexers and JK Flip Flop includes modifying the clock pulses by applying either edge triggered or level triggered clock pulses. The edge triggered flip flops change state at rising or falling edge of clock pulses depending upon control input [4]. When the clock level is high the inputs change the outputs, which is the major concern for level triggered flip flops. There is double edge triggered flipflops where the width of the pulses is made thrice that of an inverter at rising and falling edges. Gate Diffusion Input 1
(GDI) technique has been used for the design of various digital circuits where area power consumption and delay is reduced by ensuring less complexity of the design. Multiplexer has been designed based on the GDI technique which is power efficient [4]. 3. Proposed Work In the proposed work a JK Master Slave flip flop and 4*1 Multiplexer is designed using modified NAND gate. The NAND gate is designed by combining Sleepy stack technique with RBB and DTCMOS. By keeping sleep switches on the dynamic power consumption is measured and by keeping them off static power consumption is measured. Fig1. Proposed 2 input NAND Gate The NAND gate designed by combining sleepy stack approach with RBB and DTCMOS achieves utmost leakage power consumption, lesser delay and better dynamic power consumption. In active mode leakage power is measured with sleep switches S1 and S2 ON and in ideal state they are kept OFF by cutting off the path from supply to ground. In the sleepy stack technique the existing transistor is broken down in to two half size transistors without altering the logic of the design. Sleepy stack technique gives higher leakage power consumption with stack approach. Combining sleep transistor during active mode and stack approach during sleep mode is the main ideology behind sleepy stack technique, thus achieving high leakage power reduction. The Reverse Body Bias (RBB) technique is a method to reduce the leakage by controlling the threshold voltage. Voltage will be given to the body which controls the leakage [6].Threshold is either increased or decreased to control leakage. It is increased for PMOS devices and decreased for NMOS devices. The Dual Threshold CMOS (DTCMOS) consists of input transistors that can receive certain input. The body of one transistor will be connected to gate of another transistor. The transistors that receive signals that arrive later will be received with a lesser threshold caused by the early arrived input signal. Thus leakage is reduced with the use of DTCMOS. JK Master Slave flip flop and 4*1 MUX with the proposed NAND gate is designed as shown in fig 2 and fig 3 respectively. 2
Fig2. JK Master Slave flip flop using Proposed NAND gate Fig 3.4*1 Multiplexer Based on Proposed NAND Gate The JK Master Slave flip flop comprises of a master and a slave that are two discrete clocked flip flops. When there is transition to disable level by the clock the flip flop responds. The inputs to the gates at the master is Clock C and the inputs to the gate at the Slave is clock complement.when Clock (C=1) then Clock Complement (C ) and vice versa. Gates 3A and 3B are disabled when gates 1A and 1B are enabled and vice versa. To measure the leakage power the sleep switches is kept OFF and to measure dynamic power the sleep switches are kept ON. Multiplexer is mostly used to select from a set of signals. A Multiplexer (MUX) selects the analog or digital signals and then passes it to the output section to get a single output. In a 2 n Multiplexer which inputs line has to be sent to output will be decided by the n selection lines. The amount of data that can be sent within definite amount of time and bandwidth in a network can be increased using a Multiplexer [7]. I0, I1, I2, 13 are the inputs of the 4*1 Multiplexer. A and B act as selector inputs. Two inverters are also placed along with the selector inputs. There are two and three input NAND gates. These NAND Gates are designed using the proposed approach by combining sleepy stack with RBB and DTCMOS. Dynamic power consumption is 3
obtained from simulation by keeping sleep switches ON and static power consumption by keeping sleep switches OFF. 4. Simulation Results Simulations has been done using Tanner S-Edit EDA tool and Static power consumption and Dynamic power consumption along with Propagation delay and power delay product for both JK master slave flip flop and multiplexer has been recorded. The tanner tool uses.8v V dd supply with dual threshold PMOS and NMOS and with reverse body biasing techniques. Both high threshold and low threshold transistors are used where high threshold transistors produces low leakage with greater delay and low threshold transistors with high speed and high leakage. Fig 4.Output waveform for JK Master -Slave flip flop The simulation results of 4*1multiplexer with different configurations of selection lines is shown in Table I to IV. The dynamic power consumption, static power consumption, delay and power delay product is calculated with every selection line as input..except propagation delay (PDP) of the circuit reduction in all the parameters i.e. dynamic power consumption, static power consumption is achieved. The simulation results of JK Master Slave flip flop with clock high is shown in Table V. The recordings show that outstanding power reduction is obtained when the circuit is in active state and ideal state. The use of RBB and high threshold transistors has contributed to increased delay but its effect is reimbursed by reduction in static power consumption achieved. The increment in delay is compensated by the power consumption achieved as there is trade -off between delay and static power consumption. 4
Fig 5.Outputwaveform for 4*1 multiplexer TABLE 1. Dynamic Power Saving for 4*1 Multiplexer with and RBB without RBB State Dynamic Power (nw)with Dynamic Power (nw)without Percentage Saving% 00 199.5 250.9 18.32 01 125.7 144.2 10.86 10 120.8 160 24.32 11 100.4 144.2 30.54 TABLE 2.Static Power saving for 4*1 Multiplexer with RBB and without RBB State Dynamic Power (nw)with Dynamic Power (nw)without Percentag e saving % 00 312 772.6 56.30 5
01 339.12 645.12 45.52 10 338 645.9 45.55 11 361 519.9 29.96 TABLE 3.Delay Savings for 4*1 Multiplexer with RBB and without RBB State Delay(pSec) with DTCMOS &RBB Delay(pSec) without Percentage Increment 00 300.2 197.8 51.25 01 145.8 109.8 33.44 10 80.5 51.8 54.76 11 153.8 115.8 31.35 TABLE 4.PDP Saving for 4*1 Multiplexer with RBB and without RBB STATE PDP(IE21) with DTCMOS &RBB PDP(IE21) without DTCMOS &RBB 00 93.65 151.87 35.56 01 49.06 70.87 26.78 Percentage Saving 10 26.34 58.26 17.43 11 52.324 60.34 6.74 TABLE 5. Dynamic power, Static power, Delay and PDP analysis of JK Master Slave Flip flop with DTCMOS and RBB 65nm Dynamic Power (nw) Static Power (nw) Delay (psec) PDP (IE21) 6
With DTCMOS& RBB Without DTCMOS& RBB Percentage Savings% 332.4.3065 251.9.7342 387.2 115.9 262.8 29.43 12.56 99.65-4.32 96.86 5. Conclusion A gate level power reduction technique for static and dynamic power consumption for digital CMOS circuits based on NAND gate like flip-flop and multiplexer is presented in this paper. When considering the gate current and sub threshold current there is a wide range of leakage for all input combinations of NAND. If the concentration is focused on increasing the speed of CMOS VLSI circuits then body biasing technique that use single power supply is enough. The delay penalty of body biasing is neglected as the focus is mainly on leakage power reduction. The employment of RBB and high threshold transistors has resulted in achieving static power reduction maximum up to 56.30% in 4*1 multiplexer and 99.65% in JK master-slave flip-flop but with 54.76% and 4.32% increment in delay in multiplexer and flip-flop respectively. The increment in delay is compensated by the power consumption achieved as there is trade-off between delay and static power consumption. References [1] Farzan Fallah and Massoud Pedram, Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits, IEICE transactions 01/2005; 88-C:509-519,JANUARY2005. [2] Pushpa Saini and Rajesh Mehra, Leakage Power Reduction in CMOS VLSI Circuits, INTERNATIONAL JOURNAL OF COMPUTER APPLICATIONS (0975 8887) VOLUME 55 NO.8, OCTOBER 2012. [3] Yuh-Fang Tsai, David E. Duarte, N. Vijaykrishnan, Mary Jane Irwin, Characterization and Modelling of Run Time Techniques For Leakage Power Reduction, IEEE transactions on very large scale integration (vlsi) systems, VOL. 12, NO. 11, NOVEMBER 2004 [4] Massoud Pedram, Qing Wu and Xunwei Wu A New Design for Double Edge Triggered Flip-flops IEEE conference on design automation 1998. Proceedings of the asp-dac '98. Asia and South pacific, 417 421, 0-7803-4425-1, 10-13 FEB 1998 [5] Satish Sharma, Shyam Babu Singh and Shyam Akashe, A Power Efficient GDI Technique for Reversible Logic, international journal of computer applications (0975 8887) Volume 73 No.14, July 2013. [6] Nisha Goyal, Neha Goyal,Sandeep Kaushal and Khushboo Sagar, Sub threshold Leakage Reduction Using Optimum Body Bias, international journal of engineering and science Isbn: 2319-6483, issn: 2278-4721, vol. 1, issue 8 (November 2012), pp 20-23. 7
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