Michelangelo Grosso Curriculum vitae

Michelangelo Grosso Curriculum vitae updated October 18, 2011 Education January 2005 April 2008: PhD in Computer and System Engineering at Politecnico di Torino, Italy. Dissertation title: Test and Diagnosis Techniques for Systems on Chip advised by Prof. M. Sonza Reorda. The thesis was selected as finalist for the 2008 IEEE-TTTC Doctoral Thesis Contest held at the IEEE VLSI Test Symposium, San Diego (CA), USA, 2008. September 1998 April 2004: Five-year Master Degree cum laude in Electronic Engineering at Politecnico di Torino, Italy. Dissertation title: Design and Evaluation of Test Strategies for Circuits Composed of Multiple Cores. Special Mention at the AICA-Federcomin Master Thesis Prize, Roma, Italy, 2004. July 1998: High School Diploma from I.T.C.S. Blaise Pascal, Giaveno (TO), Italy, final mark 60/60. Research Activities May 2008 now: Post-doctoral fellow at the Department of Control Theory and Computer Science Politecnico di Torino, Italy. He is with the Electronic CAD and Reliability Group (www.cad.polito.it) led by Prof. Matteo Sonza Reorda, working on electronic system reliability and test. The main research topics can be resumed as follows: Low-cost test, diagnosis and debug methodologies for Systems-on-Chip (SoCs) and Systems-in Package (SiPs), considering core and system architectural layers and test application Dependability techniques for integrated circuits and systems Methods for embedded system verification and validation. The following paragraphs provide additional details about the research activities, with references to published works. Test, diagnosis and debug techniques for Systems-on-Chip and Systems-in-Package. Design and development of methodologies and architectures aimed at improving test, diagnosis and debug of embedded systems. The following topics have been addressed: I-IP modules for test and diagnosis of embedded memories [C6][C25] and embedded processors [J4][C14][C29][W9][W13] Functional (software-based) test and diagnosis of microprocessors [B1][J5][C4][C5][C21][W1]; software-based delay testing [C18][C20][J6][C23][C24]. Fault injection. Evolutionary algorithms for test program generation. Software-based verification and self-test of microprocessor peripherals [J1][C11][C13] Definition of system-level test/diagnosis architectures for SoCs [J7][C30][C31][C32] Definition of algorithms for digital integrated circuit diagnosis [C27] 1

Design and development of software tools for the management of test and diagnosis flows in complex SoCs [C26][W8][W11][W12] Development of mechanisms for manufacturing yield monitoring and improvement, applied to new implementation technologies for semiconductor devices (Design for Manufacturing, DfM) [W4] [W6][W7][W10] Design of architectures for test and diagnosis of Systems-in-Package [J8]. Dependability techniques for digital integrated circuits and system verification. Reliability characterization - definition of a low-cost flow based on DfT and new tester architectures [C12][C16][C19][W3] Accelerated fault injection techniques [C9] Radiation testing for digital integrated circuits: definition of low-cost experimental flows based on available on-chip DfT structures for embedded memories, processors and logic [J3][C15][C17], and analysis of physical effects of radiation on silicon devices [C7][W2] Microprocessor and multicore on-line self-test, concurrent error detection and hardening techniques [J2][C1][C8] System functionality and dependability assessment trough FPGA prototyping [C2][C3][C10]. Test and Dependability of innovative implementation technologies for integrated circuits. Design and evaluation of methodologies for testing digital circuits implemented on the structured ASIC platform [C28] Design and evaluation of methodologies for assessing and improving the dependability of digital circuits implemented on the NanoFabric platform [C22][W5]. Scientific Collaborations Michelangelo Grosso has been working in tight collaboration with renowned international research centers and some of the most important Italian companies designing and developing electronic systems, obtaining significant results and several joint publications. He collaborated in the preparation of several regional and European project funding requests and was the coordinator of the proposal for a FIRB Futuro in Ricerca Italian research project. Collaborations with other Universities Since 2009: Participation and coordination of research in collaboration with Universidad Carlos III de Madrid Electronic Technology Department (Madrid, Spain Prof. L. Entrena) on the topics of multiprocessor error-detection and hardening. Since 2008: Participation and coordination of research in collaboration with the University of Padova Dipartimento di Ingegneria Elettronica e Informatica (Padova, Italy Prof. A. Paccagnella), concerning the radiation testing of integrated circuits. Definition of low-cost, DfT-based radiation testing flows for embedded microprocessor, memories and logic. May-December 2007: Participation and coordination of research in collaboration with the University of Cyprus - Department of Electrical and Computer Engineering (Nicosia, Cyprus Prof. M.K. Michael) on the topics of path-delay fault testing in microprocessor cores. 2

Collaborations with Industry Since September 2011: Collaboration with NplusT (San Martino in Colle, PG, Italy) on the topics of test automation. Since May 2008: Participation and coordination of research, in collaboration with Pirelli Tyre (Milano, Italy Dr. G. Audisio) and Accent (Vimercate, MI, Italy Dr. V. Avantaggiati and Dr. G. Pasqualini) on the reliability, concerning test and calibration aspects of the Pirelli CyberTyre Project. The Project is aimed at the development of a radio-accessed in-tyre accelerometric sensor system providing useful information for enhancing car braking and stability control. The collaboration deals with development of test and calibration flows, digital system prototyping on FPGA, reliability analysis and evaluation. Since 2007: Collaboration with ELES Test Equipments (Todi, PG, Italy Dr. M. Giancarlini) within the activity Development of Low-Cost Solutions for Reliability Test and End-of-Production Test of Circuits equipped with Design for Testability (DfT) Structures. 2004-2005: Collaboration with Centro Ricerche Fiat (Torino, Italy Dr. A. Manzone) on the development and evaluation of methodologies for production and on-line test of integrated systems. Since 2004: Collaboration with STMicroelectronics (Agrate Brianza, MI, Italy Dr. D. Appello) on the topics of DfX: design, development and evaluation of test and diagnosis IPs for embedded memory cores, design of test interfaces (extensive use of Standards such as IEEE 1149.1, IEEE 1500, IEEE 1450), generation of test routines, study and development of Design for Manufacturing techniques. Test chip released in December 2006 in a 90 nm technology. Teaching activities Assistant professor, Computer Architecture undergraduate course in Computer Engineering, Politecnico di Torino (2006/2007, 2007/2008, 2008/2009, 2009/2010 and 2010/2011) Course tutor, Computer Science, distance learning degrees in Engineering, Politecnico di Torino (2010/2011) Assistant professor, Computer Architecture graduate course in Telecommunications Engineering, Politecnico di Torino (2006/2007 and 2007/2008) Laboratory assistant, Computer Science, undergraduate course in Production Engineering and Environmental Engineering, Politecnico di Torino (2006/2007, 2007/2008, 2008/2009 and 2009/2010) Course tutor, Computer Architecture undergraduate course, distance learning degree in Computer Engineering, Politecnico di Torino, Alessandria (TO) campus (2005/2006 and 2006/2007) Laboratory assistant, Computing Tools for Aerospace Engineering, graduate course in Aerospace Engineering, Politecnico di Torino (2004/2005 and 2005/2006). Michelangelo Grosso has been thesis advisor for about 10 Master students in Computer and Electronic Engineering (2008-2011). Co-author of the Embedded Tutorial Software Based Self-Test of Embedded Microprocessors (P. Bernardi, M. Grosso, E. Sanchez) presented at the Latin-American Test Workshop, 2011 (Porto de Galinhas, Brazil). 3

Technical skills Programming languages: C/C++, Java, bash scripting, html Hardware description languages: VHDL, Verilog Operative systems: Unix, Linux, MS-Windows, MS-DOS Ancillary software: MS-Office suite (Word, Excel, Powerpoint, Access, Visio, Publisher), graphics (Corel, Adobe) EDA tools: Synopsys Design Compiler & Tetramax ATPG, Mentor/Modelsim, Cadence Incisive Simulator suite, Xilinx ISE, Spice. Languages Italian: native language English: fluent French: good knowledge. Other Activities Michelangelo Grosso is a member of Institute of Electrical and Electronic Engineers (IEEE) since 2005. He is a Program Committee member of the European Workshop on Bio-Inspired Heuristics for Design Automation (EvoHOT) and a reviewer for IEEE Transactions on Very Large Scale Integration Systems, IET Computer and Digital Techniques and Springer Journal of Electronic Testing. He has been Publication Chair for the IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-Test) in 2010 and 2011. He was a member of the Local Organizing Committee at the IEEE European Test Symposium in 2008. His interests include music (pop, rock, jazz), books (fiction and classics), contemporary art, movies, photography and cooking. He plays classic and electric guitar, and has played with several local amateur bands. He likes cycling and canoeing. He loves traveling and visited most countries in Europe, U.S., Canada and Japan. 4

Publication List Book Chapters: [B1] P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda, Software-Based Self-Test for Embedded Microprocessors, in R. Ubar, T. Vierhaus, J. Raik, Design and Test Technology for Dependable Systems-on-Chip, IGI Global, ISBN 978-1-60960-212-3, DOI 10.4018/978-1-60960-212-3 Refereed Journal Articles: [J1] M. Grosso, W.J. Perez H., D. Ravotto, E. Sanchez, M. Sonza Reorda, A. Tonda, J. Velasco Medina, Functional Verification of DMA Controllers, Springer Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 27, N. 4, August 2011, pp. 505-516 [J2] P. Bernardi, L. Bolzani Poehls, M. Grosso, M. Sonza Reorda, A Hybrid Approach for Detection and Correction of Transient Faults in SoCs, IEEE Transactions on Secure and Dependable Computing, Vol. 7, N. 4, Oct.-Dec. 2010, pp. 439-445 [J3] P. Rech, A. Paccagnella, M. Grosso, M. Sonza Reorda, D. Melchiori, D. Appello, Evaluating the Impact of DFM Library Optimizations on Alpha-induced SEU Sensitivity in a Microprocessor Core, IEEE Transactions on Nuclear Science, Vol. 57, N. 4, Aug. 2010, pp. 2098-2105 [J4] P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, Exploiting an Infrastructure-IP for SoC test, diagnosis and silicon debug, IET Computers and Digital Techniques, Vol. 4, N. 2, March 2010, pp. 104-113 [J5] D. Appello, P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda, An Effective Diagnostic Pattern generation strategy for Transition Delay Faults in full-scan SoCs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, N. 11, November 2009, pp. 1654-1659 [J6] P. Bernardi, K. Christou, M. Grosso, M. Michael, E. Sanchez, M. Sonza Reorda, Exploiting MOEA to Automatically Generate Test Programs for Path-delay Faults in Microprocessors, in Springer Lecture Notes in Computer Science, after 4 th European Workshop on Bio-Inspired Heuristics for Design Automation (EvoHOT 2008), Vol. 4974/2008, pp. 224-234 [J7] P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, A System-layer Infrastructure for SoC Diagnosis, Springer Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 23, N. 5, October 2007, pp. 389-404 [J8] D. Appello, P. Bernardi, M. Grosso, M. Sonza Reorda, System-in-Package Testing: Problems and Solutions, IEEE Design & Test of Computers, Vol. 23, N. 3, May-June 2006, pp. 203-211 Conference Proceedings [C1] L. Parra, A. Lindoso, M. Portela, L. Entrena, M. Grosso, M. Sonza Reorda, Control flow checking through embedded debug interface, 26th Conference on Design of Circuits and Integrated Systems (DCIS2011), November 16-18, 2011, Albufeira, Portugal, accepted for publication [C2] J. Lagos-Benites, M. Grosso, M. Sonza Reorda, G. Audisio, M. Pipponzi, M. Sabatini, V.A. Avantaggiati, An FPGA-emulation-based platform for characterization of digital baseband communication systems, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, October 3-5, 2011, Vancouver (BC), Canada, pp. 391-398 [C3] J. Lagos-Benites, M. Grosso, L. Sterpone, M. Sonza Reorda, G. Audisio, M. Pipponzi, M. Sabatini, A Low-cost Emulation System for Fast Co-verification and Debug, IEEE European Test Symposium (ETS), May 23-27, 2011, Trondheim, Norway, p. 212 [C4] P. Bernardi, M. Grosso, E. Sanchez, O. Ballan, G. Fontana, Fault Grading of Software-Based Self- Test procedures for Dependable Automotive Applications, ACM/IEEE Design, Automation and Test in Europe Conference (DATE), March 14-18, 2011, Grenoble, France, pp. 1-2 [C5] O. Ballan, P. Bernardi, G. Fontana, M. Grosso, E. Sanchez, A Fault Grading Methodology for Software-Based Self-Test Programs in Systems-on-Chip, IEEE International Workshop on Microprocessor Test and Verification (MTV), Dec. 13-15, 2010, Austin, TX, USA, pp. 43-46 5

[C6] P. Bernardi, M. Grosso, M. Sonza Reorda, Y. Zhang, A Programmable BIST for DRAM Tests and Diagnosis, IEEE International Test Conference (ITC), Oct. 31 Nov. 5, 2010, Austin, TX, USA, p. 15.3 [C7] P. Rech, M. Grosso, F. Melchiori, D. Loparco, D. Appello, L. Dilillo, A. Paccagnella, M. Sonza Reorda, Analysis of Root Causes of Alpha Sensitivity Variations on Microprocessors Manufactured using Different Cell Layouts, IEEE International On-Line Testing Symposium (IOLTS), July 5-7, 2010, Corfu Island, Greece, pp. 29-34, DOI 10.1109/IOLTS.2010.5560236 [C8] M. Grosso, M. Sonza Reorda, M. Portela-Garcia, M. Garcia Valderas, C. Lopez-Ongil, L. Entrena, An on-line fault detection technique based on embedded debug features, IEEE International On- Line Testing Symposium (IOLTS), July 5-7, 2010, Corfu Island, Greece, pp. 167-172 [C9] M. Grosso, H. Guzman-Miranda, Advanced Speeding-up Techniques for SEU Sensitivity Assessment, IEEE International Symposium on Industrial Electronics (ISIE 2010), July 4-7, 2010, Bari, Italy, pp. 1995-2000 [C10] M. Di Marzio, M. Grosso, M. Sonza Reorda, L. Sterpone, G. Audisio, M. Sabatini, A Novel Scalable and Reconfigurable Emulation Platform for Embedded Systems Verification, IEEE International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, pp. 865-870 [C11] M. Grosso, W.J. Perez H., D. Ravotto, E. Sanchez, M. Sonza Reorda, J. Velasco Medina, A Software-based self-test methodology for system peripherals, IEEE European Test Symposium (ETS 10), May 24-28, 2010, Prague, Czech Republic, pp. 195-200 [C12] P. Bernardi, M. Grosso, M. Sonza Reorda, An adaptive tester architecture for volume diagnosis, IEEE European Test Symposium (ETS 10), May 24-28, 2010, Prague, Czech Republic, pp. 227-232 [C13] M. Grosso, W.J. Perez H., D. Ravotto, E. Sanchez, M. Sonza Reorda, J. Velasco Medina, Functional Test generation for DMA controllers, IEEE Latin-American Test Workshop (LATW 2010), March 28-31, 2010, Punta del Este, Uruguay, pp. 1-6 [C14] M. Grosso, M. Sonza Reorda, Exploiting Embedded FPGA in On-line Software-based Test Strategies for Microprocessor Cores, 15 th IEEE International On-Line Testing Symposium (IOLTS), June 24-26, 2009, Sesimbra-Lisbon, Portugal, pp. 95-100 [C15] P. Rech, S. Gerardin, A. Paccagnella, P. Bernardi, M. Grosso, M. Sonza Reorda, D. Appello, Evaluating Alpha-induced Soft Errors in Embedded Microprocessors, 15th IEEE International On- Line Testing Symposium (IOLTS), June 24-26, 2009, Sesimbra-Lisbon, Portugal, pp. 69-74 [C16] D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sanchez, M. Sonza Reorda, Automatic Functional Stress Pattern Generation for SoC Reliability Characterization, 14th IEEE European Test Symposium (ETS 09), May 25-29, 2009, Sevilla, Spain, pp. 93-98 [C17] D. Appello, P. Bernardi, S. Gerardin, M. Grosso, A. Paccagnella, P. Rech, M. Sonza Reorda, DfT Reuse for Low-Cost Radiation Testing of SoCs: A Case Study, 27th IEEE VLSI Test Symposium (VTS 09), May 3-7, 2009, Santa Cruz, CA, USA, pp. 276-281 [C18] P. Bernardi, M. Grosso, E. Sanchez, M. Sonza Reorda, A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores, 9th IEEE International Workshop on Microprocessor Test and Verification (MTV 08), December 8-10, 2008, Austin, TX, USA, pp. 103-108 [C19] D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso, An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs, 13 th IEEE European Test Symposium (ETS 08), May 25-29, 2008, Lago Maggiore, Italy, pp. 140-145 [C20] P. Bernardi, K. Christou, M. Grosso, M. Michael, E. Sanchez, M. Sonza Reorda, A novel SBST generation technique for path-delay faults in microprocessors based on BDD analysis and evolutionary algorithm, 26 th IEEE VLSI Test Symposium (VTS 08), Apr. 27 May 1, 2008, San Diego, CA, USA, pp. 389-394 [C21] D. Appello, P. Bernardi, M. Grosso, J. Lagos-Benites, D. Ravotto, E. Sanchez, M. Sonza Reorda, An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), Sept. 26-28, 2007, Roma, Italy, pp. 291-299 6

[C22] M. Grosso, M. Rebaudengo, M. Sonza Reorda, Safety Evaluation of NanoFabrics, 22th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), Sept. 26-28, 2007, Roma, Italy, pp. 418-426 [C23] P. Bernardi, M. Grosso, E. Sánchez, M. Sonza Reorda, On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores, 12th IEEE European Test Symposium (ETS 07), May 20-24, 2007, Freiburg, Germany, pp. 179-184 [C24] P. Bernardi, M. Grosso, M. Sonza Reorda, Hardware-Accelerated Path-Delay Fault Grading of Functional Test Programs for Processor-based Systems, 17th ACM Great Lakes Symposium on VLSI (GLSVLSI), March 11-13, 2007, Stresa-Lago Maggiore, Italy, pp. 411-416 [C25] D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, Embedded Memories Diagnosis: An Industrial Workflow, IEEE International Test Conference (ITC 2006), Oct. 24-26, 2006, Santa Clara, CA, USA, pp. 1-9 [C26] D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, V. Tancorre, On the Automation of the Test Flow of Complex SoCs, 24th IEEE VLSI Test Symposium (VTS 06), Apr. 30 May 4, 2006, Berkeley, CA, USA, pp. 386-391 [C27] P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, A pattern ordering algorithm for reducing the size of fault dictionaries, 24th IEEE VLSI Test Symposium (VTS 06), Apr. 30 May 4, 2006, Berkeley, CA, USA, pp. 166-171 [C28] P. Bernardi, M. Grosso, Test Considerations about the Structured ASIC Paradigm, IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS2006), April 18-21, 2006, Prague, Czech Republic, pp. 230-231 [C29] P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, Exploiting an I-IP for both test and silicon debug of microprocessor cores, 6th IEEE International Workshop on Microprocessor Test and Verification (MTV 05), Nov. 3-4, 2005, Austin, TX, USA, pp. 55-62 [C30] P. Bernardi, M. Grosso, A. Manzone, M. Rebaudengo, E. Sanchez, M. Sonza Reorda, Integrating BIST techniques for on-line SoC testing, 11th IEEE International On-Line Testing Symposium (IOLTS), July 6-8, 2005, Saint Raphael, France, pp. 235-240 [C31] P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, Exploiting an Infrastructure IP to reduce the costs of memory diagnosis in SoCs, 10th IEEE European Test Symposium (ETS 05), May 22-25, 2005, Tallinn, Estonia, pp. 202-207 [C32] P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, On the diagnosis of SoCs including multiple memory cores, 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS2005), April 13-16, 2005, Sopron, Hungary, pp. 75-80 Workshop participations [W1] P. Bernardi, M. De Carvalho, M. Grosso, J. Lagos, E. Sanchez, O. Ballan, On-line Software-Based Self-Test in Automotive Electronics: Problems and Solutions, IEEE Dependability Issues in Deepsubmicron Technologies (DDT), May 26-27, 2001, Trondheim, Sweden (in conjunction with IEEE European Test Workshop 2011) [W2] D. Appello, P. Bernardi, M. Grosso, F. Melchiori, A. Paccagnella, P. Rech, M. Sonza Reorda, Alphainduced SEU Sensitivity Dependencies on Logic Cell Layout Configurations: Preliminary Results Analysis, 2 nd IEEE Workshop on Design for Reliability and Variability (DRV 2009), November 5-6, 2009, Austin, TX, USA (in conjunction with ITC Test Week 2009) [W3] D. Appello, P. Bernardi, M. Bruno, R. Cagliesi, M. Giancarlini, M. Grosso, E. Sanchez, M. Sonza Reorda, An Automatic Functional Stress Pattern Generation Technique Suitable for SoC Reliability Characterization, 2 nd IEEE International Workshop on Automated Test Equipment: Vision ATE 2020, Oct. 30-31, 2008, Santa Clara, CA, USA [W4] D. Appello, P. Bernardi, M. Grosso, M. Rotigni, M. Sonza Reorda, V. Tancorre, A Case Study on SoC Low-Cost Silicon Debug and Diagnosis, 5th IEEE International Workshop on Silicon Debug and Diagnosis, April 30 May 1, 2008, San Diego, CA, USA 7

[W5] M. Grosso, M. Rebaudengo, M. Sonza Reorda, On the Evaluation of Reliability of NanoFabric-based Architectures through Fault Simulation, Workshop on Dependable and Secure Nanocomputing (WDSN07), June 28, 2007, Edinburgh, UK [W6] D. Appello, P. Bernardi, M. Grosso, J. Lagos-Benites, E. Sanchez, M. Sonza Reorda, IEEE 1500 Compliant Self-Test Design Library, IEEE International Workshop on Open Source Test Technology Tools (IOST3), May 9-10, 2007, Berkeley, CA, USA [W7] D. Appello, P. Bernardi, M. Grosso, M. Sonza Reorda, R. Sirtori, V. Tancorre, Advances on Proactive DfM Experiences, IEEE Workshop on Design for Manufacturing and Yield (DFM&Y), Oct. 26-27, 2006, Santa Clara, CA, USA [W8] D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, V. Tancorre, M. Sonza Reorda, STATbist v.0.3, IEEE International Workshop on Open Source Test Technology Tools (IOST3), April 30, 2006, Berkeley, CA, USA [W9] D. Appello, M. Grosso, M. Rebaudengo, M. Sonza Reorda, An I-IP for the Debug of Microprocessor Cores, XX Conference on Design of Circuits and Integrated Systems (DCIS 05), November 23-25, 2005, Lisboa, Portugal [W10] D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, V. Tancorre, M. Sonza Reorda, A new DFMproactive technique, 2nd IEEE International Workshop on Silicon Debug and Diagnosis (SDD 2005), Nov. 10-11, 2005, Austin, TX, USA [W11] P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, D. Appello, R. Mattiuzzo, V. Tancorre, A Tool for Supporting and Automating the Test of Complex System-on-Chips, 12th IEEE International Test Synthesis Workshop (ITSW), April 11-12, 2005, Santa Barbara, California, USA [W12] P. Bernardi, A. Bertuzzi, M. Grosso, V. Tancorre, S. Tritto, Testing parametric cores: a multilayer test program to improve and automate the EDA-ATE link, 7th European Manufacturing Test Conference (EMTC), April 11, 2005, Munich, Germany (in conjunction with SEMICON Europa 2005) [W13] D. Appello, P. Bernardi, M. Grosso, M. Rebaudengo, M. Sonza Reorda, Supporting debug and test of a SoC through an I-IP, 2nd IEEE International Workshop on Infrastructure IP (I-IP 2004), October 28-29, 2004, Charlotte, North Carolina, USA 8