1. Description of the research proposal

Transcription

1 1. Description of the research proposal a) Duration of the project and expected total cost Duration: 4 years ( ) Total cost: EEK b) General background About the importance of the research problem. Rapid advances in the areas of deep-submicron electron technology and design automation tools enabled engineers to design larger and more complex integrated circuits. Until recently, most electronic systems consisted of one or multiple printed circuit boards (PCB), containing multiple integrated circuits (IC) each. Today s design methods and microelectronics technology provides designers the possibility to integrate a large number of different functional blocks, usually referred as cores, in a single IC. Such a design style allows designers to reuse previous designs and will lead therefore to shorter time-to-market and reduced cost. Within the next four years, SOC designers will cut new product development cycle time from an average of 12 months today, to just four months. SoC is seen as a major new technology and the future direction for the semiconductor industry. On the other hand, testing of such systems is a problematic and time consuming task, mainly due to the resulting IC s complexity and the high integration density [1]. To test the individual cores of the system the test pattern source and sink have to be available together with an appropriate test access mechanism (TAM) [2]. We can implement such a test architecture in several different ways. A widespread approach implements both source and sink off-chip and requires therefore the use of external Automatic Test Equipment (ATE). But, as the internal speed of SoC is constantly increasing, the demands to the ATE memory size are increasing and the technology used in ATE is always one step behind, the ATE solution will soon become unacceptably expensive and inaccurate [3] leading also to an unacceptable yield loss. Therefore, in order to apply at-speed tests and to keep the test costs under control, on-chip test solutions are needed. Such a solution is usually referred to as built-in self-test (BIST). Moving towards multi-million gate SOCs makes embedded testing strategies via BIST mandatory. BIST will be in the future basically the only practical solution to perform at-speed test and can be used not only for manufacturing test but also for periodical field maintenance testing [4,5].This is a new hot design concept today targeting the fault-tolerance of digital systems [6]. Critical overview of previous results. The traditional BIST architecture consists of a test pattern generator (TPG), a test response analyzer (TRA) and a BIST control unit (BCU), all implemented on the chip. This approach allows to apply at-speed tests and eliminates the need for an external tester. Different BIST approaches have been available for a while and have got wide acceptance. However, the traditional architectures suffer under several disadvantages. BIST for digital logic (logic BIST) uses mostly pseudorandom tests. The fault coverage reachable by pseudorandom testing depends highly on the functionality of the circuit under test (CUT) and the logic depth. A lot of the faults in CUT may be random pattern resistant, meaning that not all signal transitions can be controlled and observed by the generated patterns. One way to solve the pattern resistance problem is to improve the testability of CUT [7]. Another disadvantage of the pseudorandom testing are the long test sequences and long testing time. One solution to the problem is to complement pseudorandom test patterns with deterministic test patterns, applied from the on-chip memory or, in special situations, from the ATE. This approach is usually referred to as hybrid BIST [8]. Traditional BIST solutions use special hardware for pattern generation (TPG) on chip, but this may introduce significant area overhead and performance degradation. To overcome these problems, recently new methods have been proposed which exploit specific functional units such as arithmetic units or processor cores for onchip test pattern generation and test response evaluation [9-10]. This approach is called functional BIST. In particular, it has been shown that adders can be used as TPGs for pseudorandom, pseudoexhaustive and 1

2 deterministic patterns. But up to now there is no general method how to use arbitrary functional units for built-in TPG. Novelty of the proposed research. In this project we propose to develop new BIST methodologies by combining the three mentioned above emerging conceptions: hybrid BIST, functional BIST and BIST driven design for testability. In hybrid BIST we have already achieved several original results in a close cooperation with Linköping University (prof. Zebo Peng) [8,11-15]. In this work we have been concentrating on test cost calculation and hybrid BIST optimization for single-core designs. Recently we developed a new methodology for test time minimization, under memory constraints, for multi-core systems. The paper was accepted at a very high-level Asian Test Symposium [13] and will be presented in the end of the year (the acceptance rate at this conference was 1 paper from 4 submissions). The methodology is based on a novel idea of cost estimation which allowed to develope a fast iterative algorithm to minimize the total length of the hybrid BIST under given memory constraints. In fact, by these starting results we have opened a new research area of hybrid BIST synthesis with a lot of challenges and oportunities. The research area is multidimensional with coordinates like a range of different BIST architectures, a set of different design criteria to be taken into account like test quality, test length, testing time, memory cost, power constraints, area overhead etc. To describe the potential research field in general terms, we try to develop methods for optimizing hybrid BIST for different BIST architectures at different criteria and different restrictions. The research in this multidimensional space is fully new. A general theory has not yet developed. The whole problem is very complex. It should be attacked step by step. A lot of steps are already planned by us, and that plan, in fact, represents a large portfolio of problems to be investigated. Through our recent publications in this field we feel ourselves to be on the research forefront. And in many cases we see already clearly the ways to solutions of the formulated problems. The novelty of our proposal related to functional BIST is the combination of two different paradigms design for testability (DFT) and functional BIST for developing a new powerful DFT/BIST approach. The main goal of this approach is to improve the traditional functional BIST methods with considerable low fault detectability by increasing the fault coverage at minimal added area overhead needed for the improvement of observability of the system. Combining functional BIST with pseudorandom testing and deterministic testing is very promising conception, never investigated up to now. The prospective results separately in hybrid BIST and functional BIST described above will give a solid basis to achieve totally new results in combining these both paradigms. The results of the project will be introduced into the educational process in TTU with the goal to develop new laboratory tools, works and internet-based teaching materials. We have been already very active in developing new teaching paradigms, methods and tools for teaching design and test, and the big interest in our international conference papers on that topic has proven the novelty and importance of this activity. This strategy of combining research with teaching, and implementing the research results into the teaching environment will be also the backbone of this project. Preliminary results achieved already. Our research group already has a lot of preliminary results in this field. The research in the field of hybrid BIST has been carried out as already mentioned in a close cooperation with Linköping University [8,11-15]. We have developed a very good laboratory research environment with a large set of diagnostic software tools. This environment has attracted many partners abroad in Sweden, Poland, Germany, France and other countries to carry out joint research project. Thanks to this environment, the copperation with Linköping has been very succesful. In this research will be involved our students who have already proven their excellence by valuable international publications: PhD students H.Kruus [8,12] and E.Orasson [13], the master student M.Jenihhin [14,15] a.o. The research in hybrid BIST will be one of the main the topics of their work on the thesis. A lot of research has been done already also in the field of functional BIST. We have developed an environment for investigating the quality of functional BIST and the dependency of the quality on input stimulation and monitoring strategies [16-18]. About 5-6 diploma works have been already carried out on this environment targeted to optimizing the functional BIST. 2

3 In design for testability, we have developed new testability calculation methods based on high-level decision diagrams [19-20]. These methods can be directly used in developing new DFT/BIST approaches. Also, based on these methods new tools for estimating controllability and observability of systems have been and will be developed to support the experimental research in this project. The research will be carried out in cooperation with ARTEC Design Group. Currently a joint project MIKROTEST is going on targeted in developing new BIST conceptions and evaluation methods. New cooperation projects are being planned in the frame of the STATE program of Development Centers (the project group belongs to the Development Center ELIKO). All the mentioned results achieved by now, and the high interest which has been expressed from the side of microelectronics industry create together an excellent motivation to continue this research towards developing new more efficient and exact methods for developing self-testing digital systems. References: [1] M.L.Bushnell, V.D.Agrawal. Essentials of Electronic testing. Kluwer Acad. Publishers, 2000, 690 p. [2] Y.Zorian, E.J.Marinissen, S.Dey, Testing Embedded Core-Based System Chips, IEEE International Test Conference (ITC), pp , Washington, DC, October IEEE Computer Society Press. [3] Technology Roadmap for Semiconductors. Semiconductor Industry Assoc., San Jose, California, [4] S.Mourad, Y.Zorian. Principles of Testing Electronic Systems. Wiley & Sons, Inc. New York, 2000, 420 p. [5] R.Rajsuman. System-on-a-Chip. Design and Test. Artech House, Boston, London, 2000, 277 p. [6] R.Ubar, J.Raik. Testing Strategies for Networks on Chip. In Network on Chip, edited by A.Jantsch and H.Tenhunen, Kluwer Academic Publishers, Boston/Dordrecht/London, 2003, pp [7] A.L.Crouch. Design for Test. Prentice Hall, 1999, 349 p. [8] G.Jervan, H.Kruus, Z.Peng, R.Ubar. About Cost Optimization of Hybrid BIST in Digital Systems. 3 rd Int. Symp. on Quality of Electronic Design, San Jose, California, March 18-20, 2002, pp [9] S.Hellebrand, H.-J.Wunderlich and A.Hertwig: Mixed-Mode BIST using Embedded Processors. Journal of Electronic Testing: Theory and Applications 12, (1998). [10] J.Rajski, J.Tyszer: Arithmetic Built-In Self-Test For Embedded Systems, Prentice-Hall, New Jersey (1998) [11] G.Jervan, Z.Peng, R.Ubar, Test Cost Minimization for Hybrid BIST, IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT 00), pp , Yamanashi, Japan, October [12] H.Kruus, R.Ubar, G.Jervan, Z.Peng. Using Tabu Search Method for Optimizing the Cost of Hybrid BIST. XVI Conference on Design of Circuits and Integrated Systems, Porto, Portugal, Nov , 2001, pp [13] R. Ubar, G. Jervan, Z. Peng, E. Orasson, R. Raidma, Fast Test Cost Calculation for Hybrid BIST in Digital Systems, Euromicro Symposium on Digital Systems Design, pp , Warsaw, Poland, September, [14] G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Test Time Minimization for Hybrid BIST of Core-Based Systems. Asian Test Symposium 2003, Xian, China, November 17-19, 2003 (accepted). [15] G.Jervan, P.Eles, Z.Peng, R.Ubar, M.Jenihhin. Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. 18 th Int. Symposium on Defect and Fault Tolerance in VLSI Systems. Cambridge, MA, USA, November 3-5, 2003 (accepted). [16] R.Ubar. E-Learning Tools for the Field of Electronics Design and Test. 4 th Int. Conf. On Information Technology Based Higher Education and Training. July 7-9, 2003, Marrakech, Morocco, pp [17] S.Devadze, A.Jutman, A.Sudnitson, R.Ubar, H.-D.Wuttke. Teaching Digital RT-Level Self-Test Using a Java Applet. 20 th IEEE Conference NORCHIP 2002, Copenhagen, Denmark, November 11-12, 2002, pp [18] A.Schneider, K.-H.Diener, G.Elst, R.Ubar, E.Ivask, J.Raik. Integration of Digital Test Tools to the Internet- Based Environment MOSCITO. Proc. of the World Conference on Systemics, Cybernetics and Informatics, SCI Orlando, Florida, USA, July 28-30, [19] R.Ubar, J.Raik, T.Nõmmeots. Testability Guided Hierarchical Test Generation with Decision Diagrams. 20 th IEEE Conference NORCHIP 2002, Copenhagen, Denmark, November 11-12, 2002, pp [20] J.Raik, T.Nõmmeots, R.Ubar. New Method of Testability Calculation to Guide RTL Test Generation. Proc. of 4 th IEEE Latin-American Test Workshop LATW2003, Natal, Brazil, February 16-19, 2003, pp c) Main goals, objectives and hypotheses of the project 3

4 The main goal of the current project is to develop new methods, algorithms and software tools for design of selftesting digital systems. The main problems and objectives to be investigated are: develoment, evaluation and optimization of hybrid BIST architectures of digital systems; develoment, evaluation and optimization of functional BIST of digital systems; methods for BIST driven design for testability of digital systems; development of new methods for design of self-testing digital systems by combining hybrid and functional BIST approaches with design for testability. Hybrid BIST consists of pseudorandom and deterministic testing. Todays complex digital systems consist usually of multiple cores, where different approaches are possible: each core can have its own test resources, or the resources can be shared. Testing of cores can be carried out in parallel, in sequence, or in a combined parallel-sequential way. Pseudorandom and deterministic testing can be managed in a uniform way (either with shared resources, in parallel, or in sequence) or in a different way. The strategy choosed will affect differently to test length and time, power consumption or memory cost. A lot of different optimization tasks can be formulated, but all of them are very complex and don t have easy straightforward solutions. There are some solutions found in the literature for combinational cores. For sequential cores no research has been made till now. The development of the methodology for sequential cores will be the objective of this project. For estimating the solutions powerful test generation and fault simulation methods and tools should be available. Existing commercial tools because of their rather low controllability and clumsiness are not well suited for using in the iterative optimization procedures. The test generation and fault simulation tool environment developed in our laboratory is better suited for the iterative use in the optimization procedures. This fact has been proved already in the cooperative research with Linköping University and Fraunhofer Institute in Germany. The high speed (comparable to the best commercial tools), efficiency and easy usability of our tools in complex iterative experiments has made our laboratory attractive for foreign partners and offers very good opportunities for carrying out this project. Adding some new features to the diagnostic tool set to be dictated by the forthcoming experimental research will provide additional side-effect of the project. Functional BIST is rather little investigated field in self-testing conception. In this approach, instead of introducing new dedicated hardware to the system, the functionalities of the system himself will be used for testing purposes. The traditional design tools should be supported by dedicated analysis tools targeted to improving the controllability/observability properties of the system with functional BIST. A methodology will be developed for functional BIST driven design for testability, and corresponding algorithms and tools will be created to support traditional CAD tools. From the set of the problems described the following tasks of the new project result: to investigate the most common BIST architectures of digital systems with the goal to create proper models for representing hardware and memory cost, testing time, fault coverage, and power consumption; to develop suitable architectures for implementing hybrid BIST conception; to develop cost models for different hybrid BIST architectures; to develop fast and simple cost estimation algorithms and tools for preliminary evaluation of proposed solutions for hybrid BIST; to develop methods for minimizing hybrid BIST cost at given different constraints; to develop new test generation, fault simulation, test ordering and cost calculation tools and experimental research environments suitable for carrying out the optimization procedures for hybrid BIST; to investigate the possibilities of using system own functionalities to build up functional BIST schemes; to develop methods of calculation the cost and quality of chosen functional BIST schemes; to develop methods, algorithms and tools to support functional BIST driven design for testability; to investigate possibilities of combining hybrid and functional BIST methods with design for testability; to develop methods, algorithms and tools for designing and evaluating combined hybrid/functional BIST solutions. 4

5 As an outcome of the work described, we will have a set of new conceptions, methods, algorithms, and tools for supporting design of self-testing digital systems. d) Research methods and equipment ressources Research methods are based on using digital electronics, automata theory, Boolean differential algebra, graph theory, theory of algorithms, combinatorial optimization theory, data structures and computation theory and other related fields of electrical engineering, computer science, software engineering and technical diagnostics. Experimental investigations of new algorithms and procedures will be carried out on PC- and SUN-platforms using the professional electronics design software SYNOPSIS, CADENCE a.o. which is available at the Computer Engineering Department. For experimental investigations, internationally reccommended and accepted benchmark examples will be used like ISCAS 85, ISCAS 89 and others as cores to build up more complex digital systems. Since 1995 the department has participated in 11 European projects: TEMPUS JEP-4722, EEMCN, FUTEG, ATSEC, SYTIC, VILAB, THEIERE, EUROCHIP, EUROPRACTICE, REASON and evikings. As the result of these projects and of active cooperation at the European level, support from the Swedish companies Ericsson Telecom AB Ltd. and DIGSIM DATA AB, a professional laboratory environment based on 3 servers, more than 30 SUN workstations and about 50 PCs has been established. It includes 15 licences for professional CAD software Cadence, 10 licences for professional CAD software Synopsys, CAD tools of Xilinx, Altera, Viewlogic, DIXI-CAD a.o. which made it possible to carry out high level experimental work with research targets. The research environment is strenghtened by the test and diagnostics oriented software Turbo-Tester and DECIDER developed at the department as the result of the mentioned European projects and ETF grants G574 ( ), G1850 ( ) G1880 ( ), G3658 ( ) and G4300 ( ). All the needed interfaces have been built between the commercial and home-made software packages allowing to carry out diverse research scenarios based on the described environment. e) Institutions and researchers involved in the project In this project, the following teachers, researchers and students of the Computer Engineering Department will participate in the research: 1. Raimund Ubar Dr. of techn. sc. Prof., Head of the chair 2. Jaan Raik Dr. of techn. sc. Senior Reseacher 3. Teet Evartson Cand. of techn. sc. Ass. prof. 4. Marina Brik Dr. of techn. sc Researcher 5. Artur Jutman Magister of techn. sc. PhD student ( ) 6. Elmet Orasson Magister of techn. sc PhD student ( ) 7. Helena Kruus Magister of techn. sc PhD student ( ) 8. Margit Aarna Magister of techn. sc PhD student ( ) 9. Maksim Jenihhin Bachelor Magister student ( ) 10. Tatjana Vassiljeva Bachelor Magister student ( ) 11. Julia Smahtina Bachelor Magister student ( ) The project proposer (prof. R.Ubar DSc, 1986) is a supervisor of the mentioned graduate students except M.Aarna. The supervisor of Margit Aarna is Jaan Raik. The theses of the students are closely related to the research work planned in this proposal. 1. The thesis of A.Jutman Simulation methods for Digital Systems is related to the following problems of the proposal: development of the theory of decision diagrams for modelling digital systems, development of the multi-level models of digital systems, development of the methods and tools for simulating digital systems. 2. The thesis of E.Orasson BIST methods for digital systems has a task to investigate and develop new BIST methods based on combining pseudorandom and deterministic testing with functional BIST. 3. The thesis of H.Kruus Development of methods for optimization of hybrid BIST has a goal to investigate and develop new BIST optimization methods based on using combinatorial optimization algorithms. 4. The thesis of M.Aarna Fault Simulation in Digital Systems has a task to develop new hierarchical fault simulation algorithms, methods and tools targeted to evaluation of the testing quality of BIST in digital systems. 5. The thesis of M.Jenihhin Hybrid BIST in Multi-Core Systems has a goal to investigate and develop new methods for minimizing the test length at given memory constraints in parallel BIST. 5

6 6. The thesis of T.Vassiljeva Modelling Digital Systems with Decision Diagrams is related to the development of methods for generating optimized models for fault simulation in digital systems and for BIST quality estimation. 7. The thesis of J.Smahtina Functional BIST in Digital Systems is related to the development of new methods for improving the quality of functional BIST. Jaan Raik is developing new methods for deterministic test generation and testability calculation. His input for this project is mainly supervising of the thesis of M.Aarna and involvment in the research on functional BIST. Associate prof. Teet Evartson will carry out research on FPGA based designs with the goal to develop methods for evaluation of the quality of BIST on FPGAs. He also will participate and supervise the work on implementing the results of the project in the educational process in TTU with the goal to develop new laboratory tools, works and internet-based teaching materials. Marina Brik is developing test generation methods for sequential cores of SoC, and his results will be used in designing hybrid BIST solutions for SOCs targeted to subsystems with single or multiple sequential cores. The ativities planned in the project will be carried out in a close cooperation with Linköping University in Sweden, with Fraunhofer Institute and TU Ilmenau in Germany. This cooperation is supported by the EU project evikings ( ) and by bilateral projects EST with Fraunhofer Institute and DILDIS with TU Ilmenau. f) Prognosis of publishing and implementing of project results It is expected to publish annually at least 7-8 papers on current research results in internationally recognized journals and conference proceedings. It is also expected to introduce the experimental diagnostic software to be developed in frame of this project into teaching process at the Tallinn Technical University and at universities in other countries of Europe. The results will be used also in the Estonian electronics industry. In the present moment the research group has a contract (industrial project MIKROTEST supported by Estonian Agency of Technology) with the company Artec Design. The goal of the project MIKROTEST is to develop new software tools and methods for designing self-testing digital systems. The expected results of the proposed project will be used in this cooperation to improve the accuracy of the fault simulators and to increase the fault coverage of built-in test generators to be developed in MIKROTEST. g) Importance of the research for science and Estonian economy The general importance of this research for scientific and industrial community of microelectronics lays in the development of a new conception, methods, algorithms and software for design of self-testing digital systems. The known methods use the classical pseudorandom based self-testing methods which are costly in terms of testing time and hardware overhead, and they don t quarantee high fault coverage. The new hybrid BIST and functional BIST based approaches to be developed in the project allow significantly to improve the fault coverage and to reduce the cost of testing. As a short-term importance for Estonian economy first, the cooperation in a form of working contract with the company Artec Design should be mentioned. The expected results of the proposed project will be used in the company and improve its competitiveness in the world market. Secondly, the educational aspects should be mentioned. The competence of the group is internationally recognized and continuously invitations have been made to the group for joining to different joint European project teams. By reaching new scientific results it will be possible to find new financial ressources from Europe and to support by these means the university teaching and R&D environment. As the result of the previous ESF projects G1850 ( ), G1880 ( ), G3658 ( ), G4300 ( ), and European projects SYTIC and VILAB, the Turbo-Tester software has been developed. The software was exchanged with the DIXIcad design software from the company of DIGSIM DATA A.B. in Sweden, which was introduced into the teaching process at the TTU. The total value of this design software exceeds the mentioned grants of the Estonian Science Foundation. This type of multiplicative effect is expected to be achieved also by the proposed project. As a general result of this type of knowledge and technology transfer, the teaching environment at the Computer Engineering Department will be continuously updated and held at the international level, which means great importance for educating students with professional skills on the international level. This fact will also have 6

7 great importance for Estonia in the long-term sense in appearing of new competitive SMEs in the Estonian electronics industry. 7

8 2. Time Schedule of the Project Theoretical research - to investigate the most common BIST architectures of digital systems with the goal to create proper models for representing hardware and memory cost, testing time, fault coverage, and power consumption - to develop suitable architectures for implementing hybrid BIST conception - to investigate the possibilities of using system own functionalities to build up functional BIST schemes 2. Software development - to develop fast and simple cost estimation algorithms and tools for preliminary evaluation of proposed solutions - preparing the software environment for experimental research on functional BIST 3. Experimental work - experimental research of the quality of functional BIST for most common blocks and architectural parts of digital systems 1. Theoretical research - to develop cost models for different hybrid BIST architectures with combinational multi-core networks - to develop methods of calculation the cost and quality of chosen functional BIST schemes - to develop methods for minimizing different cost functions at given constraints for different hybrid BIST architectures with combinational multi-core networks - to develop methods and algorithms to support functional BIST driven design for testability 2. Software development - to develop tools for calulating the cost for different hybrid BIST architectures with combinational multi-core networks - to develop new test generation, fault simulation, test ordering and cost calculation tools and experimental research environments suitable for carrying out the optimization procedures for hybrid BIST - preparing the software environment for experimental research on hybrid BIST architectures with combinational multi-core networks 3. Experimental work - experimental research of the methods of hybrid BIST architectures with combinational multi-core networks 1. Theoretical research - to develop cost models for different hybrid BIST architectures with sequential multi-core networks in system-on-chip - to develop methods of calculation the cost and quality of the functional BIST schemes for multicore networks in complex digital systems - to develop methods for minimizing different cost functions at given constraints for different hybrid BIST architectures with sequential multi-core networks 8

9 to investigate possibilities of combining hybrid and functional BIST methods with design for testability 2. Software development - to develop tools for calulating the cost for different hybrid BIST architectures with sequential multi-core networks - to develop software tools for supporting functional BIST driven design for testability - preparing the software environment for experimental research on hybrid BIST architectures with sequential multi-core networks 3. Experimental work - experimental research of the methods of hybrid BIST architectures with sequential multi-core networks 1. Theoretical research - to develop methods for combining hybrid and functional BIST methods with design for testability - to develop methods and algorithms for optimization of hybrid/functional BIST supported by design for testability 2. Software development - to develop tools for optimization of hybrid/functional BIST combined with design for testability - preparing the software environment for experimental research on hybrid/functional BIST methods 3. Experimental work - experimental research of the methods of hybrid/functional BIST combined with design for testability. 9

10 a) Expected total cost: For EEK For EEK For EEK For EEK Total: EEK 3. Explanation and Breakdown of Costs b) Other financial sources: 1) Framework V - IST REASON - 30 kecu for Financing goals: organization of seminars and tutorials, software licences and maintenance cost, salaries, travel cost 2) Framework V IST EVIKINGS - 45 kecu for Financing goals: organization of conferences and winter schools, software maintenance cost, scholarships, salaries, travel cost c) Breakdown of costs for the first project year 2004: 1) Scholarships: EEK 2) Travel: EEK 3) Overheads (20%): EEK Total: EEK Breakdown of scholarships: 1) 3 PhD students (3 x 8 months, 3500 EEK per month) EEK 2) 3 master students (3 x 8 months, 2500 EEK per month) EEK Total: EEK Breakdown of travel costs: 1) Conference: Design, Automation and Test in Europe (DATE'04), Paris, France, February 16-20, EEK travel: EEK conference fee EEK 2) European Test Symposium (ETS 04) Ajacco (France), May 23-26, EEK travel: EEK conference fee EEK 3) Conference: 11 th Mixed Design of Integr. Circuits and Systems Conf (MIXDES) Szczecin, June 20-22, EEK travel: EEK conference fee EEK 4) 5 th Int. Symposium on Quality Electronic Design (ISQED 04) San Jose, CA, USA, March 22-24, EEK travel: EEK conference fee EEK Total: EEK 10

11 d) Explanation of expenditures for the whole project period ( ): No salaries in the project are planned. The salaries of the senior personnel (R.Ubar, T.Evartson, J.Raik, M.Brik) will be covered from other financial sources, partly from the 2 EC projects mentioned. The main goal of the project is to support the graduate students in carrying out their research towards degrees. 1. Labor costs will be distributed as scholarships for students (in 2004 we will start with: 3 PhD students, 3 MSc students and at least 2-3 Bachelor students). The PhD and MSc students will be payed for the research, for development of software, and for carrying out experiments (part of the payment, 1/3 of total for PhD and MSc students will be covered by EC projects). The BSc students will be payed only from EC projects. 2. Preliminary planning of the work which will be payed from the project is as follows: E.Orasson (PhD student) - Investigation of hybrid BIST methods suitable for different architectural solutions - Development of tools for modeling hybrid BIST architectures - Development of tools and environments for hybrid BIST quality estimation H.Kruus (PhD student) - Investigation of cost models for hybrid BIST solutions - Development of methods for hybrid BIST optimization M.Aarna (MSc student) - Investigation of methods for fault simulation in hybrid BIST architectures - Development of a new high-speed fault simulation tool for complex digital systems M.Jenihhin (MSc student) - Investigation of hybrid BIST methods suitable for testing sequential multi-core architectures in systems-on-chip - Development of methods and algorithms for cost calculation of hybrid BIST solutions for sequential multi-core architectures T.Vassiljeva (MSc student) - Investigation of methods for functional BIST driven design for testability in digital systems - Development of software tools for calculating the quality of functional BIST J.Smahtina (MSc student) - Investigation of methods for implementing functional BIST in complex digital systems - Development of methods and algorithms for analysing the observability in functional BIST schemes 3) Equipment costs, software liscenses and software management costs will not be covered by this project (for that purpose the means of EC projects REASON and EVIKINGS will be used). 4) About 7-8 travels to conferences are planned for each project year, whereas 4 of them are planned to be covered by this project. DATE, ISQED and ETS are the most significant annual conferences of the given field in the World. MIXDES is the most significant conference of the field in the Central-Europe. The proposer belongs to the Program Committees of all of these 4 conferences. The proposer is also the General Vice-Chairman of the European Test Symposium in Ajacco the next year. For presenting current project results, also other European conferences like annual EDCC, EAEEIE, DDECS, NORCHIP, BEC a.o. are also planned. Although the conferences DATE and ETS are world level events, it is still needed to have a recognition to the project outputs directly from oversea. This is the motivation for planning a paper for ISQED. The conference takes place annually in the middle of Silicon Valley, in San Jose, and a lot of participants from the microelectronics industry of this area have always participated in this conference. To cover the travel and accommodation costs, daily allowances and fees of the mentioned 4 conferences will cost in total about 90 thousand EEK. From the budget of this project only 56 thousand EEK is planned. The rest of costs, and the participation in additional conferences will be supported by other resources like from the projects REASON and EVIKINGS. 11