Bandwidth Enhanced Telescopic OTA

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J. of ctive and Passive Electronic Devices, Vol. 5,. 327 334 Rerints available directly from the ublisher Photocoying ermitted by license only 200 Old City Publishing, Inc. Published by license under the OCP Science imrint, a member of the Old City Publishing Grou Bandwidth Enhanced Telescoic OT Tianwang Li,3,*, Bo Ye 2, Jinguang Jiang and Xingcheng Han 3 Deartment of integrated circuits and communication software, Wuhan University, Wuhan, 430079, China 2 Institute of Microelectronics, Shanghai University of Electronic Power, Shanghai, 200090, China 3 Giantec Semiconductor Inc., Shanghai, 20203, China fully differential bandwidth enhanced telescoic oerational transconductance amlifier is resented in this aer. The unit-gain bandwidth of the roosed OT is enhanced by recycling the tail current. Both the conventional and roosed OTs are designed in 0.8 μm CMOS rocess. Simulation results show that there is a 64% imrovement in the unitgain bandwidth comared to that of conventional telescoic oerational transconductance amlifier. Keywords: OT, full differential, unit-gain bandwidth, circuit simulation, ower consumtion. Introduction Low-ower consumtion is an imortant secification in many electronic systems, such as wireless communication and imaging systems. In these electronic systems, analog integrated circuits consume a large art of the ower. Generally seaking, the OT is the block with the most ower consumtion in analog integrated circuits for many alications, such as DC, filter, and VG etc [ 8]. low ower OT design can save the system ower effectively. There is a tradeoff among seed, ower and gain for OT design. Usually these arameters resent contradictory choices for the OT architecture. There are three kinds of OTs: two stage OT, folded-cascode *Corresonding author: tianwangli@yahoo.com 327 327-334 RC08-54 (Li).indd 327 6//200 :48:35 PM

328 Tianwang Li et al. VDD Vb M7 I M8 Vb Vb2 M5 M6 Vb2 Von Vbn2 M3 M4 Vbn2 Vo B Vin M M2 Vinn CMFB M0 2I Figure Conventional telescoic OT. transconductance amlifier and telescoic transconductance amlifier. The telescoic amlifier consumes the least ower comared with the other two amlifiers. The conventional telescoic amlifier is shown in Figure. Recently, telescoic amlifier design researches focus on imroving the gain and outut swing [3,4]. ctually, the ower efficiency of the telescoic OT can be imroved by enhancing the unit-gain bandwidth of the telescoic OT. From Figure, the DC current of M7 is the same as that of M. Only the current which flows in the NMOS differential air transistors hels to imrove the bandwidth. It is well known that less current can imrove the load resistors and imrove the gain of the amlifier. This aer rooses a novel telescoic amlifier which can reduce the current of load transistors M5 ~ M7 by introducing an additional PMOS differential air. The gain and bandwidth of the OT are enhanced. In the following sections, the roosed architecture will be shown and discussed in detail. The aer is organized as follows. Section 2 analyzes the gain and frequency resonse of the conventional telescoic OT. Section 3 describes the roosed architecture design. Section 4 shows the simulation results Section 5 resents a summary and conclusions regarding this work. 2 Conventional telescoic OT design The small signal half equivalent circuit of conventional OT is shown in Figure 2. The voltage gain of the conventional OT is given by: 327-334 RC08-54 (Li).indd 328 6//200 :48:35 PM

Bandwidth Enhanced Telescoic OT 329 M3 r C Vo M Vi Figure 2 Small signal half equivalent circuit of conventional telescoic OT. = G R () V m out where G m and R out reresent the transconductance and outut resistor resectively. In Figure 2, r is the PMOS current mirror small signal equivalent resistance, r = gm5 rds5 rds 7. The outut resistor is Rout = r // gm3 rds3 rds. It is well known that the G = g, so () can be shown as m m (( ) ( )) = g g r r // g r r (2) V m m5 ds5 ds7 m3 ds3 ds The frequency resonse of the conventional telescoic OT in Figure is determined rimarily by the outut dominant ole which is given as out = R C + C out ( ) L (3) where and C is the load caacitor and outut arasitic caacitor resectively. The unit-gain bandwidth ω u of the OT in Figure is ω u gm = C + C The non dominant oles are located at node and B in Figure, which are given as L (4) B, gm, = 34 C (5) where g m3,4 is the transconductance of the cascode transistor (M3, M4), C is the total arasitic caacitors at the node or B. From (4), increasing g m can imrove the unit-gain bandwidth of the conventional OT. It is well known that the gm can be increased by enlarging the current 2I in Figure. It means that 327-334 RC08-54 (Li).indd 329 6//200 :48:37 PM

330 Tianwang Li et al. the ower consumtion of OT is also increased. In this aer, we roose a novel architecture by recycling the tail current. The bandwidth of the roosed OT can be imroved significantly without increasing the ower consumtion. 3 roosed fully differential telescoic oerational transconductor amlifier The roosed fully differential telescoic OT is shown in Figure 3. The transistors M0 ~ M8 use the same architecture with the conventional telescoic amlifier as shown in Figure, a PMOS differential air is introduced comared with conventional telescoic amlifier. The tail current of the PMOS differential air is 2 I, here 0. The PMOS differential air injects current into node and B, which hels to imrove the bandwidth of the amlifier. Furthermore, the PMOS differential air does not consume additional ower, and the ower consumtion of the roosed design is the same as the conventional one. The small signal half equivalent circuit is shown in Figure 4. Comared with Figure 2, there is an additional PMOS transistor contributing to Gm in Figure 4. It is easy to get DC gain and unit-gain bandwidth from Figure 4. The DC gain of the roosed OT is (( ) ( )) = ( g + g ) g r r // g r ( r // r ) V m m0 m5 ds5 ds7 m3 ds3 ds ds0 (6) VDD Vb M9 2 I Vb M7 I M8 Vb Vin M0 M Vinn Von Vb2 M5 M6 Vb2 Vo Vbn2 M3 M4 Vbn2 B Vin M M2 Vinn CMFB M0 2I Figure 3 Proosed telescoic OT. 327-334 RC08-54 (Li).indd 330 6//200 :48:38 PM

Bandwidth Enhanced Telescoic OT 33 Vi M0 M3 rl C Vo Ml Vi Figure 4 Small signal half equivalent circuit of roosed telescoic OT. The unit-gain bandwidth of the roosed design is g = C + g m m0 ω u + C L (7) The outut dominant ole of the roosed design is given as out = R C + C out ( ) L (8) The non dominant oles of the roosed OT are also located at node and B in Figure 3, which is given as B, gm, = 34 C (9) From (4) and (7), the denominator is C + L C. In the roosed design of Figure 3, the outut arasitic caacitor is reduced because the current flows in the M3~M8 is smaller than that of the conventional OT in Figure. These transistors can be designed by using small size. The numerator in (7) is gm+ gm0 comaring with g m in (4). So the bandwidth of the roosed OT is enhanced without increasing the ower consumtion. For a certain unitgain bandwidth, the ower consumtion of the roosed design can be reduced comaring with the conventional telescoic OT. This will be benefit for imroving the ower efficiency of the analog system. 3 Simulation results Both the conventional and roosed telescoic amlifier are designed and simulated in 0.8 µm CMOS rocess. The load caacitor is 2F and target unitgain bandwidth is 200 MHz. To comare the ower efficiency of the roosed 327-334 RC08-54 (Li).indd 33 6//200 :48:39 PM

332 Tianwang Li et al. design with the conventional telescoic amlifier, an ideal CMFB architecture is used. Two roosed OT simulation results are resented in this aer. The first roosed design uses the same current with the conventional OT, the second roosed design achieves the same unit-gain bandwidth with the conventional OT. The C frequency resonses of the conventional OT and the roosed designs are shown in the Figure 5, Figure 6, Figure 7, resectively. It can be found clearly that the unit-gain bandwidth of the conventional design is 228 MHz, and the unit-gain bandwidth of the roosed OT is 375 MHz. The unit-gain bandwidth of the roosed design is about 64% higher than that of the conventional design. Moreover, the DC gain of the roosed design is 6dB higher than that of the conventional telescoic amlifier. Figure 5 Frequency resonse of the conventional OT. Figure 6 Frequency resonse of the roosed OT. 327-334 RC08-54 (Li).indd 332 6//200 :48:40 PM

Bandwidth Enhanced Telescoic OT 333 Figure 7 Frequency resonse of the roosed OT2. Table Performance comarison of conventional OT and the roosed design. Parameter Conventional OT Proosed OT Proosed OT2 UGBW(MHz) 228 372 224 Power(µ) 600 600 300 Gain(dB) 5 57 58 PM(deg) 88 8 8 Suly voltage.8.8.8 Technology 0.8 µm CMOS The unit-gain bandwidth of the second roosed OT is 224 MHz, which is nearly the same as that of the conventional OT. The ower consumtion of the second roosed design is 300 u, which is 50% smaller than that of the conventional OT. The erformance summary of the designs is summarized in table. 4 Conclusions bandwidth enhanced telescoic oerational amlifier is resented in this aer. The bandwidth of the telescoic OT is imroved by recycling the tail current. Comaring with the conventional telescoic OT, the roosed design can achieve the same unit-gain bandwidth with less current consumtion. It can be widely used for low ower alications. 327-334 RC08-54 (Li).indd 333 6//200 :48:40 PM

334 Tianwang Li et al. References [] Liu M., Huang K., Ou Wei., et al. low voltage-ower 3-bit 6 MSPS CMOS ieline DC. IEEE J Solid-State Circuits, 2004, 39, 834 836. [2] Ming B., Kim P., Bowman F. W, et al. 69 mw 0-bit 80 MSamle/s ieline DC. IEEE J Solid-State Circuits, 2003, 38, 203 2039. [3] Vecchi D., zzolini C., Boni., et al. 00-MS/s Track-and-Hold mlifier in 0.8-µm CMOS. Proceeding of Euroean Solid-State Circuits Conference, 2005, 259 262. [4] Gulati K, Lee H S. high swing telescoic oerational amlifier. IEEE J Solid-State Circuits, 998, 33, 200 209. [5] rias J., Boccuzzi V and Qunintanilla L., et al. Low ower ieline DC for wireless LNs. IEEE J Solid-State Circuits, 2004, 39, 338-340. [6] Ryu S., Ray S., and Song B. et al. 4-b linear caacitor for self-trimming ielined DC. IEEE J Solid-State Circuits, 2004, 39, 2046 205. [7] Shu Y., and Song B. 5-b linear 20-Ms/s ielined DC digitally calibrated with signal deendant dithering. IEEE J Solid-State Circuits, 2008, 43, 342 350. [8] Lee B., Min B., and Manganaro G., et al. 4b 00MS/s ielined DC with a merged active S/H and first MDC, ISSCC Dig. Tech. Paers, 2008, 248 250. 327-334 RC08-54 (Li).indd 334 6//200 :48:40 PM