Simulation and Optimization of Analog Circuits
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1 Simulation and Optimization of Analog Circuits (Optimization Methods for Circuit Design) Helmut Graeb Institute of Electronic Design Automation Technische Universitaet Muenchen
2 Sizing Rules Design constraints for geometries and currents/voltages of transistors Ensure function and robustness Automatic construction for given circuit netlist hierarchical library of transistor groups structural analysis of netlist [Gräb, Zizala, Eckmüller, Antreich: The Sizing Rules Method for Analog Integrated Circuit Design, IEEE International Conference on Computer-Aided Design (ICCAD), 2001] [Massier, Gräb, Schlichtmann: The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis, IEEE TCAD 2008] 2
3 Sizing Rules MOS Transistor (1) Saturation region voltage controlled current source function electrical 3
4 Sizing Rules MOS Transistor (2) Variance in i DS due to manufacture robustness geometrical (K, W, L, U th uncorrelated) [Lakshmikumar et al. IEEE JSSC 1986] 4
5 Sizing Rules Current Mirror function (current ratio) geometrical robustness (compensation U th mismatch) electrical function (compensation effect) electrical 5
6 MOS Transistor Pairs 203 variants 8 transistor pairs with design-relevant function 2-transistorcurrent mirror Level shifter Differential pair Flipflop Voltage reference 1 Voltage reference 2 Current mirror load Cascode pair 6
7 MOS Transistor Groups Cascode Current mirror (cm) Wilson cm Wilson 2 cm 4-transistor cm Wide-swing cascode cm cm Level shifter bank cm bank Differential stage 7
8 Library MOS Transistor Groups differential stage consists of current mirror is a wide swing cascode current mirror 2 cascode current Wilson current mirror 2 Wilson current 4-transistor current mirror mirror 2 2 mirror 2 2 different. pair cascode pair voltage reference 2 2-trans.- current mirror 4 4 # sizing rules VCCS 6 level shifter MOS transistor voltage reference VCR current mirror load 3 8
9 Assignment Ambiguities: Differential Pairs 7 pairs with structure of differential pair (dp) only 1 pair is a dp 9
10 Arbitration of Assignment Ambiguities: Differential Pairs Current mirror Current mirror Differential pair current mirror rules out differential pair 10
11 Ambiguity Arbitration Rules flipflop vr2 vr1 cml Wilson CM WSCM rules out if blue transistor is in both cm ls dp 11
12 Structural Analysis of a Netlist netlist library transistor groups structural analysis: search for sub-graph isomorphisms (bottom up) instantiation of sizing rules (top down) 12
13 Structural Analysis CMOS Example voltage reference 1 current mirror load 2-trans. current mirror level shifter differential pair 4-transistor current mirror current mirror (bank) level shifter (bank) cascode current mirror 30 equations inequalities 190 sizing rules casc. curr. mirror bank differential stage 13
14 Automatic Sizing min. nominal max. without sizing rules with sizing rules 126 simulations ( ) 45 simulations - Efficiency and convergence of sizing process - Circuit robustness 14
15 Basic Bipolar Building Blocks Transistor Pairs 203 possible transistor pair structures 6 pairs with a design-relevant function Further building blocks formed by combining existing ones Simple Current Mirror Level Shifter Differential Pair Cross-Coupled Pair Darlington Configuration 1 Darlington Configuration 2 15
16 Complete Analog Bipolar Building Block Library Differential Stage consists of Current Mirror is a Hierarchy Level 3 Buffered Current Mirror 5 Cascode Current Mirror Improved Wilson Current Mirror Wilson Current Mirror Differential Pair Darlington Configuration 1 Darlington Configuration 2 Simple Current Mirror # Sizing Rules Bipolar Transistor (forward active region) 3 Level Shifter 3 Cross- Coupled Pair
17 Robustness Function Technische Universität München Example: Sizing Rules for a Bipolar Simple Current Mirror i c2 k = = i c1 n 2 n 1 i c1 Q 1 i c2 Q 2 n 1 n 2 geometrical electrical A 1 = A 2 basic function v be1,2 V be0 v ce1,2 v be1,2 V ce sat v ce1 v ce2 ΔV ce max forward active region Early effect A 1,2 A min low freq. noise V be min v be 1,2 V be max maximum forward current gain 17
18 Preparation of the Netlist for Structure Recognition Transistors with resistors npn npn + res Parallel transistors 1 npn n npn BiCMOS library n npn npn NMOS NMOS 18
19 Structural Analysis BiCMOS Example Simple current mirror Differential pair Darlington configuration 2 Buffered current mirror Differential stage 6 equations + 61 inequalities = 67 sizing rules 19
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