BASIC LOGIC GATES 1 E Basic Logic Gates Richard E. Haskell All digital systems are made from a few basic digital circuits that we call logic gates. These circuits perform the basic logic functions that we will describe in this chapter. The physical realization of these logic gates has changed over the years from mechanical relays to electronic vacuum tubes to transistors to integrated circuits containing thousands of transistors. In this appendix you will learn: Definitions of the basic gates in terms of truth tables and logic equations DeMorgan's Theorem How gates defined in terms of positive and negative logic are related To use multiple-input gates How to perform a sum of products and a product of sums design from a truth table specification E.1 TRUTH TABLES AND LOGIC EQUATIONS All data in a computer are stored as binary digits. These bits can be thought of as the logical values 0 and 1, where a 1 is considered to be true and a 0 is considered to be false. The actual physical quantities associated with a 0 and a 1 might be a low (0 volts) or high (5 volts) voltage. A truth table will define the logical outputs (0 or 1) of the gate for all possible logical inputs. In this section we will define the three basic gates, NOT, AND, and OR, by means of their truth tables. We will then use these basic gates to define some additional gates. Using truth tables we will discover the important De Morgan's theorem. We will then consider the possibility of considering 0 to be true and 1 to be false. This will give us a better insight into the various gates. Finally, we will look at the definitions of multiple-input gates.
2 APPENDI E The Three Basic Gates NOT gate. The definition of the NOT gate, or inverter, is shown in Fig. E.1. The logic symbol for the inverter has a single input and a single output. The value of is the complement of the input. Thus, as shown in the truth table in Fig. E.1 if is 0, then is 1, whereas if is 1, then is 0. The NOT gate simply inverts the logic state of the input. NOT = ~ 0 1 1 0 Figure E.1 The NOT gate or inverter. The equation for the inverter in Fig. E.1 is given as = ~. We read this as " equals NOT." In this appendix we will use the exclamation point ~ as the negation operator. The exclamation point, prime, bar, slash, and are sometimes used to indicate the NOT operation, as in =! = ' = = / = The reason we will use = ~ is that this is the notation used by the Verilog software we will use to compile our logic equations to program a complex programmable logic device (CPLD). Inasmuch as all the equations you will write to program these devices will use the ~ as the negation operator, you might as well get used to it from the beginning. AND Gate. The definition of the AND gate is shown in Fig. E.2. The AND gate logic symbol has two inputs, and and the single output. From the truth table in Fig. E.2 we see that the output of an AND gate is 1 (true or high) only if both inputs, and, are 1 (true or high). The output will be zero if either or or both are zero. Figure E.2 The AND gate. The equation for the AND gate in Fig. E.2 is given as = &. We read this as " equals AND." In this book we will use the ampersand & as the and operator. Other common ways to indicate the AND operation are
BASIC LOGIC GATES 3 * V The last form involving the juxtaposition of and limits you to logic variables containing a single letter. We will be using names for our logic variables in which case could represent a single logic variable. The reason we will use = & for the AND operation is that this is the notation used by the Verilog software to program a CPLD. OR Gate. The definition of the OR gate is shown in Fig. E.3. The OR gate logic symbol has two inputs, and, and the single output. From the truth table in Fig. E.3 we see that the output of an OR gate is 1 (true or high) if either input, or, or both are 1 (true or high). The output will be zero only if both and are zero. OR = 0 0 0 1 1 1 Figure E.3 The OR gate. The equation for the OR gate in Fig. E.3 is given as =. We read this as " equals OR." In this appendix we will use the vertical line as the OR operator. Other common ways to indicate the OR operation are # + V U Again the reason we will use = for the OR operation is that this is the notation used by the Verilog software to program a PLD. As surprising as it may seem, all digital systems, including all computers, can be built from only the three basic gates: NOT, AND, and OR. We will begin by showing that three other common gates can be built from our basic three. Three New Gates Three new gates, NAND, NOR, and Exclusive-OR, can be formed from our three basic gates: NOT, AND, and OR. NAND Gate. The definition of the NAND gate is shown in Fig. E.4. The logic symbol for a NAND gate is like an AND gate with a small circle (or bubble) on the output. From the truth table in Fig. E.4, we see that the output of a NAND gate is 0 (low) only if both inputs are 1 (high). The NAND gate is equivalent to an AND gate followed by an inverter (NOT-AND), as shown by the two truth tables in Fig. E.4.
4 APPENDI E NAND = ~( & ) 0 0 1 NOT-AND W W 0 0 0 1 0 1 0 0 1 W = & 1 = ~W = ~( & ) Figure E.4 The NAND gate. NOR Gate. The definition of the NOR gate is shown in Fig. E.5. The logic symbol for a NOR gate is like an OR gate with a small circle (or bubble) on the output. From the truth table in Fig. E.5 we see that the output of a NOR gate is 1 (high) only if both inputs are 0 (low). The NOR gate is equivalent to an OR gate followed by an inverter (NOT-OR), as shown by the two truth tables in Fig. E.5. NOR = ~( ) 0 0 1 0 1 0 1 0 0 NOT-OR W W 0 0 0 1 0 0 W = 1 = ~W = ~( ) Figure E.5 The NOR gate. Exclusive-OR Gate. The definition of the Exclusive-OR, or OR, gate is shown in Fig. E.6. The OR gate logic symbol is like an OR gate symbol with an extra curved vertical line on the input. From the truth table in Fig. E.6 we see that the output of an OR gate is 1 (true or high) if either input, or, is 1 (true or high), but not both. The output will be zero if both and are the same (either both 1 or both 0). The equation for the OR gate in Fig. E.6 is given as = ^. In this book we will use the symbol ^ as the OR operator. Sometimes the symbol or the dollar sign $ is used to denote Exclusive-OR. We will use the symbol ^ because that is the symbol recognized by the Verilog software used to program a CPLD.
BASIC LOGIC GATES 5 OR = ^ 0 0 0 ~ ~ ~ & & ~ Figure E.6 The Exclusive-OR (OR) gate. = (~ & ) ( & ~) ~ ~ ~ & & ~ 0 0 0 0 0 1 0 0 1 0 0 0 0 From Fig. E.6 we see that the OR gate can be formed with two inverters, two AND gates and an OR gate. Note from this figure and truth table that the Exclusive-OR can be written as = ^ = (~ & ) ( & ~) Positive and Negative Logic: De Morgan's Theorem In the above examples we considered a 1 to be true and a 0 to be false. This is called positive logic. Another way to interpret our NAND and NOR gates is to think of an output containing the bubble (or small circle) as being true when the output is 0. We say that the output is active low. This is negative logic. Then the NAND gate is just an AND gate in which the output is true (0 or active low) only when both inputs are true (1 or active high). Look at the truth table for the NAND gate in Fig. E.4 to see this. We can even put bubbles on the input to our gates and think of them as having true values when the inputs are 0 or active low (negative logic). Remember that the bubble is equivalent to putting an inverter (NOT gate) there. If we put two bubbles on the input to an OR gate, we get a NAND gate as shown in Fig. E.7. Compare the truth table in Fig. E.7 with that in Fig. E.4 to see that it really is a NAND gate. The OR-type symbol in Fig. E.7 is just an alternate representation of a NAND gate. Note that in the representation shown in Fig. E.7 we can think of a NAND gate as an OR gate in which the output is true (1 or active high) if either or both inputs are true (0 or active low). Because the two forms of the NAND gate shown in Figs. E.4 and E.7 are equivalent, that is, they have the same truth table, the two equations for the NAND gate given in the figures must be equal. We can therefore write = ~ ~ = ~( & ) (E.1) which is one form of De Morgan's theorem.
6 APPENDI E NAND 0 0 1 = ~ ~ ~ ~ ~ ~ 0 1 0 1 1 0 0 0 Figure E.7 Alternate representation of a NAND gate. Let's apply this same idea of thinking of an output containing the bubble as being true when the output is 0, or active low, to the NOR gate in Fig. E.5. Then the NOR gate is just an OR gate in which the output is true (0 or active low) when either or both inputs are true (1 or active high). If we put two bubbles on the input to an AND gate, we get a NOR gate, as shown in Fig. E.8. Compare the truth table in Fig. E.8 with that in Fig. E.5 to see that it really is a NOR gate. The AND-type symbol in Fig. E.8 is just an alternate representation of a NOR gate. NOR = ~ & ~ 0 0 1 0 1 0 1 0 0 ~ ~ ~ ~ 0 1 0 0 1 0 0 1 0 0 0 Figure E.8 An alternate representation of a NOR gate. Note in the representation shown in Fig. E.8 that we can think of a NOR gate as an AND gate in which the output is true (1 or active high) only if both inputs are true (0 or active low). Because the two forms of the NOR gate shown in Figs. E.5 and E.8 are equivalent, that is, they have the same truth table, the two equations for the NOR gate given in these figures must be equal. We can therefore write = ~ & ~ = ~( ) (E.2)
BASIC LOGIC GATES 7 which is another form of De Morgan's theorem. The symbol for an inverter can also have the bubble on the input, as shown in Fig. E.9. From this figure we see that ~~ = (E.3) which represents two inverters forming a noninverting buffer. NOT = ~ 0 1 1 0 ~~ = ~ ~~ = Figure E.9 An alternate representation of an inverter. From Eqs. (E.1) to (E.3) we see that we can state both forms of De Morgan's theorem as follows: For example, 1. NOT all variables. 2. Change & to or to &. 3. NOT the result. ~ ~ = ~(~~ & ~~) = ~( & ) ~( & ) = ~~(~ ~) = ~ ~ ~ & ~ = ~(~~ ~~) = ~( ) ~( ) = ~~(~ & ~) = ~ & ~ (E.4) Multiple-input Gates The AND, OR, NAND, and NOR gates we have studied so far are not limited to having two inputs. The basic definitions hold for multiple inputs. For example, the output 1 of the 4-input AND gate in Fig. E.10 will be high (1) only if all four inputs are high (1). The output 2 of the 8-input OR gate in Fig. E.10 will be high (1) if any of the eight inputs are high (1). It will only be low (0) when all eight inputs are low (0). The output 3 of the 8-input NAND gate in Fig. E.10 will be low (0) only if all eight inputs are high (1). The output 4 of the 5-input NOR gate in Fig. E.10 will be low (0) if any of the five inputs are high (1). It will only be high (1) when all five inputs are low (0).
8 APPENDI E 1 2 3 4 Figure E.10 Multiple-input gates. E.2 BASIC DIGITAL DESIGN It is easy to design a digital circuit from its truth table definition. We will illustrate the procedure by designing the Exclusive-OR circuit shown in Fig. E.6. There are two different methods of design that lead to two different circuits that perform the same function. We will look at each of these methods separately. Sum of Products Design We can form a product term, called a minterm, for each row of a truth table. The minterm is formed by ANDing together a value associated with each input variable. If the value of the variable in a particular row of the truth table is 1, we include the variable name, such as. If the value of the variable in a particular row of the truth table is 0, we include the negation of the variable name, such as ~. Thus, the minterm in row 0 (numbering the rows from 0 to 3) will be m0 = ~ & ~ because both and are 0 in this row as shown in Fig. E.11. Note that the value of minterm m0 will be 1 when both and are zero. On the other hand the minterm in row 2 will be m2 = & ~. Note that the value of minterm m2 will be 1 when = 1 and = 0. All four minterms are shown in Fig. E.11. minterms 0 0 m0 = ~ & ~ 0 0 0 0 1 m1 = ~ & m1 = ~ & 1 0 m2 = & ~ m2 = & ~ 1 1 m3 = & = m1 m2 = (~ & ) ( & ~) Figure E.11 Sum of products design based on the 1's of the output. On the right side of Fig. E.11 we show the truth table for the Exclusive-OR function. If we focus on the rows in which the output is 1 (true), we see that the output will be true (1) if either the minterm m1 is true or if the minterm m2 is true. Note that m1 will be true if is 0 and is 1 because then ~ & will be 1. We can then write the
BASIC LOGIC GATES 9 equation for by simply ORing the minterms associated with each output that is 1. From Fig. E.11 we see that = m1 m2 = (~ & ) ( & ~) (E.5) which is the same as the Exclusive-OR equation we used in Fig. E.6. We will assume the following order of precedence for the logical operators ~, & and. 1. All ~ operations are done first. 2. All & operations are done next. 3. All operations are done last. Equation (E.5) can then be written without the parentheses as = ~ & & ~ (E.6) ORing all the minterms associated with each 1 in the output column of a truth table leads to a sum of products design. The OR operator is a logical sum and the AND operator & is a logical product. The logical circuit corresponding to Eq. (E.6) is the one shown in Fig. E.6. Product of Sums Design Instead of focusing on the 1's in the output column of a truth table, suppose we focus on the 0's, as shown in Fig. E.12. Note that in this case is NOT the minterm m0 AND it is NOT the minterm m3. What does it mean to be NOT a minterm? From the definitions of minterms in Fig. E.11 and using De Morgan's theorem from Eq. (E.4), we can write NOT minterm m0 = ~m0 = ~(~ & ~) = ~~( ) = We call this the maxterm, M0. The maxterms for all rows in the truth table are given in Fig. E.13. Note that each maxterm is NOT the corresponding minterm. Use De Morgan's theorem to verify each maxterm expression. 0 0 0 is NOT minterm m0 AND it is NOT minterm m3 = ~m0 & ~m3 Figure E.12 Focusing on the 0's will lead to a product of sums design.
10 APPENDI E minterms maxterms 0 0 m0 = ~ & ~ M0 = ~m0 = 0 1 m1 = ~ & M1 = ~m1 = ~ 1 0 m2 = & ~ M2 = ~m2 = ~ 1 1 m3 = & M3 = ~m3 = ~ ~ Figure E.13 A maxterm is NOT the corresponding minterm. Combining the results in Figs. E.12 and E.13 we see that we can write an equation for as the product (&) of all maxterms for rows in which the output is a zero. Thus, as shown in Fig. E.14, the equation for the Exclusive-OR is = M0 & M3 = ( ) & (~ ~) (E.7) which is in the form of a product (&) of sums ( ). The logic circuit corresponding to Eq. (E.7) is shown in Fig. E.15. Compare this with the Exclusive-OR circuit shown in Fig. E.6. Note that different logic circuits can perform the identical function. 0 0 0 M0 = M3 = ~ ~ = M0 & M3 = ( ) & (~ ~) Figure E.14 Product of sums design based on the 0's of the output. ~ ~!! = ( ) & (~ ~) ~ ~ ~ ~ 0 0 1 0 0 1 1 1 1 0 1 1 0 1 0 0 Figure E.15 Logic diagram for product of sums Exclusive-OR design.