DOUBLE DATA RATE (DDR) SDRAM

DOUBLE DATA RATE (DDR) SDRAM 256Mb: x8, x6 DDR 4 SDRAM Addendum MT46V32M8 8 MEG X 8 X 4 BANKS MT46V6M6 4 MEG X 6 X 4 BANKS For the latest data sheet revisions, please refer to the Micron Website: www.micron.com/dramds Features 2 MHz Clock, 4 Mb/s/p data rate Low Latency DDR4B (333) VDD = +2.6V ±.V VDDQ = +2.6V ±.V Bidirectional data strobe (DQS) transmitted/ received with data, i.e., sourcesynchronous data capture Internal, pipelined doubledatarate (DDR) architecture; two data accesses per clock cycle Differential clock inputs (CK and CK#) Commands entered on each positive CK edge DQS edgealigned with data for READs; centeraligned with data for WRITEs DLL to align DQ and DQS transitions with CK Four internal banks for concurrent operation Data mask (DM) for masking write data Programmable burst lengths: 2, 4, or 8 Concurrent Auto Precharge option supported Auto Refresh and Self Refresh Modes t RAS lockout ( t RAP = t RCD) OPTIONS Marking Configuration 32 Meg x 8 (8 Meg x 8 x 4 banks) 32M8 6 Meg x 6 (4 Meg x 6 x 4 banks) 6M6 Plastic Package 66Pin TSOP TG (4mil with.65mm pin pitch) 66Pin TSOP Leadfree P (4mil with.65mm pin pitch) Timing Cycle Time 5ns @ CL = 3 () 5B Self Refresh Standard none NOTE:. Supports PC32 modules with 333 timing General Description The DDR4 SDRAM is a highspeed CMOS, dynamic randomaccess memory that operates at a frequency of 2 MHz (tck=5ns) with a peak data transfer rate of 4Mb/s/p. DDR4 continues to use the JEDEC standard SSTL_2 interface and the 2nprefetch architecture. The base Micron 256Mb data sheet provides full specifications and functionality unless specified herein. This addendum data sheet concentrates on the critical parameters and key differences required to support the enhanced DDR4 speeds. Table : Configuration ARCHITECTURE 32 MEG X 8 6 MEG X 6 Configuration 8 Meg x 8 x 4 banks 4 Meg x 6 x 4 banks Refresh Count 8K 8K Row Addressing 8K (AA2) 8K (AA2) Bank Addressing 4 (BA, BA) 4 (BA, BA) Column Addressing K (AA9) 52 (AA8) Table 2: SPEED GRADE Key Timing Parameters CLOCK RATE CL = 3 DATAOUT WINDOW 2 5B 2 MHz.6ns ±7ps +4ps NOTE:. CL = CAS (Read) Latency 2. With a 5/5 clock duty cycle ACCESS WINDOW DQSDQ SKEW 95aef8a6e5f 256Mbx8x6DDR4.fm Rev. C 5/3 EN 23 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFEREE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON S PRODUCTION DATA SHEET SPECIFICATIONS.

256Mb: x8, x6 DDR 4 SDRAM Addendum Figure : 66pin TSOP Package Dimension PIN # ID..65 TYP +..5 22.22 ±.8.32 ±.75 TYP DETAIL A GAGE PLANE.2 MAX.7.6 ±.8.25.8 TYP.5 ±.. (2X).76 ±.. +.3.5.2 SEE DETAIL A Figure 2: 66pin TSOP Package Pin Assignment x8 x6 VDD VDD DQ DQ VDDQ VDDQ DQ DQ DQ2 Q VssQ DQ3 DQ2 DQ4 VDDQ VDDQ DQ5 DQ3 DQ6 Q VssQ DQ7 VDDQ VDDQ LDQS VDD VDD DNU DNU LDM WE# WE# CAS# CAS# RAS# RAS# CS# CS# BA BA BA BA A/AP A/AP A A A A A2 A2 A3 A3 VDD VDD 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 2 22 23 24 25 26 27 28 29 3 3 32 33 66 65 64 63 62 6 6 59 58 57 56 55 54 53 52 5 5 49 48 47 46 45 44 43 42 4 4 39 38 37 36 35 34 x6 DQ5 Q DQ4 DQ3 VDDQ DQ2 DQ Q DQ DQ9 VDDQ DQ8 Q UDQS DNU VREF UDM CK# CK CKE A2 A A9 A8 A7 A6 A5 A4 x8 DQ7 Q DQ6 VDDQ DQ5 Q DQ4 VDDQ Q DQS DNU VREF DM CK# CK CKE A2 A A9 A8 A7 A6 A5 A4 NOTE:. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is.25mm per side. 95aef8a6e5f 256Mbx8x6DDR4.fm Rev. C 5/3 EN 2 23 Micron Technology, Inc. All rights reserved.

Table 3: Pin Descriptions 256Mb: x8, x6 DDR 4 SDRAM Addendum PIN NUMBERS SYMBOL TYPE DESCRIPTION 45, 46 CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. 44 CKE Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWERDOWN and SELF REFRESH operations (all banks idle), or ACTIVE POWERDOWN (row ACTIVE in any bank). CKE is synchronous for POWERDOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK#, and CKE) are disabled during POWERDOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought high. After CKE is brought high it becomes an SSTL_2 input only. 24 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. 23, 22, 2 RAS#,CAS#, WE# Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the commandbeingentered. 47 2, 47 DM LDM, UDM Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are inputonly, the DM loading is designed to match that of DQ and DQS pins. For the x6 DM for DQ DQ7 and UDM is a DM for D8 D5. Pin 2 is a on x8. 26, 27 BA, BA Input Bank Address Inputs: BA and BA define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. 293 32, 35, 36 37, 38, 39 4, 28, 4 42 2, 5, 8, 56, 59 62, 65 2, 4, 5, 7, 8,,, 3, 54, 56, 57, 59, 6, 62, 63, 65 A, A, A2 A3, A4, A5 A6, A7, A8 A9, A, A A2 DQ2 DQ35 DQ67 DQ DQ2 DQ3 DQ5 DQ6 DQ8 DQ9 DQ DQ2 DQ4 DQ5 Input I/O I/O Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A LOW, bank selected by BA, BA) or all banks (A HIGH). The address inputs also provide the opcode during a MODE REGISTER SET command. BA and BA define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Data Input/Output. Data bus for x8 Data Input/Output: Data bus for x6 (Pins 4, 7,, 3, 54, 57, 6, 63 are for the x8) 95aef8a6e5f 256Mbx8x6DDR4.fm Rev. C 5/3 EN 3 23 Micron Technology, Inc. All rights reserved.

Table 3: 5 6, 5 Pin Descriptions (Continued) PIN NUMBERS SYMBOL TYPE DESCRIPTION DQS LDQS, UDQS I/O 256Mb: x8, x6 DDR 4 SDRAM Addendum Data Strobe: Output with read data, input with write data. DQS is edgealigned with read data, centered in write data. It is used to capture data. for the x6, LDQS is DQS for DQ DQ7 and UDQS is DQS for DQ8 DQ5. Pin 6 is a on x8. 4, 7, 25, 43, 53 No Connect: These pins should be left unconnected. 9, 5 DNU Do Not Use: Must float to minimize noise on Vref 3, 9, 5, 55, 6 VDDQ Supply DQ Power Supply: +2.6V ±.V. Isolated on the die for improved noise immunity. 6, 2, 52, 58, 64 Q Supply DQ Ground. Isolated on the die for improved noise immunity., 8, 33 VDD Supply Power Supply: +2.6V ±.V. 4, 48, 66 Supply Ground. 49 VREF Supply SSTL_2 reference voltage. 95aef8a6e5f 256Mbx8x6DDR4.fm Rev. C 5/3 EN 4 23 Micron Technology, Inc. All rights reserved.

256Mb: x8, x6 DDR 4 SDRAM Addendum Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency should be set to 3 clocks, as shown in the CAS Latency Diagram and Mode Register Definition Diagram. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. states should not be used as unknown operation or incompatibility with future versions may result. Table 4: CAS Latency (CL) ALLOWABLE OPERATING CLOCK FREQUEY (MHZ) SPEED CL = 3 CL = 2.5 CL = 2 5B 33MHz f 2MHz 75MHz f 67MHz 75MHz f 33MHz Figure 3: Mode Register Definition Diagram Figure 4: Example CAS Latency Diagram with CL=3 BA BA A2 A A A9 A8 A7 A6 A5 A4 A3 A2 A A Address Bus CK# T T T2 T2n T3 T3n 4 3 * * 2 9 8 7 6 5 4 3 2 Operating Mode CAS Latency BT Burst Length Mode Register (Mx) CK COMMAND READ NOP NOP NOP * M4 and M3 (BA and BA) must be, to select the base mode register (vs. the extended mode register). M2 M M Burst Length M3 = M3 = 2 2 4 4 8 8 DQS DQ CL = 3 Burst Length = 4 in the cases shown Shown with nominal t AC and nominal t DSDQ TRANSITIONING DATA DON T CARE M3 Burst Type Sequential Interleaved M6 M5 M4 CAS Latency 2 3 2.5 M2 M M M9 M8 M7 M6M Valid Valid Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved 95aef8a6e5f 256Mbx8x6DDR4.fm Rev. C 5/3 EN 5 23 Micron Technology, Inc. All rights reserved.

256Mb: x8, x6 DDR 4 SDRAM Addendum Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. VDD Supply Voltage Relative to Vss...V to +3.6V VDDQ Supply Voltage Relative to...v to +3.6V VREF and Inputs Voltage Relative to...v to +3.6V I/O Pins Voltage Relative to....5v to VDDQ +.5V Operating Temperature, T A (ambient)... C to +7 C Storage Temperature (plastic)...55 C to +5 C Power Dissipation...W Short Circuit Output Current...5mA Table 5: DC Electrical Characteristics and Operating Conditions C T A +7 C; VDDQ = +2.6V ±.V, VDD = +2.6V ±.V Notes: 5, 6, Refer to Base 256Mb Data Sheet, page 663 for all notes except 53 below. PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Supply Voltage VDD 2.5 2.7 V 36, 4, 53 I/O Supply Voltage VDDQ 2.5 2.7 V 36, 4, 44,53 I/O Reference Voltage VREF.49 x VDDQ.5 x VDDQ V 6, 44 I/O Termination Voltage (system) VTT VREF.4 VREF +.4 V 7, 44 Input High (Logic ) Voltage VIH(DC) VREF +.5 VDD +.3 V 28 Input Low (Logic ) Voltage VIL(DC).3 VREF.5 V 28 INPUT LEAKAGE CURRENT II 2 2 µa Any input V VIN VDD, VREF Pin V VIN.35V (All other pins not under test = V) OUTPUT LEAKAGE CURRENT IOZ 5 5 µa (DQs are disabled; V VOUT VDDQ) OUTPUT LEVELS: Full drive option IOH 6.8 ma 37, 39 High Current (VOUT = VDDQ.373V, minimum VREF, minimum VTT) IOL 6.8 ma OUTPUT LEVELS: Reduced drive option x6 only IOHR 9 ma 38, 39 High Current (VOUT = VDDQ.763V, minimum VREF, minimum VTT) Low Current (VOUT =.763V, maximum VREF, maximum VTT) IOLR 9 ma Note 53. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 2MHz. Any noise above 2MHz at the DRAM generated from any source other than the DRAM itself may not exceed the DC voltage range of 2.6V ± mv. 95aef8a6e5f 256Mbx8x6DDR4.fm Rev. C 5/3 EN 6 23 Micron Technology, Inc. All rights reserved.

Table 6: AC Input Operating Conditions C T A +7 C; VDDQ = +2.6V ±.V, VDD = +2.6V ±.V Notes: 5, 6, Refer to Base 256Mb Data Sheet, page 663 for all notes. 256Mb: x8, x6 DDR 4 SDRAM Addendum PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES Input High (Logic ) Voltage VIH(AC) VREF +.3 V 4, 28, 4 Input Low (Logic ) Voltage VIL(AC) VREF.3 V 4, 28, 4 I/O Reference Voltage VREF(AC).49 x VDDQ.5 x VDDQ V 6 Table 7: Capacitance (x8 TSOP) Note: 3; Refer to Base 256Mb Data Sheet, page 663 for all notes. PARAMETER SYMBOL MIN MAX UNITS NOTES Delta Input/Output Capacitance: DQDQ7 DCIO.5 pf 24 Delta Input Capacitance: Command and Address DCI.5 pf 29 Delta Input Capacitance: CK, CK# DCI2.25 pf 29 Input/Output Capacitance: DQs, DQS, DM CIO 4. 5. pf Input Capacitance: Command and Address CI 2. 3. pf Input Capacitance: CK, CK# CI2 2. 3. pf Input Capacitance: CKE CI3 2. 3. pf Table 8: Capacitance (x6 TSOP) Note: 3; Refer to Base 256Mb Data Sheet, page 663 for all notes. PARAMETER SYMBOL MIN MAX UNITS NOTES Delta Input/Output Capacitance: DQDQ7, LDQS, LDM DCIOL.5 pf 24 Delta Input/Output Capacitance: DQ8DQ5, UDQS, UDM DCIOU.5 pf 24 Delta Input Capacitance: Command and Address DCI.5 pf 29 Delta Input Capacitance: CK, CK# DCI2.25 pf 29 Input/Output Capacitance: DQ, LDQS, UDQS, LDM, UDM CIO 4. 5. pf Input Capacitance: Command and Address CI 2. 3. pf Input Capacitance: CK, CK# CI2 2. 3. pf Input Capacitance: CKE CI3 2. 3. pf 95aef8a6e5f 256Mbx8x6DDR4.fm Rev. C 5/3 EN 7 23 Micron Technology, Inc. All rights reserved.

Table 9: 256Mb: x8, x6 DDR 4 SDRAM Addendum Electrical Characteristics and Recommended AC Operating Conditions C T A +7 C; VDDQ = +2.6V ±.V, VDD = +2.6V ±.V Notes: 5, 4 7, 33, 46; Refer to Base 256Mb Data Sheet, page 663 for all notes. AC CHARACTERISTICS 5B PARAMETER SYMBOL MIN MAX UNITS NOTES Access window of DQs from CK/CK# t AC.7 +.7 ns CK highlevel width t CH.45.55 3 CK lowlevel width t CL.45.55 3 Clock cycle time CL=3 5 7.5 ns 45, 52 CL=2.5 6 3 ns 42,52 CL=2 7.5 3 ns 42, 52 DQ and DM input hold time relative to DQS t DH.4 ns 26, 3 DQ and DM input setup time relative to DQS t DS.4 ns 26, 3 DQ and DM input pulse width (for each input) t DIPW.75 ns 3 Access window of DQS from CK/CK# t DQSCK.6 +.6 ns DQS input high pulse width t DQSH.35 DQS input low pulse width t DQSL.35 DQSDQ skew, DQS to last DQ valid, per group, per access t DQSQ.4 ns 25, 26 Write command to first DQS latching transition t DQSS.72.28 DQS falling edge to CK rising setup time t DSS.2 DQS falling edge from CK rising hold time t DSH.2 Half clock period t HP t CH, t CL ns 34 Dataout highimpedance window from CK/CK# t HZ +.7 ns 8,42 Dataout lowimpedance window from CK/CK# t LZ.7 ns 8,43 Address and control input hold time (slew rate = V/ns) t IH F.6 ns Address and control input setup time (slew rate = V/ns) t IS F.6 ns Address and control input hold time (slew rate =.5V/ns) t IH S.6 ns Address and control input setup time (slew rate =.5V/ns) t IS S.6 ns Address and Control input pulse width (for each input) t IPW 2.2 ns LOAD MODE REGISTER command cycle time t MRD ns DQDQS hold, DQS to first DQ to go nonvalid, per access t QH t HP ns 25, 26 t QHS Data Hold Skew Factor t QHS.5 ns ACTIVE to READ with Auto precharge command t RAP 5 ns ACTIVE to PRECHARGE command t RAS 4 7, ns 35 ACTIVE to ACTIVE/AUTO REFRESH command period t RC 55 ns AUTO REFRESH command period t RFC 7 ns 5 ACTIVE to READ or WRITE delay t RCD 5 ns PRECHARGE command period t RP 5 ns DQS read preamble t RPRE.9. 42 DQS read postamble t RPST.4.6 ACTIVE bank a to ACTIVE bank b command t RRD ns DQS write preamble t WPRE.25 DQS write preamble setup time t WPRES ns 2, 2 DQS write postamble t WPST.4.6 9 Write recovery time t WR 5 ns Internal WRITE to READ command delay t WTR 2 Data valid output window (DVW) N/A t QH t DQSQ ns 25 REFRESH to REFRESH command interval t REFC 7.3 µs 23 Average periodic refresh interval t REFI 7.8 µs 23 Terminating voltage delay to VDD t VTD ns Exit SELF REFRESH to nonread command t XSNR 7 ns Exit SELF REFRESH to READ command t XSRD 2 95aef8a6e5f 256Mbx8x6DDR4.fm Rev. C 5/3 EN 8 23 Micron Technology, Inc. All rights reserved.

Table : IDD Specifications and Conditions C T A +7 C; VDDQ = +2.6V ±.V, VDD = +2.6V ±.V Notes: 5, 4 7, 33, 46, 53; Refer to Base 256Mb Data Sheet, page 663 for all notes. 256Mb: x8, x6 DDR 4 SDRAM Addendum PARAMETER/CONDITION SYMBOL 5B (X8) 5B (X6) UNITS NOTES OPERATING CURRENT: One bank; ActivePrecharge; IDD 35 35 ma 22, 48 t RC = t RC (MIN); = (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; ActiveReadPrecharge; IDD 7 85 ma 22, 48 Burst = 4; t RC = t RC (MIN); = (MIN); IOUT = ma; Address and control inputs changing once per clock cycle PRECHARGE POWERDOWN STANDBY CURRENT: All banks idle; Powerdown IDD2P 4 4 ma 23, 32, 5 mode; = (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle; IDD2F 6 6 ma 5 = (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWERDOWN STANDBY CURRENT: One bank active; IDD3P 4 4 ma 23, 32, 5 Powerdown mode; = (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; IDD3N 7 7 ma 22 One bank active; t RC = t RAS (MAX); = (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; IDD4R 2 26 ma 22, 48 One bank active; Address and control inputs changing once per clock cycle; CK = (MIN); IOUT = ma OPERATING CURRENT: Burst = 2; Writes; Continuous burst; IDD4W 85 25 ma 22 One bank active; Address and control inputs changing once per clock cycle; = (MIN); DQ, DM, and DQS inputs changing twice per clock cycle AUTO REFRESH BURST CURRENT: t RC = t RFC(MIN) IDD5 26 26 ma 5 t RFC = 7.8us, IDD5A 6 6 ma 27, 5 SELF REFRESH CURRENT: CKE.2V Standard IDD6 4 4 ma Low Power (L) IDD6A 2 2 ma OPERATING CURRENT: Four bank interleaving READs (Burst = 4) with auto precharge, t RC = minimum trc allowed; CK = (MIN); Address and control inputs change only during Active READ, or WRITE commands IDD7 47 5 ma 22, 49 MAX 8 S. Federal Way, P.O. Box 6, Boise, ID 83776, Tel: 2836839 Email: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 89324992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 95aef8a6e5f 256Mbx8x6DDR4.fm Rev. C 5/3 EN 9 23 Micron Technology, Inc. All rights reserved.