DDR SDRAM MT46V256M4 64 Meg x 4 x 4 Banks MT46V128M8 32 Meg x 8 x 4 Banks MT46V64M16 16 Meg x 16 x 4 Banks

Transcription

1 Features DDR SDRAM MT46V256M4 64 Meg x 4 x 4 Banks MT46V28M8 32 Meg x 8 x 4 Banks MT46V64M6 6 Meg x 6 x 4 Banks Features VDD = 2.5V ±.2V, VD = 2.5V ±.2V VDD = 2.6V ±.V, VD = 2.6V ±.V DDR4 Bidirectional data strobe transmitted/ received with data, that is, source-synchronous data capture x6 has two one per byte Internal, pipelined double-data-rate DDR architecture; two data accesses per clock cycle Differential clock inputs and # Commands entered on each positive edge edge-aligned with data for READs; centeraligned with data for WRITEs DLL to align and transitions with Four internal banks for concurrent operation Data mask DM for masking write data x6 has two one per byte Programmable burst lengths BL: 2, 4, or 8 Auto refresh and self refresh modes Longer-lead TSOP for improved reliability OCPL 2.5V I/O SSTL_2 compatible Concurrent auto precharge option is supported t RAS lockout supported t RAP = t RCD Options Notes:. Not recommended for new designs. 2. See Table 3 on page 2 for module compatibility. Marking Configuration 256 Meg x 4 64 Meg x 4 x 4 banks 256M4 28 Meg x 8 32 Meg x 8 x 4 banks 28M8 64 Meg x 6 6 Meg x 6 x 4 banks 64M6 Plastic package OCPL 66-pin TSOP TG 4-mil width,.65mm pin pitch 66-pin TSOP Pb-free P 4-mil width,.65mm pin pitch Timing cycle time CL = 3 DDR4B -5B CL = 2.5 DDR333B 2-6T CL = 2.5 DDR266B 2-75 Temperature rating Commercial C to +7 C None Industrial 4 C to +85 C IT Revision :A Table : Key Timing Parameters CL = CAS READ latency; data-out window is MIN clock rate with 5 percent duty cycle at CL = 2.5 Speed Grade Clock Rate MHz CL = 2 CL = 2.5 CL = 3 Data-Out Window Access Window Skew -5B ns ±.7ns.4ns -6T n/a 2.ns ±.7ns.45ns n/a 2.5ns ±.75ns.5ns PDF: 95aef8a2f898/Source: 95aef82a95a3a Gb_DDR_x4x8x6_D.fm - Gb DDR: Rev. J, Core DDR: Rev. E 7/ EN 23 Micron Technology, Inc. All rights reserved.

2 Features Table 2: ing Parameter 256 Meg x 4 28 Meg x 8 64 Meg x 6 Configuration 64 Meg x 4 x 4 banks 32 Meg x 8 x 4 banks 6 Meg x 6 x 4 banks Refresh count 8K 8K 8K Row address 6K A A3 6K A A3 6K A A3 Bank address 4 BA, BA 4 BA, BA 4 BA, BA Column address 4K A A9, A, A2 2K A A9, A K A A9 Table 3: Speed Grade Compatibility Marking PC PC PC PC PC PC B Yes Yes Yes Yes Yes Yes -6T Yes Yes Yes Yes Yes -75 Yes Yes -5B -6T Figure : Gb DDR SDRAM Part Numbers Example Part Number: MT46V64M6P-6T:A - MT46V Configuration Package Speed Sp. Op. Temp. : Revision Revision :A x4, x8, x6 Configuration 256 Meg x 4 28 Meg x 8 64 Meg x 6 256M4 28M8 64M6 IT Operating Temperature Commercial Industrial Package 4-mil TSOP 4-mil TSOP Pb-free TG P Special Options Standard -5B -6T -75 Speed Grade t = 5ns, CL = 3 t = 6ns, CL = 2.5 t = 7.5ns, CL = 2.5 PDF: 95aef8a2f898/Source: 95aef82a95a3a Gb_DDR_x4x8x6_D.fm - Gb DDR: Rev. J, Core DDR: Rev. E 7/ EN 2 23 Micron Technology, Inc. All rights reserved.

3 Table of Contents Gb: x4, x8, x6 DDR SDRAM Table of Contents State Diagram Functional Description General Notes Functional Block Diagrams Pin Assignments and Descriptions Package Dimensions Electrical Specifications I DD Electrical Specifications DC and AC Notes Commands DESELECT NO OPERATION NOP LOAD MODE REGISTER LMR ACTIVE ACT READ WRITE PRECHARGE PRE BURST TERMINATE BST AUTO REFRESH AR SELF REFRESH Operations INITIALIZATION REGISTER DEFINITION ACTIVE READ WRITE PRECHARGE AUTO REFRESH SELF REFRESH Power-down E Not Active PDF: 95aef8a2f898/Source: 95aef82a95a3a Gb_DDRTOC.fm - Gb DDR: Rev. J, Core DDR: Rev. E 7/ EN 3 23 Micron Technology, Inc. All rights reserved.

4 State Diagram State Diagram Figure 2: Simplified State Diagram Power applied Power on PRE Precharge all banks LMR REFS Self refresh MR EMR LMR Idle all banks precharged REFSX REFA EL Auto refresh EH Active powerdown E HIGH ACT Precharge powerdown E LOW Row active Burst stop WRITE Write WRITE WRITE A READ A READ READ BST Read READ WRITE A READ A READ A Write A PRE PRE PRE Read A PRE Precharge PREALL Automatic sequence Command sequence ACT = ACTIVE BST = BURST TERMINATE EH = Exit power-down EL = Enter power-down EMR = Extended mode register LMR = LOAD MODE REGISTER MR = Mode register PRE = PRECHARGE PREALL = PRECHARGE all banks READ A = READ with auto precharge REFA = AUTO REFRESH REFS = Enter self refresh REFSX = Exit self refresh WRITE A = WRITE with auto precharge Note: This diagram represents operations within a single bank only and does not capture concurrent operations in other banks. DDR_x4x8x6_Core.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 4 2 Micron Technology, Inc. All rights reserved.

5 Functional Description Gb: x4, x8, x6 DDR SDRAM Functional Description The DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins. A bidirectional data strobe is transmitted externally, along with data, for use in data capture at the receiver. is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. is edge-aligned with data for READs and center-aligned with data for WRITEs. The x6 offering has two data strobes, one for the lower byte and one for the upper byte. The DDR SDRAM operates from a differential clock and #; the crossing of going HIGH and # going LOW will be referred to as the positive edge of. Commands address and control signals are registered at every positive edge of. Input data is registered on both edges of, and output data is referenced to both edges of, as well as to both edges of. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which may then be followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC standard for SSTL_2. All full-drive option outputs are SSTL_2, Class II compatible. General Notes The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation. Throughout the data sheet, the various figures and text refer to s as. The term is to be interpreted as any and all collectively, unless specifically stated otherwise. Additionally, the x6 is divided into two bytes, the lower byte and upper byte. For the lower byte [7:] DM refers to LDM and refers to L. For the upper byte [5:8] DM refers to UDM and refers to U. Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. Any specific requirement takes precedence over a general statement. DDR_x4x8x6_Core.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 5 2 Micron Technology, Inc. All rights reserved.

6 Functional Block Diagrams Gb: x4, x8, x6 DDR SDRAM Functional Block Diagrams The Gb DDR SDRAM is a high-speed CMOS, dynamic random access memory containing,73,74,824 bits. It is internally configured as a 4-bank DRAM. Figure 3: 256 Meg x 4 Functional Block Diagram E # CS# WE# CAS# RAS# Command decode Control logic Bank 3 Bank 2 Bank Mode registers 6 Refresh counter 4 3 Rowaddress MUX 4 Bank rowaddress 6,384 latch and decoder Bank memory array 6,384 x 2,48 x 8 4 Data DLL Sense amplifiers 8 READ latch 4 MUX 4 DRVRS A A3, BA, BA 6 register Bank control logic Columnaddress counter/ latch I/O gating DM mask logic 248 Column decoder 6, Column Mask WRITE FIFO 2 and 4 drivers 8 4 out in Data Column generator Input registers RCVRS 3 DM PDF: 95aef8a2f898/Source: 95aef82a95a3a Gb_DDR_x4x8x6_D2.fm - Gb DDR: Rev. J, Core DDR: Rev. E 7/ EN 6 23 Micron Technology, Inc. All rights reserved.

7 Functional Block Diagrams Figure 4: 28 Meg x 8 Functional Block Diagram E # CS# WE# CAS# RAS# Command decode Control logic Bank 3 Bank 2 Bank Mode registers 6 Refresh counter 4 3 Rowaddress MUX 4 Bank rowaddress 6,384 latch & decoder Bank memory array 6,384 x,24 x 6 8 Data DLL SENSE AMPLIFIERS 6 READ latch 8 MUX 8 DRVRS 6,384 generator A A3, BA, BA 6 register 2 2 Bank control logic I/O gating DM mask logic 24 Column decoder 6 6 Column Mask WRITE FIFO 2 and drivers 6 CLK CLK out in Data 8 8 Input registers RCVRS 7 DM Columnaddress counter/ latch Column Figure 5: 64 Meg x 6 Functional Block Diagram E # CS# WE# CAS# RAS# Command decode Control logic Bank 3 Bank Bank 2 Mode registers 6 Refresh counter 4 3 Rowaddress MUX 4 Bank rowaddress 6,384 latch & decoder Bank memory array 6,384 x 52 x 32 6 Data DLL SENSE AMPLIFIERS 32 READ latch 6 MUX 6 DRVRS A A3, BA, BA 6 register 2 2 Bank control logic 6,384 I/O gating DM mask logic 52 Column decoder Column Mask WRITE FIFO 4 and drivers 32 out in Data generator Input registers RCVRS 32 5 L/H LDM, UDM Columnaddress counter/ latch 9 Column PDF: 95aef8a2f898/Source: 95aef82a95a3a Gb_DDR_x4x8x6_D2.fm - Gb DDR: Rev. J, Core DDR: Rev. E 7/ EN 7 23 Micron Technology, Inc. All rights reserved.

8 Pin Assignments and Descriptions Pin Assignments and Descriptions Figure 6: 66-pin TSOP Pin Assignments Top View x4 x8 x6 x6 x8 x4 VDD VD NC VSSQ NC 2 VD NC 3 VssQ NC NC VD NC A3 VDD DNU NC WE# CAS# RAS# CS# NC BA BA VDD VD 2 VSSQ 3 4 VD 5 6 VSSQ 7 NC VD L A3 VDD DNU LDM WE# CAS# RAS# CS# NC BA BA VSS 5 VSSQ 4 3 VD 2 VSSQ 9 VD 8 NC VSSQ U DNU VREF VSS UDM # E NC A2 A A9 VSS 7 VSSQ NC 6 VD NC 5 VSSQ NC 4 VD NC NC VSSQ DNU VREF VSS DM # E NC A2 A A9 A/AP A/AP A8 A8 A A A2 A3 VDD A A A2 A3 VDD A7 A6 A5 A4 VSS A7 A6 A5 A4 VSS VSS VDD NF VD NC VSSQ NC NF VD NC VSSQ NC NC VD NC A3 VDD DNU NC WE# CAS# RAS# CS# NC BA BA A/AP A A A2 A3 VDD VSS NF VSSQ NC 3 VD NC NF VSSQ NC 2 VD NC NC VSSQ DNU VREF VSS DM # E NC A2 A A9 A8 A7 A6 A5 A4 PDF: 95aef8a2f898/Source: 95aef82a95a3a Gb_DDR_x4x8x6_D2.fm - Gb DDR: Rev. J, Core DDR: Rev. E 7/ EN 8 23 Micron Technology, Inc. All rights reserved.

9 Pin Assignments and Descriptions Table 4: Pin Descriptions TSOP Numbers Symbol Type Description 29, 3, 3, 32, 35, 36, 37, 38, 39, 4, 28, 4, 42, 7 A, A, A2, A3, A4, A5, A6, A7, A8, A9, A, A, A2, A3 Input inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit A for READ/WRITE commands, to select one location out of the memory array in the respective bank. A sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank A LOW, bank selected by BA, BA or all banks A HIGH. The address inputs also provide the op-code during a LOAD MODE REGISTER LMR command. 26, 27 BA, BA Input Bank address inputs: BA and BA define the bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA and BA also define which mode register mode register or extended mode register is loaded during the LOAD MODE REGISTER command. 45, 46, # Input Clock: and # are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of and the negative edge of #. Output data and is referenced to the crossings of and #. 44 E Input Clock enable: E HIGH activates and E LOW deactivates the internal clock, input buffers, and output drivers. Taking E LOW provides PRECHARGE power-down and SELF REFRESH operations all banks idle or ACTIVE power-down row active in any bank. E is synchronous for power-down entry and exit and for self refresh entry. E is asynchronous for self refresh exit and for disabling the outputs. E must be maintained HIGH throughout read and write accesses. Input buffers excluding, #, and E are disabled during power-down. Input buffers excluding E are disabled during SELF REFRESH. E is an SSTL_2 input but will detect an LVCMOS LOW level after V DD is applied and until E is first brought HIGH, after which it becomes a SSTL_2 input only. 24 CS# Input Chip select: CS# enables registered LOW and disables registered HIGH the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. 47 2, 47 23, 22, 2 2, 4, 5, 7, 8,,, 3, 54, 56, 57, 59, 6, 62, 63, 65 2, 5, 8,, 56, 59, 62, 65 DM LDM, UDM RAS#, CAS#, WE# Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a write access. DM is sampled on both edges of. Although DM pins are input-only, the DM loading is designed to match that of and pins. For the x6, LDM is DM for [7;] and UDM is DM for [5:8]. Pin 2 is a NC on x4 and x8. Input Command inputs: RAS#, CAS#, and WE# along with CS# define the command being entered. I/O Data input/output: Data bus for x6. [3:] [7:4] [:8] [5:2] [3:] I/O Data input/output: Data bus for x8. [7:4] 5,, 56, 62 [3:] I/O Data input/output: Data bus for x4. 5 I/O 6 L 5 U Data strobe: Output with read data, input with write data. is edgealigned with read data, center-aligned with write data. It is used to capture data. For the x6, L is for [7:] and U is for [5:8]. Pin 6 is NC on x4 and x8., 8, 33 V DD Supply Power supply. 3, 9, 5, 55, 6 V D Supply power supply: Isolated on the die for improved noise immunity. PDF: 95aef8a2f898/Source: 95aef82a95a3a Gb_DDR_x4x8x6_D2.fm - Gb DDR: Rev. J, Core DDR: Rev. E 7/ EN 9 23 Micron Technology, Inc. All rights reserved.

10 Pin Assignments and Descriptions Table 4: Pin Descriptions continued TSOP Numbers Symbol Type Description 34, 48, 66 V SS Supply Ground. 6, 2, 52, 58, 64 V SSQ Supply ground: Isolated on the die for improved noise immunity. 49 V REF Supply SSTL_2 reference voltage. 4, 25, 43, 53 NC No connect for x6: These pins should be left unconnected. 4, 7,, 3, 4, NC No connect for x8: These pins should be left unconnected. 6, 2, 25, 43, 53, 54, 57, 6, 63 4, 7,, 3, 4, NC No connect for x4: These pins should be left unconnected. 6, 2, 25, 43, 53, 54, 57, 6, 63 2, 8, 59, 65 NF No function for x4: These pins should be left unconnected. 9, 5 DNU Do not use: Must float to minimize noise on V REF. PDF: 95aef8a2f898/Source: 95aef82a95a3a Gb_DDR_x4x8x6_D2.fm - Gb DDR: Rev. J, Core DDR: Rev. E 7/ EN 23 Micron Technology, Inc. All rights reserved.

11 Package Dimensions Package Dimensions Figure 7: 66-Pin Plastic TSOP 4 mil ±.8 See detail A.65 TYP.7. 2X.32 ±.75 TYP.76 ±.2.6 ±.8 Pin # ID Gage plane.25.2 MAX TYP.5 ±. Detail A Notes:. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is.25mm per side. PDF: 95aef8a2f898/Source: 95aef82a95a3a Gb_DDR_x4x8x6_D2.fm - Gb DDR: Rev. J, Core DDR: Rev. E 7/ EN 23 Micron Technology, Inc. All rights reserved.

12 Electrical Specifications I DD Electrical Specifications I DD Table 5: I DD Specifications and Conditions x4, x8 Notes 5,, 3, 5, and 47 apply to the entire table; Notes appear on page 26; See also Table 7 on page 4; V D = 2.6V ±.V, V DD = 2.6V ±.V -5B; V D = 2.5V ±.2V, V DD = 2.5V ±.2V -6T, -75; C T A 7 C Parameter/Condition Symbol -5B -6T -75 Units Notes Operating one-bank active-precharge current: I DD ma 23, 48 t RC = t RC MIN; t = t MIN;, DM, and inputs changing once per clock cycle; and control inputs changing once every two clock cycles Operating one-bank active-read-precharge current: I DD ma 23, 48 BL = 4; t RC = t RC MIN; t = t MIN; I OUT =ma; and control inputs changing once per clock cycle Precharge power-down standby current: All banks I DD2P 3 ma 24, 33 idle; Power-down mode; t = t MIN; E = LOW Idle standby current: CS# = HIGH; All banks are idle; I DD2F ma 5 t = t MIN; E = HIGH; and other control inputs changing once per clock cycle. V IN =V REF for,, and DM Active power-down standby current: One bank active; I DD3P ma 24, 33 Power-down mode; t = t MIN; E = LOW Active standby current: CS# = HIGH; E = HIGH; One I DD3N ma 23 bank active; t RC = t RAS MAX; t = t MIN;, DM, and inputs changing twice per clock cycle; and other control inputs changing once per clock cycle Operating burst read current: BL = 2; Continuous burst I DD4R ma 23, 48 reads; One bank active; and control inputs changing once per clock cycle; t = t MIN; I OUT =ma Operating burst write current: BL = 2; Continuous I DD4W ma 23 burst writes; One bank active; and control inputs changing once per clock cycle; t = t MIN;, DM, and inputs changing twice per clock cycle Auto refresh burst current: t REFC = t RFC MIN I DD ma 5 t REFC = 7.8µs I DD5A 3 ma 28, 5 Self refresh current: E.2V Standard I DD6 9 9 ma 2 Operating bank interleave read current: Four bank interleaving READs BL = 4 with auto precharge; RC = MIN; t = t MIN; and control inputs change only during ACTIVE, READ, or WRITE commands I DD ma 23, 49 PDF: 95aef8a2f898/Source: 95aef82a95a3a Gb_DDR_x4x8x6_D2.fm - Gb DDR: Rev. J, Core DDR: Rev. E 7/ EN 2 23 Micron Technology, Inc. All rights reserved.

13 Electrical Specifications I DD Table 6: I DD Specifications and Conditions x6 Notes 5,, 3, 5, and 47 apply to the entire table; Notes appear on page 26; See also Table 7 on page 4; V D = 2.6V ±.V, V DD = 2.6V ±.V -5B; V D = 2.5V ±.2V, V DD = 2.5V ±.2V -6T, -75; C T A 7 C Parameter/Condition Symbol -5B -6T -75 Units Notes Operating one-bank active-precharge current: I DD ma 23, 48 t RC = t RC MIN; t = t MIN;, DM and inputs changing once per clock cycle; and control inputs changing once every two clock cycles Operating one-bank active-read-precharge current: I DD ma 23, 48 BL = 4; t RC = t RC MIN; t = t MIN; I OUT =ma; and control inputs changing once per clock cycle Precharge power-down standby current: All banks I DD2P 5 ma 24, 33 idle; Power-down mode; t = t MIN; E = LOW Idle standby current: CS# = HIGH; All banks are idle; I DD2F ma 5 t = t MIN; E = HIGH; and other control inputs changing once per clock cycle. V IN =V REF for,, and DM Active power-down standby current: One bank I DD3P ma 24, 33 active; Power-down mode; t = t MIN; E = LOW Active standby current: CS# = HIGH; E = HIGH; One I DD3N ma 23 bank active; t RC = t RAS MAX; t = t MIN;, DM, and inputs changing twice per clock cycle; and other control inputs changing once per clock cycle Operating burst read current: BL = 2; Continuous burst I DD4R ma 23, 48 reads; One bank active; and control inputs changing once per clock cycle; t = t MIN; I OUT =ma Operating burst write current: BL = 2; Continuous I DD4W ma 23 burst writes; One bank active; and control inputs changing once per clock cycle; t = t MIN;, DM, and inputs changing twice per clock cycle Auto refresh burst current: t REFC = t RFC MIN I DD ma 5 t REFC = 7.8µs I DD5A 5 ma 28, 5 Self refresh current: E.2V Standard I DD6 9 9 ma 2 Operating bank interleave read current: Four bank interleaving READs BL = 4 with auto precharge; RC = MIN; t = t MIN; and control inputs change only during ACTIVE, READ, or WRITE commands I DD ma 23, 49 PDF: 95aef8a2f898/Source: 95aef82a95a3a Gb_DDR_x4x8x6_D2.fm - Gb DDR: Rev. J, Core DDR: Rev. E 7/ EN 3 23 Micron Technology, Inc. All rights reserved.

14 Electrical Specifications I DD Table 7: I DD Test Cycle Times Values reflect number of clock cycles for each test I DD Test Speed Grade Clock Cycle Time t RRD t RCD I DD ns n/a n/a n/a n/a n/a -6T 6.ns n/a n/a 7 3 n/a n/a n/a -5B 5.ns n/a n/a 8 3 n/a n/a n/a I DD ns n/a n/a n/a n/a 2.5-6T 6.ns n/a n/a 7 3 n/a n/a 2.5-5B 5.ns n/a n/a 8 3 n/a n/a 3 I DD4R ns n/a n/a n/a n/a n/a n/a n/a 2.5-6T 6.ns n/a n/a n/a n/a n/a n/a n/a 2.5-5B 5.ns n/a n/a n/a n/a n/a n/a n/a 3 I DD4W ns n/a n/a n/a n/a n/a n/a n/a n/a -6T 6.ns n/a n/a n/a n/a n/a n/a n/a n/a -5B 5.ns n/a n/a n/a n/a n/a n/a n/a n/a I DD ns n/a n/a n/a n/a n/a 6 6 n/a -6T 6.ns n/a n/a n/a n/a n/a 2 2 n/a -5B 5.ns n/a n/a n/a n/a n/a n/a I DD5A ns n/a n/a n/a n/a n/a 6,26 n/a -6T 6.ns n/a n/a n/a n/a n/a 2,82 n/a -5B 5.ns n/a n/a n/a n/a n/a 24,44 n/a I DD ns 2 3 n/a 3 n/a n/a 2.5-6T 6.ns 2 3 n/a 3 n/a n/a 2.5-5B 5.ns 2 3 n/a 3 n/a n/a 3 t RAS t RP t RC t RFC t REFI CL PDF: 95aef8a2f898/Source: 95aef82a95a3a Gb_DDR_x4x8x6_D2.fm - Gb DDR: Rev. J, Core DDR: Rev. E 7/ EN 4 23 Micron Technology, Inc. All rights reserved.

15 Electrical Specifications DC and AC Gb: x4, x8, x6 DDR SDRAM Electrical Specifications DC and AC Stresses greater than those listed in Table 8 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 8: Absolute Maximum Ratings Parameter Min Max Units V DD supply voltage relative to V SS V 3.6V V V D supply voltage relative to V SS V 3.6V V V REF and inputs voltage relative to V SS V 3.6V V I/O pins voltage relative to V SS.5V V D +.5V V Storage temperature plastic 55 5 C Short circuit output current 5 ma Table 9: DC Electrical Characteristics and Operating Conditions -5B Notes: 5 and 7 apply to the entire table; Notes appear on page 26; V D = 2.6V ±.V, V DD = 2.6V ±.V Parameter/Condition Symbol Min Max Units Notes Supply voltage V DD V 37, 42 I/O supply voltage V D V 37, 42, 45 I/O reference voltage V REF.49 V D.5 V D V 7, 45 I/O termination voltage system V TT V REF -.4 V REF +.4 V 8, 45 Input high logic voltage V IHDC V REF +.5 V DD +.3 V 29 Input low logic voltage V ILDC.3 V REF -.5 V 29 Input leakage current: I I 2 2 µa Any input V V IN V DD, V REF pin V V IN.35V All other pins not under test = V Output leakage current: I OZ 5 5 µa are disabled; V V OUT V D Full-drive option output High current V OUT = I OH 6.8 ma 38, 4 levels x4, x8, x6: V D -.373V, minimum V REF, minimum V TT Low current V OUT =.373V, maximum V REF, maximum V TT I OL 6.8 ma Reduced-drive option output levels: Ambient operating temperatures High current V OUT = I OHR 9 ma 39, 4 V D -.373V, minimum V REF, minimum V TT Low current V OUT =.373V, maximum V REF, maximum V TT I OLR 9 ma Commercial T A 7 C Industrial T A 4 85 C DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 5 2 Micron Technology, Inc. All rights reserved.

16 Electrical Specifications DC and AC Table : DC Electrical Characteristics and Operating Conditions -6, -6T, -75E, -75Z, -75 Notes: 5 and 7 apply to the entire table; Notes appear on page 26; V D = 2.5V ±.2V, V DD = 2.5V ±.2V Parameter/Condition Symbol Min Max Units Notes Supply voltage V DD V 37, 42 I/O supply voltage V D V 37, 42, 45 I/O reference voltage V REF.49 V D.5 V D V 7, 45 I/O termination voltage system V TT V REF -.4 V REF +.4 V 8, 45 Input high logic voltage V IHDC V REF +.5 V DD +.3 V 29 Input low logic voltage V ILDC.3 V REF -.5 V 29 Input leakage current: I I 2 2 µa Any input V V IN V DD, V REF pin V V IN.35V All other pins not under test = V Output leakage current: I OZ 5 5 µa are disabled; V V OUT V D Full-drive option output High current V OUT = I OH 6.8 ma 38, 4 levels x4, x8, x6: V D -.373V, minimum V REF, minimum V TT Low current V OUT =.373V, maximum V REF, maximum V TT I OL 6.8 ma Reduced-drive option output levels: Ambient operating temperatures High current V OUT = I OHR 9 ma 39, 4 V D -.373V, minimum V REF, minimum V TT Low current V OUT =.373V, maximum V REF, maximum V TT I OLR 9 ma Commercial T A 7 C Industrial T A 4 85 C Table : AC Input Operating Conditions Notes: 5 and 7 apply to the entire table; Notes appear on page 26; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V V D = 2.6V ±.V, V DD = 2.6V ±.V for -5B Parameter/Condition Symbol Min Max Units Notes Input high logic voltage V IHAC V REF +.3 V 5, 29, 4 Input low logic voltage V ILAC V REF -.3 V 5, 29, 4 I/O reference voltage V REFAC.49 V D.5 V D V 7 DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 6 2 Micron Technology, Inc. All rights reserved.

17 Electrical Specifications DC and AC Figure 8: Input Voltage Waveform VD 2.3V MIN VOH MIN.67V for SSTL_2 termination System noise margin power/ground, crosstalk, signal integrity attenuation.56v VIHAC.4V VIHDC.3V.275V.25V.225V.2V VREF + AC noise VREF + DC error VREF - DC error VREF - AC noise.v VILDC.94V VINAC - provides margin between VOL MAX and VILAC VOL MAX.83V 2 for SSTL_2 termination Receiver VILAC Transmitter Notes: VssQ. V OH,min with test load is.927v. 2. V OL,max with test load is.373v. 3. Numbers in diagram reflect nominal values utilizing circuit below for all devices other than -5B. VTT 25Ω 25Ω Reference point DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 7 2 Micron Technology, Inc. All rights reserved.

18 Electrical Specifications DC and AC Table 2: Clock Input Operating Conditions Notes: 5, 6, 7, and 3 apply to the entire table; Notes appear on page 26; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V V D = 2.6V ±.V, V DD = 2.6V ±.V for -5B Parameter/Condition Symbol Min Max Units Notes Clock input mid-point voltage: and # V MPDC.5.35 V 7, Clock input voltage level: and # V INDC.3 V D +.3 V 7 Clock input differential voltage: and # V IDDC.36 V D +.6 V 7, 9 Clock input differential voltage: and # V IDAC.7 V D +.6 V 9 Clock input crossing point voltage: and # V IXAC.5 V D V D +.2 V Figure 9: SSTL_2 Clock Input 2.8V Maximum clock level #.45V.25V.5V X X VMPDC 2 VIXAC 3 VIDDC 4 VIDAC 5.3V Minimum clock level Notes:. or # may not be more positive than V D +.3V or more negative than V SS -.3V. 2. This provides a minimum of.5v to a maximum of.35v and is always half of V D. 3. and # must cross in this region. 4. and # must meet at least V IDDC,min when static and is centered around V MPDC. 5. and # must have a minimum 7mV peak-to-peak swing. 6. For AC operation, all DC clock requirements must also be satisfied. 7. Numbers in diagram reflect nominal values for all devices other than -5B. DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 8 2 Micron Technology, Inc. All rights reserved.

19 Electrical Specifications DC and AC Table 3: Capacitance x4, x8 TSOP Note: 4 applies to the entire table; Notes appear on page 26 Parameter Symbol Min Max Units Notes Delta input/output capacitance: [3:] x4, [7:] x8 DC IO.5 pf 25 Delta input capacitance: Command and address DC I.5 pf 3 Delta input capacitance:, # DC I2.25 pf 3 Input/output capacitance:,, DM C IO pf Input capacitance: Command and address C I pf Input capacitance:, # C I pf Input capacitance: E C I pf Table 4: Capacitance x6 TSOP Note: 4 applies to the entire table; Notes appear on page 26 Parameter Symbol Min Max Units Notes Delta input/output capacitance: [7:], L, LDM DC IOL.5 pf 25 Delta input/output capacitance: [5:8], U, UDM DC IOU.5 pf 25 Delta input capacitance: Command and address DC I.5 pf 3 Delta input capacitance:, # DC I2.25 pf 3 Input/output capacitance:, L, U, LDM, UDM C IO pf Input capacitance: Command and address C I pf Input capacitance:, # C I pf Input capacitance: E C I pf DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 9 2 Micron Technology, Inc. All rights reserved.

20 Electrical Specifications DC and AC Table 5: Electrical Characteristics and Recommended AC Operating Conditions -5B Notes 6, 6 8, and 34 apply to the entire table; Notes appear on page 26; C T A 7 C; V D = 2.6V ±.V, V DD = 2.6V ±.V AC Characteristics -5B Parameter Symbol Min Max Units Notes Access window of from /# t AC.7.7 ns high-level width t CH t 3 Clock cycle time CL = 3 t ns 52 CL = 2.5 t ns 46, 52 CL = 2 t ns 46, 52 low-level width t CL t 3 and DM input hold time relative to t DH.4 ns 27, 32 and DM input pulse width for each input t PW.75 ns 32 Access window of from /# t.6.6 ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.4 ns 26, 27 WRITE command to first latching transition t S t and DM input setup time relative to t DS.4 ns 27, 32 falling edge from rising hold time t DSH.2 t falling edge to rising setup time t DSS.2 t Half-clock period t HP t CH, t CL ns 35 Data-out High-Z window from /# t HZ.7 ns 9, 43 and control input hold time slew rate.5 V/ns t IH F.6 ns 5 and control input pulse width for each input t IPW 2.2 ns and control input setup time slew rate.5 V/ns t IS F.6 ns 5 Data-out Low-Z window from /# t LZ.7 ns 9, 43 LOAD MODE REGISTER command cycle time t MRD ns hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.5 ns ACTIVE-to-READ with auto precharge command t RAP 5 ns ACTIVE-to-PRECHARGE command t RAS 4 7, ns 36 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 55 ns 55 ACTIVE-to-READ or WRITE delay t RCD 5 ns REFRESH-to-REFRESH command intervalgb t REFC 7.3 µs 24 AUTO REFRESH command period Gb t RFC 2 ns 5 Average periodic refresh interval t REFI 7.8 µs 24 AUTO REFRESH command period t RFC 7 ns 5 PRECHARGE command period t RP 5 ns read preamble t RPRE.9. t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD ns Terminating voltage delay to V DD t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 2, 22 write postamble t WPST.4.6 t 2 Write recovery time t WR 5 ns DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 2 2 Micron Technology, Inc. All rights reserved.

21 Electrical Specifications DC and AC Table 5: Electrical Characteristics and Recommended AC Operating Conditions -5B continued Notes 6, 6 8, and 34 apply to the entire table; Notes appear on page 26; C T A 7 C; V D = 2.6V ±.V, V DD = 2.6V ±.V AC Characteristics -5B Parameter Symbol Min Max Units Notes Internal WRITE-to-READ command delay t WTR 2 t Exit SELF REFRESH-to-non-READ Gb t XSNR 26 ns command Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window n/a t QH - t Q ns 26 DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 2 2 Micron Technology, Inc. All rights reserved.

22 Electrical Specifications DC and AC Table 6: Electrical Characteristics and Recommended AC Operating Conditions -6T Notes: 6, 6 8, and 34 apply to the entire table; Notes appear on page 26; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -6T TSOP Parameter Symbol Min Max Units Notes Access window of from /# t AC.7.7 ns high-level width t CH t 3 Clock cycle time CL = 2.5 t ns 46, 52 CL = 2 t ns 46, 52 low-level width t CL t 3 and DM input hold time relative to t DH.45 ns 27, 32 and DM input pulse width for each input t PW.75 ns 32 Access window of from /# t.6.6 ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.45 ns 26, 27 WRITE command to first latching transition t S t and DM input setup time relative to t DS.45 ns 27, 32 falling edge from rising - hold time t DSH.2 t falling edge to rising - setup time t DSS.2 t Half-clock period t HP t CH, ns 35 t CL Data-out High-Z window from /# t HZ.7 ns 9, 43 and control input hold time fast slew rate t IH F.75 ns and control input hold time slow slew rate t IH S.8 ns 5 and control input pulse width for each input t IPW 2.2 ns and control input setup time fast slew rate t IS F.75 ns and control input setup time slow slew rate t IS S.8 ns 5 Data-out Low-Z window from /# t LZ.7 ns 9, 43 LOAD MODE REGISTER command cycle time t MRD 2 ns - hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.55 ns ACTIVE-to-READ with auto precharge command t RAP 5 ns ACTIVE-to-PRECHARGE command t RAS 42 7, ns 36, 54 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 6 ns 55 ACTIVE-to-READ or WRITE delay t RCD 5 ns REFRESH-to-REFRESH command interval t REFC 7.3 µs 24 Average periodic refresh interval t REFI 7.8 µs 24 AUTO REFRESH command period Gb t RFC 2 ns 5 PRECHARGE command period t RP 5 ns read preamble t RPRE.9. t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 2 ns Terminating voltage delay to V SS t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 2, 22 write postamble t WPST.4.6 t 2 DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 22 2 Micron Technology, Inc. All rights reserved.

23 Electrical Specifications DC and AC Table 6: Electrical Characteristics and Recommended AC Operating Conditions -6T continued Notes: 6, 6 8, and 34 apply to the entire table; Notes appear on page 26; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -6T TSOP Parameter Symbol Min Max Units Notes Write recovery time t WR 5 ns Internal WRITE-to-READ command delay t WTR t Exit SELF REFRESH-to-non-READ Gb t XSNR 26 ns command Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window n/a t QH - t Q ns 26 DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 23 2 Micron Technology, Inc. All rights reserved.

24 Electrical Specifications DC and AC Table 7: Electrical Characteristics and Recommended AC Operating Conditions -75 Notes: 6, 6 8, and 34 apply to the entire table; Notes appear on page 26; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -75 Parameter Symbol Min Max Units Notes Access window of from /# t AC ns high-level width t CH t 3 Clock cycle time CL = 2.5 t ns 46 CL = 2 t 2 3 ns 46 low-level width t CL t 3 and DM input hold time relative to t DH.5 ns 27, 32 and DM input pulse width for each input t PW.75 ns 32 Access window of from /# t ns input high pulse width t H.35 t input low pulse width t L.35 t skew, to last valid, per group, per access t Q.5 ns 26, 27 WRITE command-to-first latching transition t S t and DM input setup time relative to t DS.5 ns 27, 32 falling edge from rising hold time t DSH.2 t falling edge to rising setup time t DSS.2 t Half-clock period t HP t CH, t CL ns 35 Data-out High-Z window from /# t HZ.75 ns 9, 43 and control input hold time fast slew rate t IH F.9 ns and control input hold time slow slew rate t IH S ns 5 and control input pulse width for each input t IPW 2.2 ns and control input setup time fast slew rate t IS F.9 ns and control input setup time slow slew rate t IS S ns 5 Data-out Low-Z window from /# t LZ.75 ns 9, 43 LOAD MODE REGISTER command cycle time t MRD 5 ns hold, to first to go non-valid, per access t QH t HP - t QHS ns 26, 27 Data hold skew factor t QHS.75 ns ACTIVE-to-READ with auto precharge command t RAP 2 ns ACTIVE-to-PRECHARGE command t RAS 4 2, ns 36 ACTIVE-to-ACTIVE/AUTO REFRESH command period t RC 65 ns 55 ACTIVE-to-READ or WRITE delay t RCD 2 ns REFRESH-to-REFRESH command interval t REFC 7.3 µs 24 Average periodic refresh interval t REFI 7.8 µs 24 AUTO REFRESH command period Gb t RFC 2 ns 5 PRECHARGE command period t RP 2 ns read preamble t RPRE.9. t 44 read postamble t RPST.4.6 t 44 ACTIVE bank a to ACTIVE bank b command t RRD 5 ns Terminating voltage delay to V DD t VTD ns write preamble t WPRE.25 t write preamble setup time t WPRES ns 2, 22 write postamble twpst.4.6 t 2 Write recovery time twr 5 ns DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 24 2 Micron Technology, Inc. All rights reserved.

25 Electrical Specifications DC and AC Table 7: Electrical Characteristics and Recommended AC Operating Conditions -75 continued Notes: 6, 6 8, and 34 apply to the entire table; Notes appear on page 26; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V AC Characteristics -75 Parameter Symbol Min Max Units Notes Internal WRITE-to-READ command delay t WTR t Exit SELF REFRESH-to-non-READ Gb t XSNR 27.5 ns command Exit SELF REFRESH-to-READ command t XSRD 2 t Data valid output window n/a t QH - t Q ns 26 Table 8: Input Slew Rate Derating Values for es and Commands Note: 5 applies to the entire table; Notes appear on page 26; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V Speed Slew Rate t IS t IH Units V/ns. ns V/ns.5 ns V/ns. ns Table 9: Input Slew Rate Derating Values for,, and DM Note: 32 applies to the entire table; Notes appear on page 26; C T A 7 C; V D = 2.5V ±.2V, V DD = 2.5V ±.2V Speed Slew Rate t DS t DH Units V/ns.5.5 ns V/ns ns V/ns.6.6 ns DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 25 2 Micron Technology, Inc. All rights reserved.

26 Electrical Specifications DC and AC Notes. All voltages referenced to V SS. 2. Tests for AC timing, I DD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and the device operation are guaranteed for the full voltage range specified. 3. Outputs except for I DD measurements measured with equivalent load: VTT Output VOUT 5 Reference point 3pF 4. AC timing and I DD tests may use a V IL -to-v IH swing of up to.5v in the test environment, but input timing is still referenced to V REF or to the crossing point for /#, and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is V/ns in the range between V ILAC and V IHAC. 5. The AC and DC input level specifications are as defined in the SSTL_2 standard that is, the receiver will effectively switch as a result of the signal crossing the AC input level and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level. 6. All speed grades are not offered on all densities. Refer to page for availability. 7. V REF is expected to equal V D /2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise noncommon mode on V REF may not exceed ±2% of the DC value. Thus, from V D /2, V REF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest V REF bypass capacitor. 8. V TT is not applied directly to the device. V TT is a system supply for signal termination resistors, it is expected to be set equal to V REF, and it must track variations in the DC level of V REF. 9. V ID is the magnitude of the difference between the input level on and the input level on #.. The value of V IX and V MP is expected to equal V D /2 of the transmitting device and must track variations in the DC level of the same.. I DD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle times at CL = 3 for -5B; CL = 2.5, -6T/-75 speeds with the outputs open. 2. Enables on-chip refresh and address counters. 3. I DD specifications are tested after the device is properly initialized and is averaged at the defined cycle rate. 4. This parameter is sampled. V DD = 2.5V ±.2V, V D = 2.5V ±.2V, V REF =V SS, f =MHz, T A =25 C, V OUTDC =V D /2, V OUT peak-to-peak =.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 5. For slew rates less than V/ns and greater than or equal to.5 V/ns. If the slew rate is less than.5 V/ns, timing must be derated: t IS has an additional 5ps per each mv/ns reduction in slew rate from the 5 mv/ns. t IH has ps added, that is, it remains constant. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For -5B and -6T, slew rates must be greater than or equal to.5 V/ns. DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 26 2 Micron Technology, Inc. All rights reserved.

27 Electrical Specifications DC and AC 6. The /# input reference level for timing referenced to /# is the point at which and # cross; the input reference level for signals other than /# is V REF. 7. Inputs are not recognized as valid until V REF stabilizes. Once initialized, including self refresh mode, V REF must be powered within specified range. Exception: during the period before V REF stabilizes, E <.3 V DD is recognized as LOW. 8. The output timing reference level, as measured at the timing reference point indicated in Note 3, is V TT. 9. t HZ and t LZ transitions occur in the same access time windows as data valid transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving High-Z or begins driving Low-Z. 2. The intent of the Don t Care state after completion of the postamble is the driven signal should either be HIGH, LOW, or High-Z, and that any signal transition within the input switching region must follow valid input requirements. That is, if transitions HIGH above V IHDCmin then it must not transition LOW below V IHDC prior to t H [MIN]. 2. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 22. It is recommended that be valid HIGH or LOW on or before the WRITE command. The case shown going from High-Z to logic LOW applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, could be HIGH during this time, depending on t S. 23. MIN t RC or t RFC for I DD measurements is the smallest multiple of t that meets the minimum absolute value for the respective parameter. t RAS MAX for I DD measurements is the largest multiple of t that meets the maximum absolute value for t RAS. 24. The refresh period is 64ms. This equates to an average refresh rate of 7.825µs. However, an AUTO REFRESH command must be asserted at least once every 7.3µs; burst refreshing or posting by the DRAM controller greater than 8 REFRESH cycles is not allowed. 25. The I/O capacitance per and byte/group will not differ by more than this maximum amount for any given device. 26. The data valid window is derived by achieving other specifications: t HP t /2, t Q, and t QH t QH = t HP - t QHS. The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, because functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided in Figure on page 28 for duty cycles ranging between 5/5 and 45/ Referenced to each output group: x4 = with [3:]; x8 = with [7:]; x6 = L with [7:] and U with [5:8]. 28. This limit is actually a nominal value and does not result in a fail value. E is HIGH during the REFRESH command period t RFC [MIN], else E is LOW that is, during standby. 29. To maintain a valid level, the transitioning edge of the input must: 29a. Sustain a constant slew rate from the current AC level through to the target AC level, V ILAC or V IHAC. 29b. Reach at least the target AC level. 29c. After the AC target level is reached, continue to maintain at least the target DC level, V ILDC or V IHDC. DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 27 2 Micron Technology, Inc. All rights reserved.

28 Electrical Specifications DC and AC 3. The input capacitance per pin group will not differ by more than this maximum amount for any given device. 3. and # input slew rate must be V/ns 2 V/ns if measured differentially. Figure : Derating Data Valid Window t QH t Q Data Valid Window 3.ns 2.5ns 2.ns.5ns t = 7.5ns -75E / t = 7.5ns t = 6ns t = 6ns t = 5ns ns 5/5 49/5 48/53 47/53 46/54 45/55 Clock Duty Cycle 32. and DM input slew rates must not deviate from by more than %. If the / DM/ slew rate is less than.5 V/ns, timing must be derated: 5ps must be added to t DS and t DH for each mv/ns reduction in slew rate. For -5B and -6T speed grades, the slew rate must be.5 V/ns. If the slew rate exceeds 4 V/ns, functionality is uncertain. 33. V DD must not vary more than 4% if E is not active while any bank is active. 34. The clock is allowed up to ±5ps of jitter. Each timing parameter is allowed to vary by the same amount. 35. t HP MIN is the lesser of t CL MIN and t CH MIN actually applied to the device and # inputs, collectively, during bank active. 36. READs and WRITEs with auto precharge are not allowed to be issued until t RAS MIN can be satisfied prior to the internal PRECHARGE command being issued. 37. Any positive glitch must be less than /3 of the clock cycle and not more than 4mV or 2.9V 3mV or 2.9V maximum for -5B, whichever is less. Any negative glitch must be less than /3 of the clock cycle and not exceed either 3mV or 2.2V 2.4V for -5B, whichever is more positive. The average cannot be below the 2.5V 2.6V for -5B minimum. 38. Normal output drive curves: 38a. The full driver pull-down current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure on page b. The driver pull-down current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure on page 29. DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 28 2 Micron Technology, Inc. All rights reserved.

29 Electrical Specifications DC and AC 38c. The full driver pull-up current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 2 on page d. The driver pull-up current variation within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 2 on page e. The full ratio variation of MAX to MIN pull-up and pull-down current should be between.7 and.4 for drain-to-source voltages from.v to.v at the same voltage and temperature. 38f. The full ratio variation of the nominal pull-up to pull-down current should be unity ±% for device drain-to-source voltages from.v to.v. Figure : Full Drive Pull-Down Characteristics IOUT ma VOUT V Figure 2: Full Drive Pull-Up Characteristics IOUT ma VD - VOUT V 39. Reduced output drive curves: 39a. The full driver pull-down current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 3 on page 3. 39b. The driver pull-down current variation, within nominal voltage and temperature limits, is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 3 on page 3. 39c. The full driver pull-up current variation from MIN to MAX process; temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 4. DDR_x4x8x6_Core2.fm - Gb DDR: Rev. J; Core DDR Rev. E 7/ EN 29 2 Micron Technology, Inc. All rights reserved.