Features Floating channel designed for bootstrap operation Fully operational to + V Tolerant to negative transient voltage, dv/dt immune Gate drive supply range from V to V Undervoltage lockout. V, V, and V input logic compatible Cross-conduction prevention logic Internally set deadtime High-side output in phase with input Shutdown input turns off both channels Matched propagation delay for both channels RoHS compliant Description The IRS is a high voltage, high speed power MOSFET and IGBT driver with dependent high- and lowside referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to. V Typical Connection Product Summary V OFFSET I O +/- V OUT t on/off (typ.) Deadtime (typ.) Packages Data Sheet No.PD7 HALF-BRIDGE DRIVER 8 Lead SOIC IRSS IRS(S)PbF V max. ma/7 ma V - V 8 ns/ ns ns logic. The output drivers feature a high pulse current buffer stage designed for minimum driver crossconduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration which operates from V to V. 8 Lead PDIP IRS (Refer to Lead Assignment for correct pin configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. www.irf.com
IRS(S) PbF Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Units V B High-side floating absolute voltage -. V S High-side floating supply offset voltage V B - V B +. V HO High-side floating output voltage V S -. V B +. V CC Low-side and logic fixed supply voltage -. V LO Low-side output voltage -. V CC +. V IN Logic input voltage (IN & ) -. V CC +. dv s /dt Allowable offset supply voltage transient V/ns P D Package power dissipation @ T A + C Rth JA Thermal resistance, junction to ambient (8 lead PDIP). (8 lead SOIC). (8 lead PDIP) (8 lead SOIC) T J Junction temperature T S Storage temperature - T L Lead temperature (soldering, seconds) V W C/W C Recommended Operating Conditions The input/output logic timing diagram is shown in Fig.. For proper operation the device should be used within the recommended conditions. The V S offset rating is tested with all supplies biased at a V differential. Symbol Definition Units V B High-side floating supply absolute voltage V S + V S + V S High-side floating supply offset voltage Note V HO High-side floating output voltage V S V B V CC Low-side and logic fixed supply voltage V V LO Low-side output voltage V CC V IN Logic input voltage (IN & ) V CC T A Ambient temperature - C Note : Logic operational for V S of - V to + V. Logic state held for V S of - V to -V BS. (Please refer to the Design Tip DT97- for more details). www.irf.com
IRS(S) PbF Dynamic Electrical Characteristics V BIAS (V CC, V BS ) = V, C L = pf and T A = C unless otherwise specified. Symbol Definition Units Test Conditions ton Turn-on propagation delay 8 8 V S = V toff Turn-off propagation delay V S = V tsd Shutdown propagation delay tr Turn-on rise time 7 7 tf Turn-off fall time 9 DT Deadtime, LS turn-off to HS turn-on & HS turn-on to LS turn-off MT Delay matching, HS & LS turn-on/off ns Static Electrical Characteristics V BIAS (V CC, V BS ) = V and T A = C unless otherwise specified. The V IN, V TH, and I IN parameters are referenced to COM. The V O and I O parameters are referenced to COM and are applicable to the respective output leads: HO or LO. Symbol Definition Units Test Conditions V IH Logic (HO) & Logic (LO) input voltage. V IL Logic (HO) & Logic (LO) input voltage.8 V SD,TH+ SD input positive going threshold. V SD,TH- SD input negative going threshold.8 V OH High level output voltage, V BIAS - V O.. V OL Low level output voltage, V O.. I LK Offset supply leakage current V B = V S = V I QBS Quiescent V BS supply current I QCC Quiescent V CC supply current 7 I IN+ Logic input bias current V IN = V I IN- Logic input bias current V IN = V V CCUV+ V CCUV- V CC supply undervoltage positive going threshold V CC supply undervoltage negative going threshold 8 8.9 9.8 7. 8. 9 I O+ Output high short circuit pulsed current 9 I O- Output low short circuit pulsed current 7 V µa V ma V CC = V to V I O = ma V IN = V or V V O = V PW µs V O = V PW µs www.irf.com
IRS(S) PbF Functional Block Diagram VB HV LEVEL SHIFT PULSE FILTER R S Q HO IN PULSE GEN VS DEAD TIME & SHOOT-THROUGH PREVENTION UV DETECT VCC SD LO COM Lead Definitions Symbol IN V B HO V S V CC LO COM Description Logic input for high-side and low-side gate driver outputs (HO and LO), in phase with HO Logic input for shutdown High-side floating supply High-side gate drive output High-side floating supply return Low-side and logic fixed supply Low-side gate drive output Low-side return Lead Assignments V CC V B 8 V CC V B 8 IN HO 7 IN HO 7 SD V S SD V S COM LO COM LO 8 Lead PDIP 8 Lead SOIC IRSPbF IRSSPbF www.irf.com
IRS(S) PbF Figure. Input/Output Timing Diagram Figure. Switching Time Waveform Definitions Figure. Shutdown Waveform Definitions Figure. Deadtime Waveform Definitions Figure. Delay Matching Waveform Definitions www.irf.com
IRS(S) PbF Turn-On Delay Time (ns) 8 Typ. - - 7 Figure A. Turn-On Time Turn-On Delay Time (ns) 8 8 Figure B. Turn-On Time vs. Supply Voltage Turn-On Delay Time (ns) 8 8 8 Input Voltage (V) Turn-Off Delay Time (ns) - - 7 Figure C. Turn-On Time vs. Input Voltage Figure 7A. Turn-Off Time Turn-Off Delay Time (ns) 8 Turn-Off Delay Time (ns) 8 Typ 8 8 Input Voltage (V) Figure 7B. Turn-Off Time vs. Supply Voltage Figure 7C. Turn-Off Time vs. Input Voltage www.irf.com
IRS(S) PbF Shutdown Delay Time (ns) - - 7 Shutdown Delay Time (ns) 8 Figure 8A. Shutdown Time Figure 8B. Shutdown Time vs. Voltage Turn-On Rise Time (ns) MAX - - 7 Figure 9A. Turn-On Rise Time Turn-On Rise Time (ns) ( 8 VBIAS Supply Voltage (V) Figure 9B. Turn-On Rise Time vs. Voltage Turn-Off Fall Time (ns) - - 7 Figure A. Turn-Off Fall Time Turn-Off Fall Time (ns) 8 Input Voltage (V) Figure B. Turn-Off Fall Time vs. Input Voltage www.irf.com 7
IRS(S) PbF Deadtime (ns) 8 Deadtime (ns) 8 M ax. - - 7 8 Figure A. Deadtime Figure B. Deadtime vs. Voltage 8 8 7 7 Input Voltage (V) Input Voltage (V) - - 7 8 Temperature ( o C) Min FigureA. Logic "" Input Voltage Figure B. Logic "" Input Voltage vs. Supply Voltage.. Input Voltage (V)...8 Input Voltage (V)...8 - - 7 Figure A. Logic "" (HO) & Logic (LO) & Active SD Input Voltage 8 Vcc Supply Voltage (V) Figure B. Logic "" (HO) & Logic (LO) & Active SD Input Voltage vs. Supply Voltage www.irf.com 8
IRS(S) PbF High Level Output Voltage (V)...... - - 7 Temperature ( o C) Figure A. High Level Output Voltage High Level Output Voltage (V)...... 8 Figure B. High Level Output Voltage vs. Supply Voltage Low Level Output Voltage (V)...... - - 7 Temperature ( o C) Figure A. Low Level Output Voltage Low Level Output Voltage (V)..... 8 V BIAS Supply Voltage (V) Figure B. Low Level Output Voltage vs. Supply Voltage Offset Supply Leakage Current (µa) - - 7 Offset Supply Leakage Current (µa) V B Boost Voltage (V) Figure A. Offset Supply Current Figure B. Offset Supply Current vs. Voltage www.irf.com 9
IRS(S) PbF V BS Supply Current (µa) 9 - - 7 V BS Supply Current (µa) 9 8 V BS Floating Supply Voltage (V) Figure 7A. V BS Supply Current Figure 7B. V BS Supply Current vs. Voltage 7 7 V cc Supply Current (µa) - - 7 V cc Supply Current (µa) 8 V cc Supply Voltage (V) Figure 8A. Vcc Supply Current Figure 8B. Vcc Supply Current vs. Voltage Logic Input Current (µa) - - 7 Logic Input Current (µa) 8 V cc Supply Voltage (V) Figure 9A. Logic"" Input Current Figure 9B. Logic"" Input Current vs. Voltage www.irf.com
IRS(S) PbF Logic Input Bias Current (µa) Logic "" Input Bias Current (µa) Max - - 7 Figure A. Logic "" Input Bias Current Logic "" Input Bias Current (µa) Max 8 Supply Voltage (V) Figure B. Logic "" Input Bias Current vs. Voltage Vcc UVLO Threshold +(V) 9 8 7 - - 7 Figure A. Vcc Undervoltage Threshold(+) Vcc UVLO Threshold - (V) 9 8 7 - - 7 Figure B. Vcc Undervoltage Threshold(-) Output Source Current (ma) - - 7 Figure A. Output Source Current Output Source Current (ma) 8 VBIAS Supply Voltage (V) Figure B. Output Source Current vs. Voltage www.irf.com
IRS(S) PbF Output Sink Current (ma) 8 Output Sink Current (ma) 8 - - 7 8 Figure A. Output Sink Current Figure B. Output Sink Current vs. Supply Voltage SD Input Threshold (+) (V) SD Input Threshold (+) (V) - - 7 8 Vcc Supply Voltage (V) Figure A. SD Input Positive Going Threshold (+) Figure B. SD Input Positive Going Threshold (+) vs. Supply Voltage www.irf.com
IRS(S) PbF Case Outline A E X D 8 7 e B H. [.] A. [.] X.7 [.] FOOTPRINT 8X.7 [.8] 8X.78 [.7] DIM INC HES MILLIMETERS MIN MAX MIN MAX A A b c....7.88.98..98....9.7... D E.89.97.98.7.8.8.. e. BASIC.7 BASIC e. BASIC. BASIC H K L y.8.99...9. 8.8.....7 8 e A C y K x 8X b A. [.] C A B. [.] 8X L 7 8X c NOTES:. DIMENSIONING & TOLERANCING PER ASME Y.M-99.. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].. OUTLINE CONFORMS TO JEDEC OUTLINE MS-AA. 8 Lead SOIC DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE. -7 - (MS-AA) 8 Lead PDIP - - (MS-AB) www.irf.com
IRS(S) PbF Tape & Reel 8-lead SOIC LOADED TAPE FEED DIRECTION B A H D F C N OTE : CONTROLLING D IMENSION IN MM E G CARRIER TAPE DIMENSION FOR 8SOICN M etr ic Im p erial Code Min Max Min Max A 7.9 8... 8 B.9... C.7...8 D.... 8 E... 8. F.... 8 G. n/a.9 n/a H... 9. F D E C B A G H REEL DIMENSIONS FOR 8SOICN M etr ic Im p erial Code Min Max Min Max A 9...97. B.9..8.8 C.8...9 D.9..7 7. 9 E 98...88. F n/a 8. n/a.7 G. 7..7.7 H...88. www.irf.com
IRS(S) PbF LEADFREE PART MARKING INFORMATION Part number Date code IRSxxxxx YWW? IR logo Pin Identifier? MARKING CODE P Lead Free Released Non-Lead Free Released?XXXX Lot Code (Prod mode - digit SPN code) Assembly site code Per SCOP - ORDER INFORMATION 8-Lead PDIP IRSPbF 8-Lead SOIC IRSSPbF 8-Lead SOIC Tape & Reel IRSSTRPbF The SOIC-8 is MSL qualified. This product has been designed and qualified for the industrial level. Qualification standards can be found at www.irf.com IR WORLD HEADQUARTERS: Kansas St., El Segundo, California 9 Tel: () -7 Data and specifications subject to change without notice. /7/ www.irf.com