IR2109(4) (S) HALF-BRIDGE DRIVER. Features. Product Summary. Packages. Description. Typical Connection

Transcription

1 Data Sheet No. PD66-T Features Floating channel designed for bootstrap operation Fully operational to +6V Tolerant to negative transient voltage dv/dt immune Gate drive supply range from to V Undervoltage lockout for both channels.v, V and V input logic compatible Cross-conduction prevention logic Matched propagation delay for both channels High side output in phase with input Logic and power ground +/- V offset. Internal ns dead-time, and programmable up to us with one external R DT resistor (IR9) Lower di/dt gate driver for better noise immunity Shut down input turns off both channels. Typical Connection Packages IR9() (S) HALF-BRIDGE DRIVER Product Summary V OFFSET 6V max. I O +/- ma / ma V OUT - V t on/off (typ.) 7 & ns Dead Time ns (programmable up to us for IR9) Description Lead SOIC The IR9()(S) are high voltage, high speed power MOSFET and IGBT drivers with dependent high and 8 Lead SOIC low side referenced output channels. Proprietary HVIC Lead PDIP and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to.v logic. The output drivers feature a high 8 Lead PDIP pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 6 volts. up to 6V V B V S TO AD COM up to 6V IR9 V B IR9 (Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout. V SS R DT DT V SS V S COM TO AD

2 IR9() (S) Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Symbol Definition Units V B High side floating absolute voltage -. 6 V S High side floating supply offset voltage V B - V B +. V High side floating output voltage V S -. V B +. Low side and logic fixed supply voltage -. V Low side output voltage DT Programmable dead-time pin voltage (IR9 only) V SS V Logic input voltage ( & ) V SS V SS Logic ground (IR9/IR89 only) - +. dv S /dt Allowable offset supply voltage transient V/ns P D Package power T A + C (8 Lead PDIP). (8 Lead SOIC).6 ( lead PDIP).6 W ( lead SOIC). Rth JA Thermal resistance, junction to ambient (8 Lead PDIP) (8 Lead SOIC) ( lead PDIP) 7 C/W ( lead SOIC) T J Junction temperature T S Storage temperature - C T L Lead temperature (soldering, seconds) V

3 IR9() (S) Recommended Operating Conditions The input/output logic timing diagram is shown in figure. For proper operation the device should be used within the recommended conditions. The V S and V SS offset rating are tested with all supplies biased at V differential. Symbol Definition Units VB High side floating supply absolute voltage V S + V S + V S High side floating supply offset voltage Note 6 V High side floating output voltage V S V B Low side and logic fixed supply voltage V Low side output voltage V Logic input voltage ( & ) V SS DT Programmable dead-time pin voltage (IR9 only) V SS V SS Logic ground (IR9 only) - T A Ambient temperature - C Note : Logic operational for V S of - to +6V. Logic state held for V S of -V to -V BS. (Please refer to the Design Tip DT97- for more details). V Dynamic Electrical Characteristics V BIAS (, V BS ) = V, V SS = COM, C L = pf, T A = C, DT = VSS unless otherwise specified. Symbol Definition Units Test Conditions ton Turn-on propagation delay 7 9 V S = V toff Turn-off propagation delay 8 V S = V or 6V tsd Shut-down propagation delay 8 MT Delay matching, HS & LS turn-on/off 7 tr Turn-on rise time V S = V tf Turn-off fall time 8 V S = V DT Deadtime: turn-off to turn-on(dt-) & 68 RDT= turn-off to turn-on (DT-) 6 usec RDT = k (IR9) MDT Deadtime matching = DT - - DT- 6 RDT= nsec 6 RDT = k (IR9) nsec

4 IR9() (S) Static Electrical Characteristics V BIAS (, V BS ) = V, V SS = COM, DT= V SS and T A = C unless otherwise specified. The V IL, V IH and I parameters are referenced to V SS /COM and are applicable to the respective input leads: and. The V O, I O and Ron parameters are referenced to COM and are applicable to the respective output leads: and. Symbol Definition Units Test Conditions V IH Logic input voltage for & logic for.9 = V to V V IL Logic input voltage for & logic for.8 = V to V V,TH+ input positive going threshold.9 = V to V V,TH- input negative going threshold.8 V = V to V V OH High level output voltage, V BIAS - V O.8. I O = ma V OL Low level output voltage, V O..6 I O = ma I LK Offset supply leakage current V B = V S = 6V µa I QBS Quiescent V BS supply current 7 V = V or V I QCC Quiescent supply current...6 ma V = V or V RDT = I + Logic input bias current = V, = V I - Logic input bias current µa = V, = V UV+ and V BS supply undervoltage positive going V BSUV+ threshold UV- and V BS supply undervoltage negative going V BSUV- threshold V UVH Hysteresis..7 V BSUVH I O+ Output high short circuit pulsed vurrent V O = V, PW µs I O- Output low short circuit pulsed current ma V O = V,PW µs

5 IR9() (S) Functional Block Diagrams IR9 UV DETECT DELAY COM VCC VS VB PULSE FILTER HV LEVEL SHIFTER R R S Q UV DETECT PULSE GENERATOR VSS/COM LEVEL SHIFT VSS/COM LEVEL SHIFT +V DEADTIME UV DETECT DELAY COM VCC DT VSS VS VB PULSE FILTER HV LEVEL SHIFTER R R S Q UV DETECT PULSE GENERATOR VSS/COM LEVEL SHIFT VSS/COM LEVEL SHIFT +V DEADTIME IR9

6 IR9() (S) Lead Definitions Symbol Description DT VSS V B V S COM Logic input for high and low side gate driver outputs ( and ), in phase with (referenced to COM for IR9 and VSS for IR9) Logic input for shutdown (referenced to COM for IR9 and VSS for IR9) Programmable dead-time lead, referenced to VSS. (IR9 only) Logic Ground (9 only) High side floating supply High side gate drive output High side floating supply return Low side and logic fixed supply Low side gate drive output Low side return Lead Assignments V B 8 V B V S 6 V S 6 COM COM 8 Lead PDIP 8 Lead SOIC IR9 IR9S V B V B DT V S DT V S VSS VSS 6 COM 9 6 COM Lead PDIP Lead SOIC IR9 IR9S 6

7 IR9() (S) () () % % t on t r t off t f Figure. Input/Output Timing Diagram 9% 9% % % Figure. Switching Time Waveform Definitions % % % t sd 9% 9% DT - % 9% DT - Figure. Shutdown Waveform Definitions % MDT= DT - - DT - () Figure. Deadtime Waveform Definitions () % % % MT MT 9% Figure. Delay Matching Waveform Definitions 7

8 IR9() (S) Turn-on Propagation Delay (ns) 9 Max Turn-on Propagation Delay (ns) V BIAS Figure 6A. Turn-on Propagation Delay Figure 6B. Turn-on Propagation Delay Turn-off Propagation Delay (ns) Turn-off Propagation Delay (ns) V BIAS Figure 7A. Turn-off Propagation Delay Figure 7B. Turn-off Propagation Delay 8

9 IR9() (S) Propagation Delay (ns) M ax. Propagation Delay (ns) V BIAS Figure 8A. Propagation Delay Figure 8B. Propagation Delay Turn-on Rise Time (ns) Turn-on Rise Time (ns) M ax V BIAS Figure 9A. Turn-on Rise Time Figure 9B. Turn-on Rise Time 9

10 IR9() (S) Turn-off Fall Time (ns) Turn-off Fall Time (ns) V BIAS Figure A. Turn-off Fall Time Figure B. Turn-off Fall Time Deadtime (ns) 8 6 Deadtime (ns) V BIAS Figure A. Deadtime Figure B. Deadtime

11 IR9() (S) 7 Deadtime ( s) 6 Logic "" Input Voltage (V) R DT (KΩ) Figure C. Deadtime vs. RDT (IR9 only) Figure A. Logic Input Voltage Logic "" Input Voltage (V) Logic "" Input Voltage (V) 6 8 Figure B. Logic Input Voltage Figure A. Logic Input Voltage

12 IR9() (S) Logic "" Input Voltage (V) 6 8 Positive Going Threshold (V) Figure B. Logic Input Current Figure A. Positive Going Threshold Positive Going Threshold (V) Negative Going Threshold (V) Figure B. Positive Going Threshold Figure A. Negative Going Threshold

13 IR9() (S) Negative Going Threshold (V) 6 8 High Level Output Voltage (V) Figure B. Negative Going Threshold Figure 6A. High Level Output Voltage. High Level Output Voltage (V) Low Level Output Voltage (V) V BIAS Figure 6B. High Level Output Voltage Figure 7A. Low Level Output Voltage

14 IR9() (S) Low Level Output Voltage (V) V BIAS Offset Supply Leakage Current ( A) Figure 7B. Low Level Output Voltage Figure 8A. Offset Supply Leakage Current O ffset S upply Leakage C urrent ( A) M ax. 6 V B Boost Volta g e (V ) V BS Supply C urrent ( A) M ax Tem perature ( o C) igure 8B. Offset Supply Leakage Current vs. Boost Voltage Figure 9A. VBS Supply Current

15 IR9() (S). V BS Supply Current ( A) V cc Supply C u rre n t (m A ) V BS Supply V olta g e (V ) Tem perature ( o C) Figure 9B. VBS Supply Current Figure A. VCC Supply Current. 6 Supply Current (ma)..... Logic "" Input Current ( A) i i C Figure B. VCC Supply Current vs. VCC Supply Voltage Figure A. Logic Input Current

16 IR9() (S) 6 Logic "" Input Current ( A) M ax. Logic "" Input Current ( A) 6 8 Figure B. Logic Input Current Figure A. Logic Input Current Logic "" Input Current ( A) UV Threshold (+) (V) Figure B. Logic Input Currentt Figure. VCC Undervoltage Threshold (+) 6

17 IR9() (S) UV Threshold (-) (V) V BS UV Threshold (+) (V) Figure. VCC Undervoltage Threshold (-) Figure. VBS Undervoltage Threshold (+) V BS UV Threshold (-) (V) Output Source Current ( A) Figure 6. VBS Undervoltage Threshold (-) Figure 7A. Output Source Current 7

18 IR9() (S) 6 Output Source Current ( A) 6 8 V BIAS Output Sink Current ( A) Figure 7B. Output Source Current Figure 8A. Output Sink Current 6 Output Sink Current ( A) V S Offset V BIAS V BS Flouting Figure 8B. Output Sink Currentt Figure 9. Maximum VS Negative Offset 8

19 IR9() (S) Temprature ( o C) 8 6 V 7V V 8 6 V 7V V Figure. IR9 vs Frequency (IRFBC) Rgate = Ω, VCC = V Figure. IR9 vs Frequency (IRFBC) Rgate = Ω, VCC = V V 7V V 8 6 V 7V V 8 6 Figure. IR9 vs Frequency (IRFBC) Rgate = Ω, VCC = V Figure. IR9 vs Frequency (IRFPE) Rgate = Ω, VCC = V 9

20 IR9() (S) 8 6 V 7V V 8 V 6 7V V Figure. IR9 vs. Frequency (IRFBC), R gate =Ω, =V Figure. IR9 vs. Frequency (IRFBC), R gate =Ω, =V V 7V 8 6 V 7V V 8 6 V Figure 6. IR9 vs. Frequency (IRFBC), R gate =Ω, =V Figure 7. IR9 vs. Frequency (IRFPE), R gate =Ω, =V

21 IR9() (S) 8 6 V 7V V 8 6 V 7V V Figure 8. IR9S vs. Frequency (IRFBC), R gate =Ω, =V Figure 9. IR9S vs. Frequency (IRFBC), R gate =Ω, =V V 7V V 7V V 8 6 V Tempreture ( o C) 8 6 Figure. IR9S vs. Frequency (IRFBC), R gate =Ω, =V Figure. IR9S vs. Frequency (IRFPE), R gate =Ω, =V

22 IR9() (S) 8 6 V 7V V 8 6 V 7V V Figure. IR9S vs. Frequency (IRFBC), R gate =Ω, =V Figure. IR9S vs. Frequency (IRFBC), R gate =Ω, =V V 7V V 8 6 V 7V V 8 6 Figure. IR9S vs. Frequency (IRFBC), R gate =Ω, =V Figure. IR9S vs. Frequency (IRFPE), R gate =Ω, =V

23 IR9() (S) Case Outlines 8 Lead PDIP -6 - (MS-AB) A E 6 6X D e B H. [.] A 6.6 [.] X.7 [.] FOOTPRT 8X.7 [.8] 8X.78 [.7] DIM C HES MILLIMETERS M MAX M MAX A A b c D E e. BASIC.7 BASIC e. BASIC.6 BASIC H K L y e A C y K x 8X b A. [.] C A B. [.] 8X L 7 8X c NOTES:. DIMENSIONG & TOLERANCG PER ASME Y.M-99.. CONTROLLG DIMENSION: MILLIMETER. DIMENSIONS ARE SWN MILLIMETERS [CHES].. OUTLE CONFORMS TO JEDEC OUTLE MS-AA. 8 Lead SOIC DIMENSION DOES NOT CLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.6]. 6 DIMENSION DOES NOT CLUDE MOLD PROTRUSIONS. MOLD PROTRUSIONS NOT TO EXCEED. [.]. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERG TO A SUBSTRATE (MS-AA)

24 IR9() (S) Lead PDIP -6 - (MS-AC) Lead SOIC (narrow body) (MS-AB) Data and specifications subject to change without notice. 7//

25 This datasheet has been download from: Datasheets for electronics components.