HUF76137P3, HUF76137S3S

HUF7137P3, HUF7137S3S Data Sheet December 21 75A, 3V,.9 Ohm, NChannel, Logic Level UltraFET Power MOSFETs These NChannel power MOSFETs are manufactured using the innovative UltraFET process. This advanced process technology achieves the lowest possible onresistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and batteryoperated products. Formerly developmental type TA7137. Ordering Information PART NUMBER PACKAGE BRAND Features Logic Level Gate Drive 75A, 3V Ultra Low OnResistance, r DS(ON) =.9Ω Temperature Compensating PSPICE Model Temperature Compensating SABER Model Thermal Impedance SPICE Model Thermal Impedance SABER Model Peak Current vs Pulse Width Curve UIS Rating Curve Related Literature TB334, Guidelines for Soldering Surface Mount Components to PC Boards Symbol D HUF7137P3 TO22AB 7137P HUF7137S3S TO23AB 7137S NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO23AB variant in tape and reel, e.g., HUF7137S3ST. G S Packaging JEDEC TO22AB JEDEC TO23AB DRAIN (FLANGE) SOURCE DRAIN GATE GATE SOURCE DRAIN (FLANGE) 21 Fairchild Semiconductor Corporation HUF7137P3, HUF7137S3S Rev. B

Absolute Maximum Ratings T C = 25 o C, Unless Otherwise Specified UNITS Drain to Source Voltage (Note 1).......................................... V DSS 3 V Drain to Gate Voltage (R GS = 2kΩ) (Note 1)................................ V DGR 3 V Gate to Source Voltage.................................................. V GS ±1 V Drain Current Continuous (T C = 25 o C, V GS = 1V) (Figure 2)............................... I D Continuous (T C = 1 o C, V GS = 5V)........................................ I D Continuous (T C = 1 o C, V GS = 4.5V) (Figure 2).............................. I D Pulsed Drain Current.................................................. I DM 75 55 52 Figure 4 Pulsed Avalanche Rating................................................. E AS Figures, 17, 1 Power Dissipation....................................................... P D Derate Above 25 o C...................................................... Operating and Storage Temperature.................................... T J, T STG 4 to 15 Maximum Temperature for Soldering Leads at.3in (1.mm) from Case for 1s................................. T L 3 Package Body for 1s, See Techbrief 334.................................. T pkg 2 145 1.1 A A A W W/ o C o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. T J = 25 o C to 15 o C. HUF7137P3, HUF7137S3S o C o C Electrical Specifications T A = 25 o C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BV DSS I D = 25µA, V GS = V (Figure 12) 3 V Zero Gate Voltage Drain Current I DSS V DS = 25V, V GS = V 1 µa V DS = 25V, V GS = V, T C = 15 o C 25 µa Gate to Source Leakage Current I GSS V GS = ±1V ±1 na ON STATE SPECIFICATIONS Gate to Source Threshold Voltage V GS(TH) V GS = V DS, I D = 25µA (Figure 11) 1 3 V Drain to Source On Resistance r DS(ON) I D = 75A, V GS = 1V (Figures 9, 1).75.9 Ω I D = 55A, V GS = 5V (Figure 9).1.125 Ω I D = 52A, V GS = 4.5V (Figure 9).11.14 Ω THERMAL SPECIFICATIONS Thermal Resistance Junction to Case R θjc (Figure 3). o C/W Thermal Resistance Junction to Ambient R θja TO22 and TO23 2 o C/W SWITCHING SPECIFICATIONS (V GS = 4.5V) TurnOn Time t ON V DD = 15V, I D 52A, 42 ns TurnOn Delay Time t d(on) R L =.29Ω, V GS = 4.5V, R GS = 5.1Ω 2 ns Rise Time t r (Figures 15, 21, 22) 2 ns TurnOff Delay Time t d(off) 2 ns Fall Time t f 3 ns TurnOff Time t OFF 1 ns 21 Fairchild Semiconductor Corporation HUF7137P3, HUF7137S3S Rev. B

HUF7137P3, HUF7137S3S Electrical Specifications T A = 25 o C, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SWITCHING SPECIFICATIONS (V GS = 1V) TurnOn Time t ON V DD = 15V, I D 75A, 225 ns TurnOn Delay Time t d(on) R L =.2Ω, V GS = 1V, R GS = 5.Ω 1 ns Rise Time t r (Figures 1, 21, 22) 14 ns TurnOff Delay Time t d(off) 45 ns Fall Time t f 35 ns TurnOff Time t OFF 12 ns GATE CHARGE SPECIFICATIONS Total Gate Charge Q g(tot) V GS = V to 1V V DD = 15V, 55 72 nc Gate Charge at 5V Q g(5) V GS = V to 5V I D 55A, R L =.273Ω 31 4 nc Threshold Gate Charge Q g(th) V GS = V to 1V I g(ref) = 1.mA 2.2 2.9 nc (Figures 14, 19, 2) Gate to Source Gate Charge Q gs. nc Gate to Drain Miller Charge Q gd 15.5 nc CAPACITANCE SPECIFICATIONS Input Capacitance C ISS V DS = 25V, V GS = V, 21 pf Output Capacitance C OSS f = 1MHz (Figure 13) 15 pf Reverse Transfer Capacitance C RSS 225 pf Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage V SD I SD = 55A 1.25 V Reverse Recovery Time t rr I SD = 55A, di SD /dt = 1A/µs 77 ns Reverse Recovered Charge Q RR I SD = 55A, di SD /dt = 1A/µs 143 nc Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1....4.2 I D, DRAIN CURRENT (A) 4 2 V GS = 4.5V V GS = 1V 25 5 75 1 125 15 T C, CASE TEMPERATURE ( o C) 25 5 75 1 125 T C, CASE TEMPERATURE ( o C) 15 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 21 Fairchild Semiconductor Corporation HUF7137P3, HUF7137S3S Rev. B

HUF7137P3, HUF7137S3S Typical Performance Curves (Continued) Z θjc, NORMALIZED THERMAL IMPEDANCE 2 1.1 DUTY CYCLE DESCENDING ORDER.5.2.1.5.2.1 t 1 t 2 NOTES: DUTY FACTOR: D = t 1 /t 2 SINGLE PULSE PEAK T J = P DM x Z θjc x R θjc T C.1 1 5 1 4 1 3 1 2 1 1 1 t, RECTANGULAR PULSE DURATION (s) P DM 1 1 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE I DM, PEAK CURRENT (A) 2 1 V GS = 1V V GS = 5V T C = 25 o C FOR TEMPERATURES ABOVE 25 o C DERATE PEAK CURRENT AS FOLLOWS: I = I 25 15 T C TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 5 1 5 1 4 1 3 1 2 1 1 1 1 1 t, PULSE WIDTH (s) 125 FIGURE 4. PEAK CURRENT CAPABILITY I D, DRAIN CURRENT (A) 1 1 1 T J = MAX RATED T C = 25 o C 1µs 1ms 1ms OPERATION IN THIS AREA MAY BE LIMITED BY r DS(ON) BV DSS MAX = 3V 1 1 1 1 1.1.1.1 1 1 1 V DS, DRAIN TO SOURCE VOLTAGE (V) t AV, TIME IN AVALANCHE (ms) I AS, AVALANCHE CURRENT (A) 2 1 1 1 If R = t AV = (L)(I AS )/(1.3*RATED BV DSS V DD ) If R t AV = (L/R)ln[(I AS *R)/(1.3*RATED BV DSS V DD ) 1] STARTING T J = 15 o C STARTING T J = 25 o C FIGURE 5. FORWARD BIAS SAFE OPERATING AREA NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 21 Fairchild Semiconductor Corporation HUF7137P3, HUF7137S3S Rev. B

HUF7137P3, HUF7137S3S Typical Performance Curves (Continued) I D, DRAIN CURRENT (A) 15 12 9 3 PULSE DURATION = µs DUTY CYCLE =.5% MAX V DD = 15V 4 o C 25 o C 15 o C 1 2 3 4 5 V GS, GATE TO SOURCE VOLTAGE (V) I D, DRAIN CURRENT (A) 15 V GS = 1V V GS = 5V V GS = 4.5V V GS = 4V 12 9 V GS = 3.5V V GS = 3V 3 PULSE DURATION = µs DUTY CYCLE =.5% MAX T C = 25 o C 1 2 3 4 5 V DS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 7. TRANSFER CHARACTERISTICS FIGURE. SATURATION CHARACTERISTICS r DS(ON), DRAIN TO SOURCE ON RESISTANCE (mω) 2 1 12 I D = 25A I D = 75A I D = 5A PULSE DURATION = µs DUTY CYCLE =.5% MAX NORMALIZED DRAIN TO SOURCE ON RESISTANCE 1. 1.4 1.2 1. PULSE DURATION = µs DUTY CYCLE =.5% MAX V GS = 1V, I D = 75A 4 2 4 1 V GS, GATE TO SOURCE VOLTAGE (V). 12 T J, JUNCTION TEMPERATURE ( o C) 1 FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 1. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1... V GS = V DS, I D = 25µA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.15 1.1 1.5 1..95 I D = 25µA.4 12 T J, JUNCTION TEMPERATURE ( o C) 1.9 12 T J, JUNCTION TEMPERATURE ( o C) 1 FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 21 Fairchild Semiconductor Corporation HUF7137P3, HUF7137S3S Rev. B

HUF7137P3, HUF7137S3S Typical Performance Curves (Continued) C, CAPACITANCE (pf) 3 25 2 15 1 5 C ISS C OSS C RSS V GS = V, f = 1MHz C ISS = C GS C GD C RSS = C GD C OSS C DS C GD 5 1 15 2 25 V DS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 3 V GS, GATE TO SOURCE VOLTAGE (V) 1 4 2 V DD = 15V 1 WAVEFORMS IN DESCENDING ORDER: I D = 75A I D = 5A I D = 25A 2 3 4 5 Q g, GATE CHARGE (nc) NOTE: Refer to Fairchild Application Notes AN7254 and AN72. FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT SWITCHING TIME (ns) 1 4 2 V GS = 4.5V, V DD = 15V, I D = 52A, R L =.29Ω t r t d(off) t f SWITCHING TIME (ns) 4 3 2 1 V GS = 1V, V DD = 15V, I D = 75A, R L =.2Ω t d(off) t f t r t d(on) t d(on) 1 2 3 4 5 R GS, GATE TO SOURCE RESISTANCE (Ω) 1 2 3 4 5 R GS, GATE TO SOURCE RESISTANCE (Ω) FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 1. SWITCHING TIME vs GATE RESISTANCE Test Circuits and Waveforms V DS BV DSS L t P V DS VARY t P TO OBTAIN REQUIRED PEAK I AS V GS R G V DD I AS V DD DUT V t P I AS.1Ω t AV FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 1. UNCLAMPED ENERGY WAVEFORMS 21 Fairchild Semiconductor Corporation HUF7137P3, HUF7137S3S Rev. B

HUF7137P3, HUF7137S3S Test Circuits and Waveforms (Continued) V DS R L V DD Q g(tot) V DS V GS = 1 V GS Q g(5) V DD V GS V GS = 5V I g(ref) DUT V GS = 1V Q g(th) I g(ref) FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 2. GATE CHARGE WAVEFORMS V DS t ON t d(on) t OFF t d(off) R L t r t f V DS 9% 9% V GS V DD 1% 1% V GS R GS DUT V GS 1% 5% PULSE WIDTH 9% 5% FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM 21 Fairchild Semiconductor Corporation HUF7137P3, HUF7137S3S Rev. B

PSPICE Electrical Model SUBCKT HUF7137 2 1 3 ; REV May 199 HUF7137P3, HUF7137S3S CA 12 3.1e9 CB 15 14 3.1e9 CIN 1.e9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 1 5 DPLCAPMOD EBREAK 11 7 17 1 33.7 EDS 14 5 1 EGS 13 1 ESG 1 1 EVTHRES 21 19 1 EVTEMP 2 1 22 1 IT 17 1 LDRAIN 2 5 1e9 LGATE 1 9.73e9 LSOURCE 3 7 2.3e9 MMED 1 MMEDMOD MSTRO 1 MSTROMOD MWEAK 1 21 MWEAKMOD RBREAK 17 1 RBREAKMOD 1 RDRAIN 5 1 RDRAINMOD 1.2e3 RGATE 9 2 1 RLDRAIN 2 5 1 RLGATE 1 9 7.3 RLSOURCE 3 7 2.3 RSLC1 5 51 RSLCMOD 1e RSLC2 5 5 1e3 RSOURCE 7 RSOURCEMOD 5.1e3 RVTHRES 22 RVTHRESMOD 1 RVTEMP 1 19 RVTEMPMOD 1 S1A 12 13 S1AMOD S1B 13 12 13 S1BMOD S2A 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 GATE 1 LGATE RLGATE CA ESG S1B EGS EVTEMP RGATE 9 2 1 22 S1A 12 13 13 1 S2A 14 13 DPLCAP RSLC2 5 51 EVTHRES 1 19 21 CIN 15 RDRAIN MMED MSTRO 17 1 RBREAK 17 1 S2B RVTEMP CB 19 IT 14 5 VBAT EDS 5 RSLC1 51 5 ESLC DBREAK EBREAK MWEAK 11 RSOURCE 7 RVTHRES 22 LDRAIN RLDRAIN DBODY LSOURCE SOURCE 3 RLSOURCE DRAIN 2 ESLC 51 5 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e*5),4))}.MODEL DBODYMOD D (IS = 2.5e12 IKF = 4 RS = 3.5e3 TRS1 = 3e4 TRS2 = e CJO = 3.1e9 TT = 9e M = 4e1 XTI =5.2 ).MODEL DBREAKMOD D (RS = 1.25e 2TRS1 = 3e 3TRS2 = 3.5e5 IKF = 1).MODEL DPLCAPMOD D (CJO = 2.5e 9IS = 1e3 N = 1 M = 7.5e1).MODEL MMEDMOD NMOS (VTO = 1.73 KP = 2 IS = 1e3 N = 1 TOX = 1 L = 1u W = 1u RG = 1).MODEL MSTROMOD NMOS (VTO = 2. KP = 13 IS = 1e3 N = 1 TOX = 1 L = 1u W = 1u).MODEL MWEAKMOD NMOS (VTO = 1.3 KP =1e2 IS = 1e3 N = 1 TOX = 1 L = 1u W = 1u RG = 1 RS = 1e1).MODEL RBREAKMOD RES (TC1 = 1e 3TC2 = 1e9).MODEL RDRAINMOD RES (TC1 = 1.1e2 TC2 = 1e5).MODEL RSLCMOD RES (TC1 = 7e3 TC2 = 7e9).MODEL RSOURCEMOD RES (TC1 = 1e3 TC2 = e).model RVTHRESMOD RES (TC1 = 1.e3 TC2 = 1e5).MODEL RVTEMPMOD RES (TC1 = 1.5e 3TC2 = 1e).MODEL S1AMOD VSWITCH (RON = 1e5 ROFF =.1 VON =.5 VOFF=.5).MODEL S1BMOD VSWITCH (RON = 1e5 ROFF =.1 VON =.5 VOFF=.5).MODEL S2AMOD VSWITCH (RON = 1e5 ROFF =.1 VON = 1.5 VOFF=.5).MODEL S2BMOD VSWITCH (RON = 1e5 ROFF =.1 VON =.5 VOFF= 1.5).ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE SubCircuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 21 Fairchild Semiconductor Corporation HUF7137P3, HUF7137S3S Rev. B

HUF7137P3, HUF7137S3S SABER Electrical Model nom temp=25 deg c 3v LL Ultrafet REV May199 template huf7137 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is=2.5e12,xti=5.2,cjo=3.1e9,tt=9e,m=4e1) d..model dbreakmod = () d..model dplcapmod = (cjo=2.5e9,is=1e3,n=1,m=7.5e1) m..model mmedmod = (type=_n,vto=1.73,kp=2,is=1e3, tox=1) m..model mstrongmod = (type=_n,vto=2.,kp=13,is=1e3, tox=1) m..model mweakmod = (type=_n,vto=1.3,kp=1e2,is=1e3, tox=1) sw_vcsp..model s1amod = (ron=1e5,roff=.1,von=.5,voff=.5) sw_vcsp..model s1bmod = (ron=1e5,roff=.1,von=.5,voff=.5) sw_vcsp..model s2amod = (ron=1e5,roff=.1,von=1.5,voff=.5) sw_vcsp..model s2bmod = (ron=1e5,roff=.1,von=.5,voff=1.5) c.ca n12 n = 3.1e9 c.cb n15 n14 = 3.1e9 c.cin n n = 1.e9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n1 n5 = model=dplcapmod i.it n n17 = 1 l.ldrain n2 n5 = 1e9 l.lgate n1 n9 =.73e9 l.lsource n3 n7 = 2.3e9 m.mmed n1 n n n = model=mmedmod, l=1u, w=1u m.mstrong n1 n n n = model=mstrongmod, l=1u, w=1u m.mweak n1 n21 n n = model=mweakmod, l=1u, w=1u res.rbreak n17 n1 = 1, tc1=1e3,tc2=1e9 res.rdbody n71 n5 =3.5e3, tc1=3e4, tc2=e res.rdbreak n72 n5 =1.25e2, tc1=3e3, tc2=3.5e5 res.rdrain n5 n1 = 1.2e3, tc1=1.1e2,tc2=1e5 res.rgate n9 n2 = 1 res.rldrain n2 n5 = 1 res.rlgate n1 n9 = 7.3 res.rlsource n3 n7 = 2.3 res.rslc1 n5 n51 = 1e, tc1=7e3,tc2=7e9 res.rslc2 n5 n5 = 1e3 res.rsource n n7 = 5.1e3, tc1=e3,tc2=e res.rvtemp n1 n19 = 1, tc1=1.e3,tc2=1e5 res.rvthres n22 n = 1, tc1=1.5e3,tc2=1e spe.ebreak n11 n7 n17 n1 = 33.7 spe.eds n14 n n5 n = 1 spe.egs n13 n n n = 1 spe.esg n n1 n n = 1 spe.evtemp n2 n n1 n22 = 1 spe.evthres n n21 n19 n = 1 sw_vcsp.s1a n n12 n13 n = model=s1amod sw_vcsp.s1b n13 n12 n13 n = model=s1bmod sw_vcsp.s2a n n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 GATE 1 LGATE RLGATE EVTEMP RGATE 1 9 22 2 equations { i (n51>n5) =iscl iscl: v(n51,n5) = ((v(n5,n51)/(1e9abs(v(n5,n51))))*((abs(v(n5,n51)*1e/5))** 4)) } } CA ESG S1A 12 13 S1B EGS 13 1 S2A 14 13 DPLCAP RSLC2 EVTHRES 1 19 21 CIN 15 5 RSLC1 51 5 ISCL RDRAIN MMED MSTRO EBREAK 17 1 RBREAK 17 1 S2B RVTEMP CB 19 IT 14 5 VBAT EDS RDBREAK 72 DBREAK MWEAK 11 RSOURCE 7 RVTHRES 22 71 LDRAIN RLDRAIN RDBODY DBODY LSOURCE SOURCE 3 RLSOURCE DRAIN 2 21 Fairchild Semiconductor Corporation HUF7137P3, HUF7137S3S Rev. B

HUF7137P3, HUF7137S3S SPICE Thermal Model th JUNCTION REV May 199 HUF7137 CTHERM1 th 1.e CTHERM2 5 2.e CTHERM3 5 4.e3 CTHERM4 4 3 9.5e3 CTHERM5 3 2 3.e2 CTHERM 2 tl 1. RTHERM1 CTHERM1 RTHERM1 th 1.e4 RTHERM2 5 1.4e3 RTHERM3 5 4 2.9e2 RTHERM4 4 3 1.e1 RTHERM5 3 2 2.e1 RTHERM 2 tl 4.e2 RTHERM2 5 CTHERM2 SABER Thermal Model RTHERM3 CTHERM3 Saber thermal model HUF7137 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th = 1.e ctherm.ctherm2 5 = 2.e ctherm.ctherm3 5 4 =.e3 ctherm.ctherm4 4 3 = 9.5e3 ctherm.ctherm5 3 2 = 3.e1 ctherm.ctherm 2 tl = 1. RTHERM4 4 3 CTHERM4 rtherm.rtherm1 th = 1.e4 rtherm.rtherm2 5 = 1.4e3 rtherm.rtherm3 5 4 = 2.9e2 rtherm.rtherm4 4 3 = 1.e1 rtherm.rtherm5 3 2 = 2.e1 rtherm.rtherm 2 tl = 4.e2 } RTHERM5 RTHERM 2 CTHERM5 CTHERM tl CASE 21 Fairchild Semiconductor Corporation HUF7137P3, HUF7137S3S Rev. B

TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx Bottomless CoolFET CROSSVOLT DenseTrench DOME EcoSPARK E 2 CMOS TM EnSigna TM FACT FACT Quiet Series STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms FAST FASTr FRFET GlobalOptoisolator GTO HiSeC ISOPLANAR LittleFET MicroFET MicroPak MICROWIRE OPTOLOGIC OPTOPLANAR PACMAN POP Power247 PowerTrench QFET QS QT Optoelectronics Quiet Series SILENT SWITCHER SMART START STAR*POWER Stealth SuperSOT 3 SuperSOT SuperSOT SyncFET TinyLogic TruTranslation UHC UltraFET 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Datasheet Identification Product Status Definition VCX Advance Information Preliminary No Identification Needed Formative or In Design First Production Full Production This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4

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