Applications. Pin 1 TOP. WL-CSP 0.8X0.8 Thin

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1 FDZ66PZ P-Channel.5 V Specified PowerTrench Thin WL-CSP MOSFET - V, -.6 A, 4 mω Features Max r DS(on) = 4 mω at V GS = -4.5 V, I D = - A Max r DS(on) = 8 mω at V GS = -.5 V, I D = -.5 A Max r DS(on) = 3 mω at V GS = -.8 V, I D = - A Max r DS(on) = 35 mω at V GS = -.5 V, I D = - A Occupies only.64 mm of PCB area. Less than 6% of the area of x BGA Ultra-thin package: less than.4 mm height when mounted to PCB HBM ESD protection level > kv (Note3) RoHS Compliant D S BOTTOM G S Pin Pin General Description December Designed on Fairchild's advanced.5 V PowerTrench process with state of the art "fine pitch" Thin WLCSP packaging process, the FDZ66PZ minimizes both PCB space and r DS(on). This advanced WLCSP MOSFET embodies a breakthrough in packaging technology which enables the device to combine excellent thermal transfer characteristics, ultra-low profile (.4 mm) and small (.8x.8 mm ) packaging, low gate charge, and low r DS(on). Applications Battery management Load switch Battery protection TOP WL-CSP.8X.8 Thin MOSFET Maximum Ratings T A = 5 C unless otherwise noted Symbol Parameter Ratings Units V DS Drain to Source Voltage - V V GS Gate to Source Voltage ±8 V -Continuous T A = 5 C (Note a) -.6 I D -Pulsed - A Power Dissipation T A = 5 C (Note a).3 P D Power Dissipation T A = 5 C (Note b).4 W T J, T STG Operating and Storage Junction Temperature Range -55 to +5 C Thermal Characteristics R θja Thermal Resistance, Junction to Ambient (Note a) 93 R θja Thermal Resistance, Junction to Ambient (Note b) 3 Package Marking and Ordering Information C/W Device Marking Device Package Reel Size Tape Width Quantity EH FDZ66PZ WL-CSP.8X.8 Thin 7 8 mm 5 units

2 Electrical Characteristics T J = 5 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BV DSS Drain to Source Breakdown Voltage I D = -5 μa, V GS = V - V ΔBV DSS Breakdown Voltage Temperature ΔT J Coefficient I D = -5 μa, referenced to 5 C -3 mv/ C I DSS Zero Gate Voltage Drain Current V DS = -6 V, V GS = V - μa I GSS Gate to Source Leakage Current V GS = ±8 V, V DS = V ±6 μa On Characteristics V GS(th) Gate to Source Threshold Voltage V GS = V DS, I D = -5 μa V ΔV GS(th) ΔT J Gate to Source Threshold Voltage Temperature Coefficient Dynamic Characteristics Switching Characteristics Drain-Source Diode Characteristics I D = -5 μa, referenced to 5 C.5 mv/ C V GS = -4.5 V, I D = - A 8 4 V GS = -.5 V, I D = -.5 A 9 8 r DS(on) Static Drain to Source On Resistance V GS = -.8 V, I D = - A 59 3 mω V GS = -.5 V, I D = - A 35 V GS = -4.5 V, I D = - A, T J =5 C 43 4 g FS Forward Transconductance V DD = -5 V, I D = - A 7.8 S C iss Input Capacitance pf V DS = - V, V GS = V, C oss Output Capacitance 6 8 pf f = MHz C rss Reverse Transfer Capacitance 53 7 pf t d(on) Turn-On Delay Time 4.9 ns t r Rise Time V DD = - V, I D = -.5 A, ns t d(off) Turn-Off Delay Time V GS = -4.5 V, R GEN = 6 Ω 68 8 ns t f Fall Time 33 5 ns Q g Total Gate Charge nc V GS = -4.5 V, V DD = - V, Q gs Gate to Source Charge.6 nc I D = -.5 A Q gd Gate to Drain Miller Charge.7 nc V SD Source to Drain Diode Forward Voltage V GS = V, I S = -.4 A (Note ) V t rr Reverse Recovery Time 9 46 ns I F = -.5 A, di/dt = A/μs Q rr Reverse Recovery Charge 8 nc Notes:. R θja is determined with the device mounted on a in pad oz copper pad on a.5 x.5 in. board of FR-4 material. R θjc is guaranteed by design while R θca is determined by the user's board design. a. 93 C/W when mounted on a in pad of oz copper. b. 3 C/W when mounted on a minimum pad of oz copper.. Pulse Test: Pulse Width < 3 μs, Duty cycle <.%. 3. The diode connected between the gate and source serves only as protection ESD. No gate overvoltage rating is implied.

3 Typical Characteristics T J = 5 C unless otherwise noted -ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE -ID, DRAIN CURRENT (A) V GS = -4.5 V V GS = -3 V V GS = -.5 V PULSE DURATION = 8 μs DUTY CYCLE =.5% MAX 3 -V DS, DRAIN TO SOURCE VOLTAGE (V) Figure. V GS = -.5 V V GS = -.8 V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE PULSE DURATION = 8 μs DUTY CYCLE =.5% MAX I D, DRAIN CURRENT (A) On-Region Characteristics Figure. Normalized On-Resistance vs Drain Current and Gate Voltage T J, JUNCTION TEMPERATURE ( o C) Figure 3. Normalized On- Resistance vs Junction Temperature I D = - A V GS = -4.5 V PULSE DURATION = 8 μs DUTY CYCLE =.5% MAX V DS = -5 V T J = 5 o C T J = 5 o C T J = -55 o C V GS, GATE TO SOURCE VOLTAGE (V) rds(on), DRAIN TO SOURCE ON-RESISTANCE (mω) -IS, REVERSE DRAIN CURRENT (A) Figure 4. V GS = -.5 V I D = - A V GS = -.8 V T J = 5 o C T J = 5 o C V GS = -3 V V GS = -.5 V V GS = -4.5 V PULSE DURATION = 8 μs DUTY CYCLE =.5% MAX V GS = V -V GS, GATE TO SOURCE VOLTAGE (V) On-Resistance vs Gate to Source Voltage T J = 5 o C T J = 5 o C T J = -55 o C V SD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current 3

4 Typical Characteristics T J = 5 C unless otherwise noted -V GS, GATE TO SOURCE VOLTAGE (V) - Ig, GATE LEAKAGE CURRENT (A) I D = -.5 A Q g, GATE CHARGE (nc) Figure VDS = V V DD = - V V DD = -8 V V DD = - V. -V DS, DRAIN TO SOURCE VOLTAGE (V) Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage T J = 5 o C T J = 5 o C V GS, GATE TO SOURCE VOLTAGE (V) Figure 9. Gate Leakage Current vs Gate to Source Voltage CAPACITANCE (pf) -ID, DRAIN CURRENT (A) 5.. f = MHz V GS = V THIS AREA IS LIMITED BY r DS(on) SINGLE PULSE TJ = MAX RATED R θja = 3 o C/W C iss C oss C rss T A = 5 o C.. -V DS, DRAIN to SOURCE VOLTAGE (V) Figure. Forward Bias Safe Operating Area us ms ms ms s s DC P (PK), PEAK TRANSIENT POWER (W) t, PULSE WIDTH (sec) Figure. Single Pulse Maximum Power Dissipation SINGLE PULSE R θja = 3 o C/W T A = 5 o C 4

5 Typical Characteristics T J = 5 C unless otherwise noted NORMALIZED THERMAL IMPEDANCE, Z θja.. DUTY CYCLE-DESCENDING ORDER D = SINGLE PULSE R θja = 3 o C/W t, RECTANGULAR PULSE DURATION (sec) Figure. Junction-to-Ambient Transient Thermal Response Curve P DM t t NOTES: DUTY FACTOR: D = t /t PEAK T J = P DM x Z θja x R θja + T A 5

6 Dimensional Outline and Pad Layout 6

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