Data Sheet FN295. 00V, 3A/A Peak, High Frequency Half-Bridge Drivers The ISL20, ISL2 are 00V, high frequency, half-bridge N-Channel power MOSFET driver ICs. They are based on the popular P200, P20 half-bridge drivers, but offer several performance improvements. Peak output pull-up/ pull-down current has been increased to 3A/A, which significantly reduces switching power losses and eliminates the need for external totem-pole buffers in many applications. Also, the low end of the V DD operational supply range has been extended to 8VDC. The ISL20 has additional input hysteresis for superior operation in noisy environments and the inputs of the ISL2, like those of the ISL20, can now safely swing to the V DD supply rail. Ordering Information PART NUMBER (Notes, 2) PART MARKING TEMP RANGE ( C) PACKAGE (Pb-Free) PKG. DWG. # ISL20ABZ 20 ABZ -0 to +25 8 Ld SOIC M8.5 ISL20ARZ 2 0ARZ -0 to +25 2 Ld x DFN L2.xA ISL2ABZ 2 ABZ -0 to +25 8 Ld SOIC M8.5 ISL2ARZ 2 ARZ -0 to +25 2 Ld x DFN L2.xA ISL2ARTZ 2 ARTZ -0 to +25 0 Ld x TDFN L0.x ISL2BRZ 2 BRA -0 to +25 8 Ld x DFN L8.x NOTES:. Add -T* suffix for tape and reel. Please refer to TB37 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 00% matte tin plate plus anneal (e3 termination finish, which is Ro compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL20, ISL2. For more information on MSL please see techbrief TB33. Features Drives N-Channel MOSFET Half-Bridge SOIC, DFN and TDFN Package Options SOIC, DFN and TDFN Packages Compliant with 00V Conductor Spacing Guidelines per IPC-222 Pb-Free (Ro Compliant) Bootstrap Supply Max Voltage to VDC On-Chip W Bootstrap Diode Fast Propagation Times for Multi-MHz Circuits Drives nf Load with Typical Rise/Fall Times of 9ns/7.5ns CMOS Compatible Input Thresholds (ISL20) 3.3V/TTL Compatible Input Thresholds (ISL2) Independent Inputs Provide Flexibility No Start-Up Problems Outputs Unaffected by Supply Glitches, Ringing Below Ground or Slewing at High dv/dt Low Power Consumption Wide Supply Voltage Range (8V to V) Supply Undervoltage Protection.W/W Typical Output Pull-Up/Pull-Down Resistance Applications Telecom Half-Bridge DC/DC Converters Telecom Full-Bridge DC/DC Converters Two-Switch Forward Converters Active-Clamp Forward Converters Class-D Audio Amplifiers CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. -888-INTERSIL or -888-8-377 Copyright Intersil Americas Inc. 200-2009, 20, 202. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
Pinouts ISL2ARTZ (0 LD x TDFN) ISL20ARZ, ISL2ARZ (2 LD x DFN) VDD 0 VDD 2 2 9 VSS 2 VSS 3 8 7 3 EPAD* 0 9 5 5 8 7 *EPAD = Exposed PAD ISL20ABZ, ISL2ABZ (8 LD SOIC) ISL2BRZ (8 LD x DFN) VDD 2 3 8 7 5 VSS V DD 2 3 EPAD* 8 7 5 V SS *EPAD = EXPOSED PAD Application Block Diagram +2V +00V V DD SECONDARY CIRCUIT PWM CONTROLLER CONTROL DRIVE DRIVE V SS ISL20 ISL2 REFEREE AND ISOLATION 2 FN295.
Functional Block Diagram V DD UNDER VOLTAGE LEVEL SFT DRIVER ISL2 ISL2 UNDER VOLTAGE DRIVER V SS EPAD (DFN Package Only) *EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For best thermal performance connect the EPAD to the PCB power ground plane. +8V +2V PWM ISL20 ISL2 SECONDARY CIRCUIT ISOLATION FIGURE. TWO-SWITCH FORWARD CONVERTER +8V +2V SECONDARY CIRCUIT PWM ISL20 ISL2 ISOLATION FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE-CLAMP 3 FN295.
Absolute Maximum Ratings Supply Voltage, V DD, V - V (Notes, 5)........ -0.3V to 8V and Voltages (Note 5)................ -0.3V to V DD + 0.3V Voltage on (Note 5)................... -0.3V to V DD + 0.3V Voltage on (Note 5).............. V - 0.3V to V + 0.3V Voltage on (Continuous) (Note 5).............. -V to 0V Voltage on (Note 5)............................... 8V Average Current in V DD to Diode.................. 00mA Maximum Recommended Operating Conditions Supply Voltage, V DD............................. 8V to V Voltage on................................ -V to 00V Voltage on...............(repetitive Transient) -5V to 05V Voltage on.....v +7V to V +V and V DD - V to V DD +00V Slew Rate.................................... <50V/ns Thermal Information Thermal Resistance (Typical) θ JA ( C/W) θ JC ( C/W) 8 Ld SOIC (Notes, 0)............ 95 0 Ld TDFN (Notes 7, 8)........... 2 5.5 2 Ld DFN (Notes 7, 8)............ 0 5.5 8 Ld DFN (Notes 7, 8)............. 0.0 Max Power Dissipation at +25 C in Free Air 8 Ld SOIC (Notes, 0)..............................3W 0 Ld TDFN (Notes 7, 8)............................. 3.0W 2 Ld DFN (Notes 7, 8).............................. 3.W 8 Ld DFN (Notes 7, 8)............................... 3.W Storage Temperature Range................... -5 C to +50 C Junction Temperature Range..................-55 C to +50 C Pb-free reflow profile..........................see link below http://www.intersil.com/pbfree/pb-freereflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES:. The ISL20 and ISL2 are capable of derated operation at supply voltages exceeding V. Figure 22 shows the high-side voltage derating curve for this mode of operation. 5. All voltages referenced to V SS unless otherwise specified.. θ JA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details. 7. θ JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech Brief TB379. 8. For θ JC, the case temp location is the center of the exposed metal pad on the package underside. 9. Parameters with MIN and/or MAX limits are 00% tested at +25 C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 0. For θ JC, the case temp location is taken at the package top center. Electrical Specifications V DD = V = 2V, V SS = V = 0V, No Load on or, unless otherwise specified. T J = +25 C T J = -0 C to +25 C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN (Note 9) MAX (Note 9) UNITS SUPPLY CURRENTS V DD Quiescent Current I DD ISL20; = = 0V - 0. 0.25-0.3 ma V DD Quiescent Current I DD ISL2; = = 0V - 0.3 0.5-0.55 ma V DD Operating Current I DDO ISL20; f = 500kHz - 3. 5.0-5.5 ma V DD Operating Current I DDO ISL2; f = 500kHz - 3.5 5.0-5.5 ma Total Quiescent Current I = = 0V - 0. 0.5-0.2 ma Total Operating Current I O f = 500kHz - 3. 5.0-5.5 ma to V SS Current, Quiescent I S = = 0V; V = V = V - 0.05.5-0 µa to V SS Current, Operating I SO f = 500kHz; V = V = V -.2 - - - ma INPUT PINS Low Level Input Voltage Threshold V IL ISL20 3.7. - 3.5 - V Low Level Input Voltage Threshold V IL ISL2..8 -.2 - V High Level Input Voltage Threshold V IH ISL20 -. 7. - 7. V High Level Input Voltage Threshold V IH ISL2 -.8 2.2-2. V Input Voltage Hysteresis V IHYS ISL20-2.2 - - - V Input Pull-Down Resistance R I - 20-00 500 kω FN295.
Electrical Specifications V DD = V = 2V, V SS = V = 0V, No Load on or, unless otherwise specified. (Continued) T J = +25 C T J = -0 C to +25 C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN (Note 9) MAX (Note 9) UNITS UNDERVOLTAGE PROTECTION V DD Rising Threshold V DDR.. 7. 5.8 7. V V DD Threshold Hysteresis V DDH - 0. - - - V Rising Threshold V R 5.5..8 5.0 7. V Threshold Hysteresis V H - 0. - - - V BOOT STRAP DIODE Low Current Forward Voltage V DL I VDD- = 00µA - 0.5 0. - 0.7 V High Current Forward Voltage V DH I VDD- = 00mA - 0.7 0.9 - V Dynamic Resistance R D I VDD- = 00mA - 0.7 -.5 Ω GATE DRIVER Low Level Output Voltage V OLL I = 00mA - 0. 0.8-0.25 V High Level Output Voltage V OHL I = -00mA, V OHL = V DD - V - 0. 0.23-0.3 V Peak Pull-Up Current I OHL V = 0V - 3 - - - A Peak Pull-Down Current I OLL V = 2V - - - - A GATE DRIVER Low Level Output Voltage V OLH I = 00mA - 0. 0.8-0.25 V High Level Output Voltage V OHH I = -00mA, V OHH = V - V - 0. 0.23-0.3 V Peak Pull-Up Current I OHH V = 0V - 3 - - - A Peak Pull-Down Current I OLH V = 2V - - - - A Switching Specifications V DD = V = 2V, V SS = V = 0V, No Load on or, unless otherwise specified. T J = +25 C T J = -0 C to +25 C PARAMETERS SYMBOL TEST CONDITIONS MIN TYP MAX MIN (Note 9) MAX (Note 9) UNITS Lower Turn-Off Propagation Delay ( Falling to Falling) t LPHL - 32 50-0 ns Upper Turn-Off Propagation Delay ( Falling to Falling) t HPHL - 32 50-0 ns Lower Turn-On Propagation Delay ( Rising to Rising) t LPLH - 39 50-0 ns Upper Turn-On Propagation Delay ( Rising to Rising) t HPLH - 38 50-0 ns Delay Matching: Upper Turn-Off to Lower Turn-On t MON 8 - - ns Delay Matching: Lower Turn-Off to Upper Turn-On t MOFF - - ns Either Output Rise Time (0% to 90%) t RC C L = nf - 9 - - - ns Either Output Fall Time (90% to 0%) t FC C L = nf - 7.5 - - - ns Either Output Rise Time (3V to 9V) t R C L = 0.µF - 0.3 0. - 0.5 µs Either Output Fall Time (9V to 3V) t F C L = 0.µF - 0.9 0.3-0. µs Minimum Input Pulse Width that Changes the Output t PW - - - - 50 ns Bootstrap Diode Turn-On or Turn-Off Time t BS - 0 - - - ns 5 FN295.
Pin Descriptions SYMBOL DESCRIPTION V DD Positive supply to lower gate driver. Bypass this pin to V SS. V SS EPAD High-side bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin. Bootstrap diode is on-chip. High-side output. Connect to gate of high-side power MOSFET. High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. High-side input. Low-side input. Chip negative supply, which will generally be ground. Low-side output. Connect to gate of low-side power MOSFET. No Connect. Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins. Timing Diagrams, t HPLH, t LPLH t HPHL, t LPHL, t MON t MOFF FIGURE 3. PROPAGATION DELAYS FIGURE. DELAY MATCNG Typical Performance Curves 0.0 0.0 I DDO (ma).0 T = +25 C T = -0 C T = +25 C T = +50 C T = +25 C T = +50 C 0. 0k 00k. 0 3 0. k 0k 00k. 0 3 k FREQUEY (Hz) FIGURE 5. ISL20 I DD OPERATING CURRENT vs FREQUEY I DDO (ma).0 T = +25 C T = -0 C FREQUEY (Hz) FIGURE. ISL2 I DD OPERATING CURRENT vs FREQUEY FN295.
Typical Performance Curves (Continued) 0.0 T = +50 C 0.0 T = -0 C T = +50 C I O (ma).0 0. T = +25 C T = +25 C I SO (ma).0 0. T = +25 C T = -0 C 0.0 0k 00k. 0 3 k FREQUEY (Hz) FIGURE 7. I OPERATING CURRENT vs FREQUEY T = +25 C 0.0 0k 00k. 0 3 k FREQUEY (Hz) FIGURE 8. I S OPERATING CURRENT vs FREQUEY 300 200 V OHL, V OHH (mv) 250 200 50 00 V DD = V = V V DD = V = 2V 50-50 0 50 00 50 V DD = V = 8V V OLL, V OLH (mv) V DD = V = V 50 00 V DD = V = 8V V DD = V = 2V 50-50 0 50 00 50 FIGURE 9. GH LEVEL OUTPUT VOLTAGE vs TEMPERATURE FIGURE 0. W LEVEL OUTPUT VOLTAGE vs TEMPERATURE.7 0.70 V DDR, V R (V).5.3. 5.9 5.7 V R V DDR V DDH, V H (V) 0.5 0.0 0.55 0.50 V H 5.5 0.5 V DDH 5.3-50 0 50 00 50 FIGURE. UNDERVOLTAGE CKOUT THRESLD vs TEMPERATURE 0.0-50 0 50 00 50 FIGURE 2. UNDERVOLTAGE CKOUT HYSTERESIS vs TEMPERATURE 7 FN295.
Typical Performance Curves (Continued) 55 55 t LPLH, t LPHL, t HPLH, t HPHL (ns) 50 5 0 35 30 t HPLH t LPLH t HPHL t LPHL t LPLH, t LPHL, t HPLH, t HPHL (ns) 50 5 0 35 30 t HPLH t LPLH t HPHL t LPHL 25-50 0 50 00 50 25-50 0 50 00 50 FIGURE 3. ISL20 PROPAGATION DELAYS vs TEMPERATURE FIGURE. ISL2 PROPAGATION DELAYS vs TEMPERATURE t MON, t MOFF (ns) 8.0 7.5 7.0 t MON.5.0 t MOFF 5.5 5.0.5.0-50 0 50 00 50 t MON, t MOFF (ns) 0.0 9.5 9.0 8.5 t MON 8.0 7.5 7.0.5 t MOFF.0 5.5 5.0.5.0-50 0 50 00 50 FIGURE 5. ISL20 DELAY MATCNG vs TEMPERATURE FIGURE. ISL2 DELAY MATCNG vs TEMPERATURE I OHL, I OHH (A) 3.5 3.0 2.5 2.0.5.0 0.5 0 0 2 8 0 2 0 0 2 8 0 2 V, V (V) V, V (V) I OHL, I OHH (A).5.0 3.5 3.0 2.5 2.0.5.0 0.5 FIGURE 7. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE FIGURE 8. PEAK PULL-DOWN CURRENT vs OUTPUT VOLTAGE 8 FN295.
Typical Performance Curves (Continued) I DD, I (µa) 20 0 00 90 80 70 0 50 0 30 20 0 0 I DD I 0 5 0 5 20 V DD, V (V) I DD, I (µa) 320 300 280 20 20 220 200 80 0 0 20 00 80 0 0 20 0 I DD I 0 5 0 5 20 V DD, V (V) FIGURE 9. ISL20 QUIESCENT CURRENT vs VOLTAGE FIGURE 20. ISL2 QUIESCENT CURRENT vs VOLTAGE.00 20 FORWARD CURRENT (A) 0.0 0.0. 0-3. 0 -. 0-5 V TO V SS VOLTAGE (V) 00 80 0 0 20. 0-0 0.3 0. 0.5 0. 0.7 0.8 2 3 5 FORWARD VOLTAGE (V) V DD TO V SS VOLTAGE (V) FIGURE 2. BOOTSTRAP DIODE I-V CHARACTERISTICS FIGURE 22. V VOLTAGE vs V DD VOLTAGE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN295.
Package Outline Drawing L0.x 0 LEAD TN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev, /08 A.00 PIN # INDEX AREA 3.2 REF 8X 0.80 BSC B 5 0X 0. 0 PIN INDEX AREA.00 2.0 0.5 (X) 0 3.00 0.0 M C A B 0.05 M C 0 X 0.30 BOTTOM VIEW ( 3.00 ) ( 0 X 0.0 ) 0.75 SEE DETAIL "X" 0.0 C BASE PLANE C ( 3.80) ( 2.0) SIDE VIEW SEATING PLANE 0.08 C C 0. 2 REF ( 8X 0. 8 ) TYPICAL RECOMMENDED LAND PATTERN ( 0X 0. 30 ) DETAIL "X" 0. 00 MIN. 0. 05 MAX. NOTES:. 2. 3.. 5.. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y.5m-99. Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension b applies to the metallized terminal and is measured between 0.5mm and 0.30mm from the terminal tip. Tiebar shown (if present) is a non-functional feature. The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # identifier may be either a mold or mark feature. 0 FN295.
Package Outline Drawing L2.xA 2 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev, 3/ A.00 PIN # INDEX AREA 3.2 REF 0X 0.50 BSC B 2X 0. 5 PIN INDEX AREA.00.58 0.5 (X) 2 2.80 7 0.0 M C A B 0.05 M C 2 X 0.25 BOTTOM VIEW ( 2.80 ) ( 2 X 0.5 ).00 MAX SEE DETAIL "X" 0.0 C BASE PLANE C ( 3.80) (.58) SIDE VIEW SEATING PLANE 0.08 C C 0. 2 REF ( 0X 0. 5 ) TYPICAL RECOMMENDED LAND PATTERN ( 2X 0. 25) DETAIL "X" 0. 00 MIN. 0. 05 MAX. NOTES:. 2. 3.. 5.. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y.5m-99. Unless otherwise specified, tolerance : Decimal ± 0.05 Lead width applies to the metallized terminal and is measured between 0.5mm and 0.30mm from the terminal tip. Tiebar shown (if present) is a non-functional feature. The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # identifier may be either a mold or mark feature. FN295.
Package Outline Drawing M8.5 8 LEAD NARROW BODY SMALL OUTNE PLASTIC PACKAGE Rev 3, 3/ ISL20, ISL2 DETAIL "A".27 (0.050) 0.0 (0.0) INDEX AREA.00 (0.57) 3.80 (0.50).20 (0.2) 5.80 (0.228) 0.50 (0.20) 0.25 (0.0) x 5 2 3 8 0 0.25 (0.00) 0.9 (0.008) SIDE VIEW B 2.20 (0.087) SEATING PLANE 8 5.00 (0.97).80 (0.89).75 (0.09).35 (0.053) 2 7 0.0 (0.023).27 (0.050) 3 -C-.27 (0.050) 0.5(0.020) 0.33(0.03) 0.25(0.00) 0.0(0.00) 5 5.20(0.205) SIDE VIEW A TYPICAL RECOMMENDED LAND PATTERN NOTES:. Dimensioning and tolerancing per ANSI Y.5M-982. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.5mm (0.00 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.00 inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only.. The lead width as measured 0.3mm (0.0 inch) or greater above the seating plane, shall not exceed a maximum value of 0.mm (0.02 inch). 7. Controlling dimension: MILMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-02-AA ISSUE C. 2 FN295.
Package Outline Drawing L8.x 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 0, /09 A.00 PIN # INDEX AREA 2. REF X 0.80 BSC B 8X 0. 0 ± 0.0 PIN INDEX AREA.00 2.50 ± 0.0 0.5 (X) 8 3.5 ± 0.0 5 0.0 M C A B 0.05 M C 8 X 0.30 BOTTOM VIEW ( 3.5 ) SEE DETAIL "X" ( 8 X 0.0 ) 0.9 ± 0.0 0.0 C BASE PLANE C ( 3.80) ( 2.50) SIDE VIEW SEATING PLANE 0.08 C C 0. 2 REF ( X 0. 8 ) TYPICAL RECOMMENDED LAND PATTERN ( 8X 0. 30 ) 0. 00 MIN. 0. 05 MAX. DETAIL "X" NOTES:. 2. 3.. 5.. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y.5m-99. Unless otherwise specified, tolerance : Decimal ± 0.05 Dimension applies to the metallized terminal and is measured between 0.5mm and 0.30mm from the terminal tip. Tiebar shown (if present) is a non-functional feature. The configuration of the pin # identifier is optional, but must be located within the zone indicated. The pin # identifier may be either a mold or mark feature. 3 FN295.