Chapter 3 Digital asics We conclude our review of basic concepts with a survey of topics from digital electronics. We confine our attention to aspects that are important in the understanding of simple devices, and in particular the analog to digital converter. s often as is practical we illustrate the concept with a LabVIEW demonstration. ackground We have seen in Chapter 2 how a gate can be made from a manual switch, a transistor, and an operational amplifier (opamp). gate can exist in one of only two states: ON or OFF, CLOSED or OPEN. transistor can be conducting a current or not. n opamp s output can be HIGH or LOW. We can think of these states of switches, transistors or opamps as representing a TRUE logic state or a FLSE logic state. The functionality of these devices, existing in only two possible states, is most naturally described by the binary number system. We begin therefore with background mathematics and basic definitions. Number System number system is defined as a set of unique number elements. For example, the decimal system, the one most familiar to us (with our ten fingers and toes) has ten elements: the digits through 9. ny number in the decimal system is constructed with digits from this set. The size of the set is called the base. Thus a number N in the decimal system is said to be to the base and is commonly written N when the base needs to be explicitly indicated. In any system the integers making up any number have a weight depending on their position in the number. The number abcd n in the base n system may be written as the series: abcd n = a( n 3 ) + b( n 2 ) + c( n ) + d( n ). [3-] inary System The binary number system is comprised of the elements and. number in this system is to the base 2 and is denoted N 2. If a is taken to stand for the one state of a digital device and a for the other, then the mathematics of digital circuitry involves just s and s, or binary arithmetic. binary number is written as a string of s and s arranged from left to right with the digits laid out in order of decreasing significance. Each digit is called a bit. n example is shown in Figure 3-, the 8-bit number 2. Each bit is shown within a box. Shown below each box is the decimal value of each bit, and shown above each box is the decimal value expressed as a power of 2. In accordance with eq[3-] the decimal equivalent is seen to be 23. The digit a has the weight n 3, the digit b the weight n 2, and so on. For example, = ()+ () + () + () Though in principle a system may have any number of elements, the systems in most use in modern digital electronics have two, eight or sixteen elements, called the binary, octal and hexadecimal systems. We consider some aspects of each. ON/OFF 2 n : 2 7 2 6 2 5 2 4 2 3 2 2 2 2 DEC: 28 64 32 6 8 4 2 The decimal equivalent is: x28 + x64 + x32 + x6 + x8 + x4 + x2 + x = 23. Figure 3-. The eight-bit binary number. 3-
Digital asics number may require more than 8-bits or less than 8- bits to be completely specified. Some of the instruments of data acquisition you will use in this course produce floating point measurements of 8-bits, some of -bits, and a few of 2-bits. In comparison, stateof-the-art audio CDs have a resolution of 2 bits and current microcomputers handle data of 32 bits (with 64-bit models just around the corner). Figure 3-2 shows what a binary number can look like in terms of voltages on an RS-232 interface line. Example Problem 3- inary-to-decimal Conversion Using the Method of Positional Values Convert the 5-bit number 2 to N using the method of positional values. Solution: The method of positional values implements eq[3-]: 2 = (2 4 ) + (2 3 ) + (2 2 ) + (2 ) + (2 ) = (6) + (8) + (4) + (2) + () = 6 + 4 + 2 = 22. Thus 2 = 22. If you wish you can experiment with the LabVIEW demo intodec.vi for the same purpose. Running a LabVIEW Demo To run a LabVIEW demo on a Macintosh in the physics lab do the following: Figure 3-2. The pulse train for the SCII character m, 9, as sent over an RS-232 interface. Octal System The octal number system is comprised of the eight elements: the digits through 7. This system was much used in the days of mainframe computers but is little used today. We mention it here only for completeness. Navigate from the desktop through Physics >> PSCS >> LabVIEW Demos >> Chapter 3 and load intodec.vi. LabVIEW should run. ➁ When LabVIEW has finished booting it will present you with intodec.vi s front panel (Figure 3-3a). To run the demo click the Run button. The demo will continue running until you click the STOP button. Hexadecimal System In terms of usage the hexadecimal system is next in importance to the binary system. The system is comprised of sixteen elements: the digits through 9 and the letters through F.,, etc. stand for,, etc. For compactness, data and computer memory locations are commonly wrtten in hexadecimal notation. In the following example problems and LabVIEW demos we demonstrate a few methods of converting from one number system to another. Figure 3-3a.The Panel of intodec.vi. 3-2
➂ Manipulate the vertical slide switches as you wish by clicking with the mouse in the up or down spaces. You will see the demo update the decimal value dynamically. When you wish to stop the demo, click the Stop button. ➃ With the demo stopped, but with LabVIEW still running, you might wish to examine the code of the VI. The code is contained in the Diagram window. First ensure the demo is stopped. Then select Window >> Display Diagram. The Diagram window will open (Figure 3-3b). You should be able to identify the functions Multiply and dd in the G code. Digital asics The so-called remainder method of converting from decimal to binary is illustrated in Example Problem 3-2. The demo Dectoin.vi illustrating the LabVIEW equivalent is shown in Figures 3-4a and b. Example Problem 3-2 Decimal-to-inary Conversion y the Remainder Method Convert 39 to N 2 by the remainder method. Solution: The remainder method of converting a decimal number to binary consists of continuously dividing the number by 2 and recording the remainder. The remainders then form the binary digits. For example, 39 2 9 2 9 2 4 2 2 2 2 = 9 and remainder of = 9 and remainder of = 4 and remainder of = 2 and remainder of = and remainder of = and remainder of Therefore, 39 = 2. Figure 3-3b. The Diagram of intodec.vi. This G code implements the method of positional values of Example Problem 3-. The border structure is a While loop which continues to execute until the stop button is pressed. Can you recognize the method of positional values in the code? 5 t this stage, even though you may have stopped the VI, LabVIEW itself is still running. To quit LabVIEW correctly select File >> Quit. Don t just click in the window close box. Figure 3-4a. The Panel of Dectoin.vi. The VI is shown in its running state. Compare the switch settings with Figure 3-. 3-3
Digital asics Figure 3-6a. The LabVIEW demo HextoDec.vi. Figure 3-4b. The Diagram of Dectoin.vi. This VI does not employ the remainder method. The decimal number is converted into a boolean array whose elements are then indexed and displayed. It is sometimes necessary to convert from decimal to hexadecimal and back again, especially when using legacy data acquisition devices. Demonstrations of decimal to hex conversion and vice versa are given in the LabVIEW demos DectoHex.vi and HextoDec.vi (Figures 3-5 and 3-6). Figure 3-6b. The Diagram of HextoDec.vi. The next two example problems involve octal conversions. They are given here only for your information. To the knowledge of the auther, the octal system is not used in instrument remote control. In this course you will likely not have to perform octal conversions. Example Problem 3-3 Octal-to-Decimal Conversion Using the Method of Positional Values Convert 247 8 to N. Solution: Figure 3-5a. The LabVIEW demo DectoHex.vi. 247 8 = 2(8 3 ) + 4(8 2 ) + (8 ) + 7(8 ) = 2(52) + 4(64) + (8) + 7() = 24 + 256 + 8 + 7 = 295. Therefore 247 8 = 295. Figure 3-5b. The Diagram of DectoHex.vi. 3-4
Digital asics Example Problem 3-4 Decimal-to-Octal Conversion Using the Remainder Method Convert 483 to N 8. Solution: 483/8 = 6 and remainder of 3 6/8 = 7 and remainder of 4 7/8 = and remainder of 7 Therefore 483 = 743 8. Figure 3-7b. The LabVIEW demo SevenSegDisp.vi simulating the working of a CD coded display. CD System CD stands for binary-coded decimal. The CD system is a kind of pseudo number system in that each number in this system consists of four bits, the binary equivalent of a decimal digit. It is sometimes desireable to convert a decimal number to binary by converting each digit of the decimal number into its four-bit nibble equivalent. Thus instead of converting 96 to its pure binary equivalent of 2, it is converted more easily digit-by-digit, that is, first 9 and then 6 to get. This form of notation is called binary-coded decimal (CD). CD coding is used in LED and LCD seven-segment display devices on multimeters and other instruments (including many of those described in ppendix ). n example of the circuit is drawn in Figure 3-7a. LabVIEW demo of this device is shown in Figure 3-7b. CD display works in this way. Each decimal digit which is already CD encoded is passed to a decoder. The decoder decodes the four bits by closing the circuits on certain output lines. These closures result in current being passed through certain light emitting diodes (LEDs) in the display. (We have discussed the functioning of light emitting diodes in Chapter 2.) Thus for example if the CD input were corresponding to decimal 8, all the lines a through g (Figure 3-7a) would be closed, resulting in all seven LEDs being lit and the digit 8 being displayed. oolean lgebra ll number systems, simple or complex, support an algebra. The algebra of the binary number system is called oolean algebra, named after oole, the 9 th century French mathematician who invented it. In oolean algebra the letters,, C etc stand for logical variables which take on the values (called in positive logic FLSE) or (in positive logic TRUE). Three basic operations are supported:. ddition + read OR, [3-2a] 2. Multiplication read ND, [3-2b] (also written just for convenience), and Figure 3-7a. CD decoder used in the display of an instrument like a digital multimeter. Each digit is displayed by a circuit such as this one. 3. Inversion read NOT or complement of. [3-2c] The symbols for the operators should not be confused with the word-description of the operations. For example, the symbol for addition, +, represents the 3-5
Digital asics operation OR (not ND); the symbol for multiplication stands for the operation ND. For example: The statement = + means the output is TRUE (or ) if or is TRUE (or ). The statement Y = means the output Y is TRUE (or ) if both and are TRUE (s). The statement Z = means if is TRUE (or ) then Z is FLSE (), and vice versa. The basic operations of oolean algebra are implemented with electronic devices called gates. We therefore continue in the next section with this subject. Survey of Gates Most gates in logic circuits today are integrated circuits (ICs). Gates are sold in various family types to perform various logical functions. For each gate type, there exist simple relationships between the inputs and the output that can be summarized in a special kind of table called a truth table. The truth table lists these relationships for all possible combinations of input. TTL Gates There are various families of gates designed to be used at various voltage levels. We concentrate here on the most widely-used family, the TTL (Transistor- Transistor Logic) family. In this family the voltages corresponding to the logic states are as follows: logical (LOW) < V <.8 volts logical (HIGH) 2.4 < V < 5. volts. This is known as positive logic. For a gate to operate as intended these voltages must be obeyed. ny voltage between and.8 volts corresponds to a logic, any voltage between 2.4 and 5. volts corresponds to a logic. Thus the TTL family is fairly forgiving in terms of voltage. However, a voltage between.8 volts and 2.4 volts represents an undefined state and therefore an undefined logic. n undefined state should be avoided since a gate that is operated in this voltage range will produce an unpredictable output. There are seven fundamental TTL logic gates: the ND, OR, NOT, NND, NOR, exclusive-or (OR), and exclusive-nor (NOR) gates. We consider each one in turn. ND Gate The ND gate (Figure 3-8a) has two or more inputs (,, etc.) and performs the operation. Its output is only if all inputs are ; otherwise its output is. The truth table is shown in the figure. The table should be read row by row. For example, the second row shows that when is and is, is, and so on. = Figure 3-8a. Circuit symbol, algebraic representation, and truth table for a two-input ND gate. The Panel of the LabVIEW demo ND gate.vi is shown in Figure 3-8b. See if you can reproduce the truth table by manipulating the buttons. In principle, an ND gate can have any number of inputs; Figure 3-9 shows the Panel of a 3-input ND gate demo. Figure 3-8b. The LabVIEW demo ND gate.vi. 3-6
Digital asics NOT Gate The NOT gate (Figure 3-) performs inversion. (The insertion of an open circle in a line of a logical circuit conventionally denotes inversion.) The single output is the complement of the single input; i.e., the output is if the input is, and the output is if the input is. Figure 3-9. The LabVIEW demo 3ND gate.vi. OR Gate The OR gate (Figure 3-) performs the operation +. Its output is when any input is, and only if all inputs are. The Panel of the LabVIEW demo Or gate.vi is shown in Figure 3-b. = + Figure 3-a. Circuit symbol, algebraic representation, and truth table for a two-input OR gate. = Figure 3-. Circuit symbol, algebraic representation, and truth table for a NOT gate (inverter). NND Gate The NND gate (Figure 3-2) performs two operations one after the other: an ND followed by a NOT. The symbol consists of a normal ND gate symbol with an open circle at the output. The Panel of the LabVIEW demo is shown in Figure 3-2b. = Figure 3-2a. two-input NND gate consists of a twoinput ND gate plus inversion. Figure 3-b. The LabVIEW demo OR gate.vi. Figure 3-2b. The LabVIEW demo NND gate.vi. 3-7
Digital asics NOR Gate The NOR gate (Figure 3-3) performs an OR followed by a NOT. The Panel of the LabVIEW demo NOR gate.vi is shown in Figure 3-3b. = + Figure 3-3a. two-input NOR gate. Figure 3-4b. The LabVIEW demo OR gate.vi. Exclusive-NOR or Equality Gate The exclusive-nor ( NOR) gate (Figure 3-5a) performs the operation followed by a NOT. The output is when the inputs are equal and otherwise. The gate is therefore also called an equality gate. The Panel of the LabVIEW demo NOR gate.vi is shown in Figure 3-5b. Figure 3-3b. The LabVIEW demo NOR gate.vi. The next two gates, though available as single ICs and represented by single circuit symbols, are derivative in the sense that they consist of combinations of ND, OR, and NOT. = Figure 3-5a. n exclusive-nor or equality gate. Exclusive-OR Gate The exclusive-or (OR) gate (Figure 3-4) performs an operation denoted by the symbol. The gate has two inputs and an output which is when the inputs are different ( and, or and ), and an output when the inputs are alike ( and, or and ). 3-8 = Figure 3-4a. Circuit symbol, algebraic representation, and truth table for an exclusive-or gate. Figure 3-5b. The LabVIEW demo NOR gate.vi. We stated earlier that logic gates used today are nearly always in IC form. ut a logic gate in IC form does have an equivalent circuit that can be represented by
transistors. It is instructive to decipher the transistor equivalent of simple gates. Here is one example. Example Problem 3-5 Gate Identification With reference to the operation of the transistors explain that the following circuit functions as an OR gate. Confirm this result by means of a truth table. (The values of the resistors are not important to your answer.) kω kω + 6V Digital asics Gate Synthesis In digital electronics the NND gate is considered to be the basic building block from which all other gate operations can be constructed. Today, the gates we have described in the previous section are readily available as ICs, and from a number of manufacturers. In principle, there is no need to derive a gate operation from other gates. In practice, however, it is often expedient to synthesize gate operations, especially when constrained to do so by your circuit design. For example, when using a chip that contains many gates, you may wind up with extra unused gates, and may wish to use them up by synthesizing an operation rather than using a dedicated, single gate. We shall see in this section that the NOT gate can be formed from a NND gate with inputs joined; an ND gate can be formed from a NND gate followed by a NOT. Other gates can be derived following the rules of oolean algebra. 4.7 kω Solution: If the voltages applied to both and are HIGH () then both transistors are saturated, the current flow through them is at a maximum and the voltage drop across the 4.7 kω resistor is in a HIGH () state. Thus two input HIGHs give an output HIGH and we have the first row in the truth table below. If the voltages applied to both and are LOW () then both transistors are cut off, neither transistor conducts and the voltage across the 4.7 kω resistor is in a LOW () state. If any one of or is HIGH (), then the output is also HIGH () by similar arguments. The truth table is as follows. Z This truth tables describes the functioning of an OR gate. Z De Morgan s Theorems De Morgan s theorems are important in implementing gate combinations; they allow one to switch between ND (or NND) and OR (or NOR) gate implementations. De Morgan s theorems may be written:. + + C...= C... [3-5a] 2. C... = + + C... [3-5b] These theorems are useful in gate synthesis as we shall show in the next section. OR Gate Synthesized from NND Gates If the NND gate is taken as the natural building block then an OR gate may be synthesized from 3 NND gates by connecting them together as shown in Figure 3-6. The segmented truth table for this circuit is given in Table 3-. You can see that the last column of this table is identical to the truth table for +. You can prove this with the help of de Morgan s theorem (Figure 3-6). This is only one example of gate synthesis. 3-9
Digital asics = + = + Figure 3-6. This circuit illustrates how to synthesize an OR gate from three NND gates with the help of de Morgan s theorem. Table 3-. Segmented truth table for the synthesized OR gate of Figure 3-6. The Half dder We can now investigate the mechanization of binary addition. For this purpose we consider only 2-bit numbers using the following notation: and Y Y, where the subscript refers to the order of the bit. Of course,, etc. can take only the values or. Starting with the th bit, we can write + Y = C Z, [3-6] where C is the carry from the addition of the two th order bits over into the st order bit position. The addition of the two 2-bit numbers can therefore be represented in this way: inary rithmetic Like any arithmetic, binary arithmetic must include the standard operations of addition, subtraction, multiplication, and division. Here we look briefly at binary addition. The physical process of addition, say how it is done with pencil and paper, can be summarize with a truth table and then mechanize with logic gates. inary ddition s we have seen, the binary system includes only two elements. ddition is therefore simple. Some examples are shown in Figure 3-7. Numbers in binary can be added in columns much like numbers in decimal. Note that plus yields a sum of and a carry of into the next column to the left, producing an answer of 2. Similarly, plus plus yields a sum of and a carry of into the next column to the left. inary numbers, like decimal numbers, can be added column by column working from right to left. + + + + Figure 3-7. Some examples of binary addition. Carry bits C 2 C 2-bit number 2-bit number Y Y Z 2 Z Z The result Z 2 Z Z is, in general, a 3-bit number. The truth table for the operation given in eq[3-6] is given in Table 3-2. This operation is called half addition because no provision exists for dealing with an initial carry (or carry in). Table 3-2. Truth table for a half-addition. Y C Z This table is represented by the following oolean statements: C = Y, [3-7a] and Z = Y. [3-7b] The second of these equations describes the Sum operation, the first describes the Carry. These equations can be mechanized, that is, they can be represented by real, physical gates. With a little reflection you can see that the Carry operation is given by an ND gate and the Sum is given by an exclusive-or gate (Figure 3-8). The combination of these gates (within the 3-
dashed rectangle) is called a half adder. The LabVIEW demo Halfdder.vi that illustrates this is shown in Figures 3-8b and c. Sum S = Carry C = Figure 3-8a. Mechanization of a half-adder using an ND gate and an exclusive-or gate. Digital asics The Full dder The process of full addition must allow for an initial, or carry-in bit and a final, or carry-out bit. Generalizing Table 3-2 with a carry-in bit (C ) gives the truth table shown in Table 3-3. C 2 is the carry-out bit. There are two results of a full addition: the result Z and the carry bit C 2. Let us consider them separately as we did for the half adder. From Table 3-3 you can see that C 2 = Y + C Y + C. [3-8] This expression can be mechanized using three ND gates and a three-input OR gate (Figure 3-9). Table 3-3. Truth Table for a Full dder. C Y C 2 Z Figure 3-8b. The panel of the LabVIEW demo Halfdder.vi. You should be able to show also from Table 3-3 that Z = C ( Y ). [3-9] Figure 3-8c. The diagram of the LabVIEW demo Half- dder.vi. Note how the G code resembles the circuit diagram of Figure 3-8a. The half adder can only add two -bit numbers. It cannot be used to add two 2-bit numbers because in general the result is a 3-bit number. The sum of the 2 column involves three bits: one bit from each of the two numbers being added and a carry-in bit from the units column. Thus a full adder for two 2-bit numbers must be able to process three input variables. The full adder we consider next. Mechanizing this expression in conjunction with the majority detector of Figure 3-9 drawn as a black box gives the full adder circuit shown in Figure 3-2. full adder is commonly represented as a rectangle with three inputs and two outputs. The LabVIEW demo Fulldder.vi is shown in Figures 3-2b and c. This is the simplest kind of binary adder. It is also the slowest as each column of the sum must wait on the resulting carry bit from its adjoining lower-order column. This is known as serial carry propagation. Modern packages are described as 4-bit sum plus carry. These 4-bit sum plus carrys may be serially propagated to create an 8-bit sum plus carry, the smallest truly useable circuit in 8-bit devices. 3-
Digital asics C C Y C Y C 2 Figure 3-2b. The LabVIEW demo Full adder.vi. Y C 2 = Y + C Y + C Figure 3-9. Mechanization of the carry bit from a full addition. This is called a majority detector. Y C Y Majority detector Z Sum Figure 3-2a. Mechanization of a full adder. C 2 Carry Figure 3-2c. Diagram of the LabVIEW demo Full adder.vi. This concludes our survey of a few of the basics of digital electronics. We spend the rest of our time in this chapter on the subject of analogue-to-digital conversion. 3-2
nalog to Digital Conversion t the heart of a digital instrument is an analog-to-digital converter (DC). There are three common types or techniques of analog converter: parallel (also called flash conversion), successive approximation and dual slope integration. Digital asics Terminology Each type of DC has its own conversion time, absolute accuracy and resolution. Resolution is the number of bits to which the analog signal is converted. bsolute accuracy is expressed in bits. The absolute accuracy, in bits, times the voltage value represented by the least significant bit gives the absolute accuracy in volts. Conversion time is the time it takes the converter to take an analog signal and convert it to its binary equivalent. Parallel Conversion parallel (flash or simultaneous) converter employs a series of comparator circuits as is shown in Figure 3-2. (For a description of a comparator see the discussion of the opamp in Chapter 2.) This particular example is a 3-bit parallel DC that uses seven comparators. Parallel converters require 2 n comparators where n is the resolution in bits. Thus a 2-bit parallel converter would require 4,95 comparators! The chain of resistors in the figure provides a reference or trip point voltage for each comparator. The trip point of each successive comparator is equally spaced in voltage, say V. Each value of V represents one bit. The voltage to be converted Vin is applied simultaneously to the other input of each comparator. Comparator trips at the lowest input voltage, comparator G at the highest. To give the simplest example, if Vref = 7. V then V = V; the trip point for comparator is.5 V, is.5 V, C is 2.5 V, D is 3.5 V, E is 4.5 V, F is 5.5 V and G is 6.5 V. Thus if Vin were 4.9 V, comparators through E would trip, while F and G would remain unchanged. The decoder circuitry would convert the (high to low) on its input lines to the 3-bit value, representing a voltage in the range of 4.5 to 5.49 V (the decoding is summar-ized in Table 3-4). Thus the parallel or flash nature of the DC should be apparent. This is the fastest of the three DC types and is widely used in the audio industry. Though a 3- bit DC as considered here is of little use, 2-bit converters are now widely available, with conversion frequencies in the MHz range. /2 R R R R R R R /2 R Vref Vin Range (Volts) Vin 6.5 5.5 4.5 3.5 2.5.5.5 G F E D C Decoder Circuitry Figure 3-2. parallel or flash 3-bit DC. Table 3-4. Data for the 3-bit flash converter. Comparator C D E F G MS NMS LS Encoded inary MS LS -.49.5-.49.5-2.49 2.5-3.49 3.5-4.49 4.5-5.49 5.5-6.49 > 6.5 3-3
Digital asics Successive pproximation The successive approximation converter is one of the least expensive and therefore most popular DC types. Substantially faster than a ramp DC, it has a constant and known conversion time. This circuit (Figure 3-22) employs a digital-to-analogue converter (DC roughly the opposite of an DC) and a comparator to compare the voltage to be measured with the output of the DC. The input to the DC is provided by a successive approximation circuitry triggered by the output of the comparator. SR DC Digital Outputs 53 = 2. The SR algorithm states that the MS, having the value of 28, is to be tested first. ecause 28 is less than 53, the MS is to be kept. The best estimate after the first cycle is. On the next cycle, the next MS, having value 64, is added to the best estimate (that is, 28 + 64 = 92). ecause 92 is greater than 53, this bit is not kept, and the best estimate remains. In the following cycle, the next bit value of 32 yields a test value of 28 + 32 = 6. gain, the test value is greater than the input level, so this bit is not kept, and the best estimate remains at. In the following cycle, the next test value of 6 yields 28 + 6 = 44. This value is less than 53, so this bit is kept. fter 4 cycles, the best estimate is. The remaining cycles can be seen on the panel of SR.vi. nalogue Input Comparator Successive pproximation Circuitry Clock Figure 3-22. lock diagram of a successive-approximation DC. conversion can be described in terms of the following algorithm: Zero the DC and reset its digital input (the successive approximation register or SR). 2 Set the MS of the SR, thereby producing an output V DC. If V DC is greater than V in, then turn that bit off else if V DC is less than V in, leave the bit on. 3 Repeat step 2 for the next MS, until all n bits of the SR have been set and tested. 4 fter n cycles, the digital output of the SR will contain the digitized value of the input signal. The algorithm can be followed by studying the working of the LabVIEW demo SR.vi (Figure 3-23a). The graph on the panel shows the input waveform (dashed line) and the output of the SR over about 8 clock cycles. The input waveform is, by default, the constant value 53 (which can be changed). The number 53 is equal to 28 + 6 + 8 + so the binary equivalent is Figure 3-23a. The panel of SR.vi showing on the graph a typical DC output of successive-approximation DC converter as a function of clock cycle. To get the most out of the demo do the following: Load and run SR.vi in continuous mode. ➁ Use the Operate Value tool to change the input level, and observe the SR output waveform. Change the level over a wide range, greater and less than 28. Is the input level always digitized in the same 8 clock cycles? ➂ To stop a VI running in continuous mode click the 3-4
bort button. Digital asics is only 8 bits as in the case of the PCI-2 the effective conversion time is increased. Figure 3-23b. The Diagram of SR.vi. Though slower than the flash converter, successive approximation converters are relatively fast, in the range of µs. Typical conversion times at the time of writing are µs for a -bit DC and 2 µs for a 2-bit DC. We shall see in ppendix that this method is used in a number of data acquisition (DQ) cards produced by National Instruments, in particular the PCI-2 card installed in many of the computers in the physics lab. Integrating Type: Dual Slope Conversion The dual slope integrating DC works via the charge and discharge of a capacitor (Figure 3-24). The capacitor is charged from zero volts by a current proportional to the input voltage for a given time. Then the input voltage is disconnected and the capacitor is discharged back to zero volts by a constant current source whose value is known. Figure 3-24 shows the capacitor voltage as it goes through the charge/ discharge cycle. Since the discharge time is proportional to the value of the constant current and the voltage on the capacitor, a digital representation of the discharge time (in clock cycles) is the digital value of the input voltage. Voltage on Capacitor Example Problem 3-6 Conversion Time 2-bit PCI-2 DQ card with a successive approximation DC is installed in a computer whose clock frequency is 233 MHz. In principle, what should be the approximate conversion time? Comment on the result. Solution: ccording to the method of successive approximations, a 2-bit conversion takes 2 clock cycles. Thus in principle the conversion time should be cycles 2 conversion x 233x 6 = 5.5ns seconds cycle large input voltage small input voltage Current proportional to input voltage charges capacitor for a fixed number of clock cycles zero detect zero detect Time Figure 3-24. Charge and discharge cycle for integrating DC. This kind of DC is commonly found in inexpensive hand-held DMMs, such as the Radio Shack Manual/uto Range DMM (discussed in ppendix and Lab #). This number is an absolute minimum conversion time. The actual time will depend on factors such as the bus width. If the DC is 2 bits but the bus width 3-5
Digital asics Working Circuit working DC is shown in block form in Figure 3-25. It consists essentially of two functional blocks, a signal conditioner and the DC chip itself. The signal conditioner is a variable-gain amplifier that allows for calibration for a variety of sensors. The DC in this particular case is the DC84, an 8-bit converter. DC Input DC Offset Gain /D Converter 8 Digital IO Lines Pwr Write Data Figure 3-25. lock diagram of the DC84 analogue to digital converter. (IO) lines which can then be read by a computer. The DC84 accepts an analogue input of -5 volts DC and converts it to a binary number between and 256. With a maximum range of 5 volts and 256 steps between and 5, resolution is 5/256 =.95 volts, or almost 2 mv. So for any analogue input voltage between. and.95, the DC84 will produce a binary (); for any voltage between.95 and.39, a binary (), and so on. The signal conditioner is present to enable one to process analogue signals smaller than 5V. For example, without the signal conditioner a signal as small as 4mV maximum would only give rise to two binary values. Such a signal would therefore be amplified to a value close to the maximum range of the IC and therefore result in much finer increments. The output would then be scaled back to the appropriate value by the computer software that is used to monitor the IO lines. What Was Left Out The DC84 responds to a change in an C voltage very quickly, in fact at a rate greater than per second. The DC84 converts each sample to digital form and places the signal on 8 digital input/output This brings us to the end of our review of digital basics. 3-6
Practice Problems Digital asics. Convert the following numbers to decimal: 2, 2, 2. 2. Convert the following numbers to binary:, 225, 29. 3. Convert the following numbers to decimal: 7 8, 234 8, 55 8, 62 8, 777 8. = + ; Z = +. 2. Complete the following truth table for the expressions shown: C C ++C C +C 4. Convert the following numbers to octal: 27, 2626, 95, 26, 495. 5. Convert the following numbers to CD: 27, 2, 3576428. 6. Write a G program to perform octal-to-decimal conversion. 7. Write a G program to perform decimal-to-octal conversion. 8. pply oolean theorems to reduce the following expressions to simplest form: + + ; ; M M ; + ; C + D D; + + + ; + + ; (E + E); H + H + H + H;. 9. Remove common factors to simplify the following expressions: + + ; + CDD + D + ; ( + ) + C.. Prove these expressions by means of truth tables: (+) = ; +C = (+)(+C).. Draw a block diagram corresponding to each of the following equations. Label all terminals. ssume that the variables are available in noninverted form only, i.e., if an inverted form of the variable is required, a NOT circuit must be used. = ; Y = C + C; Z = + + C; 3. Perform the following binary additions: + + + 4. The three-input OR gate follows the oolean statement Q = + + C. (a) Make a truth table for this gate. (b) Write the oolean statement for Q and mechanize the result using 2-input NND gates and inverters. 5. n experimenter observes that the output of a TTL NND gate is V with both inputs open and does not change when they are both connected to +5 V. Is the gate malfunctioning? Why or why not? 6. It is required that Q be true only when the logic signal equals the logic signal. Make a truth table of this problem, mechanize the result directly assuming that only and signals are available (not or ), and then use de Morgan s theorem to reduce this to a three-gate mechaniza- 3-7
Digital asics tion from and inputs. 7. With detailed reference to the operation of the transistors (and by means of a truth table) confirm that the following circuit functions as a NOR gate. (The values of the resistors are not important to your answer. kω + 6V + 6V kω 4.7 kω Z Z 4.7 kω kω kω 9. With reference to problem 7 construct a NND gate. Justify the operation of your gate by means of description and a truth table. (The values of the resistors are not important to your answer. 8. With detailed reference to the operation of the transistors (and by means of a truth table) confirm that the following circuit functions as a ND gate. (The values of the resistors are not important to your answer. 2. Write a program in G to prove the synthesized circuit of Figure 3-2. EndNotes for Chapter 3 These demos were modified by the author from ones written by. Paton in Fundamentals of Digital Electronics (National Instruments, 998). I am especially indebted to Prof. Paton for SR.vi in his Lab #9 and its use in illustrating the successive approximation DC. 3-8