IRF84 Data Sheet January 22 8A, 5V,.85 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17425. Ordering Information PART NUMBER PACKAGE BRAND Features 8A, 5V r DS(ON) =.85Ω Single Pulse Avalanche Energy Rated SOA is Power Dissipation Limited Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Related Literature - TB334 Guidelines for Soldering Surface Mount Components to PC Boards Symbol D IRF84 TO-22AB IRF84 NOTE: When ordering, include the entire part number. G S Packaging JEDEC TO-22AB TOP VIEW SOURCE DRAIN GATE DRAIN (FLANGE) 22 Fairchild Semiconductor Corporation IRF84 Rev. B
IRF84 Absolute Maximum Ratings T C = 25 o C, Unless Otherwise Specified IRF84 UNITS Drain to Source Voltage (Note 1)....................................................... 5 V Drain to Gate Voltage (R GS = 2kΩ) (Note 1)........................................... V DGR 5 V Continuous Drain Current............................................................. I D 8. A T C = 1 o C...................................................................... I D 5.1 A Pulsed Drain Current (Note 3)......................................................... I DM 32 A Gate to Source Voltage..............................................................V GS ±2 V Maximum Power Dissipation...........................................................P D 125 W Linear Derating Factor.................................................................. 1. W/ o C Single Pulse Avalanche Energy Rating (Note 4)...........................................E AS 51 mj Operating and Storage Temperature............................................... T J, T STG -55 to 15 o C Maximum Temperature for Soldering Leads at.3in (1.mm) from Case for 1s............................................. T L 3 Package Body for 1s, See Techbrief 334............................................. T pkg 2 o C o C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. T J = 25 o C to 125 o C. Electrical Specifications T C = 25 o C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BS V GS = V, I D = 25µA (Figure 1) 5 - - V Gate to Threshold Voltage V GS(TH) V GS =, I D = 25µA 2. - 4. V Zero-Gate Voltage Drain Current I DSS = Rated BS, V GS = V - - 25 µa =.8 x Rated BS, V GS = V, T J = 125 o C - - 25 µa On-State Drain Current (Note 2) I D(ON) > I D(ON) x r DS(ON)MAX, V GS = 1V 8. - - A Gate to Source Leakage Current I GSS V GS = ±2V - - ±1 na Drain to Source On Resistance (Note 2) r DS(ON) V GS = 1V, I D = 4.4A (Figures 8, 9) -.8.85 Ω Forward Transconductance (Note 2) g fs 5V, I D = 4.4A (Figure 12) 4.9 7.4 - S Turn-On Delay Time t D(ON) V DD = 25V, I D 8A, R G = 9.1Ω, R L = 3Ω - 15 21 ns Rise Time t r MOSFET Switching Times are Essentially Independent of Operating Temperature. - 21 35 ns Turn-Off Delay Time t D(OFF) - 5 74 ns Fall Time t f - 2 3 ns Total Gate Charge (Gate to Source + Gate to Drain) Q g(tot) V GS = 1V, I D = 8A, =.8 x Rated BS I g(ref) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature - 42 3 nc Gate to Source Charge Q gs - 7. - nc Gate to Drain Miller Charge Q gd - 22 - nc Input Capacitance C ISS V GS = V, = 25V, f = 1.MHz (Figure 11) - 1225 - pf Output Capacitance C OSS - 2 - pf Reverse-Transfer Capacitance C RSS - 85 - pf Internal Drain Inductance L D Measured from the Contact Screw on Tab to Center of Die Measured from the Drain Lead, mm (.25in) from Package to Center of Die Internal Source Inductance L S Measured from the Source Lead, mm (.25in) from Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances - 3.5 - nh - 4.5 - nh - 7.5 - nh Thermal Resistance Junction to Case R θjc - - 1. o C/W Thermal Resistance Junction to Ambient R θja Free Air Operation - - 2.5 o C/W G D L D L S S IRF84 Rev. B
IRF84 Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Continuous Source to Drain Current I SD Modified MOSFET - - 8. A D Pulse Source to Drain Current (Note 3) I Symbol Showing the SDM - - 32 A Integral Reverse P-N Junction Diode G S Source to Drain Diode Voltage (Note 2) V SD T J = 25 o C, I SD = 8.A, V GS = 1A/µs (Figure 13) - - 2. V Reverse Recovery Time t rr T J = 25 o C, I SD = 8.A, di SD /dt = 1A/µs 21 475 97 ns Reverse Recovered Charge Q RR T J = 25 o C, I SD = 8.A, di SD /dt = 1A/µs 2. 4. 8.2 µc NOTES: 2. Pulse Test: Pulse width 3µs, duty cycle 2%. 3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. V DD = 5V, starting T J = 25 o C, L = 14mH, R G = 25Ω, peak I AS = 8A. Typical Performance Curves Unless Otherwise Specified 1.2 1 POWER DISSIPATION MULTIPLIER 1..8..4.2 8 4 2 5 1 15 T C, CASE TEMPERATURE ( o C) 25 5 75 1 125 15 T C, CASE TEMPERATURE ( o C) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 Z θjc, NORMALIZED TRANSIENT THERMAL IMPEDANCE.1.5.2.1.5.2 P DM.1 1-2 SINGLE PULSE t 1 t 2 t2 NOTES: DUTY FACTOR: D = t 1 /t 2 PEAK T J = P DM x Z θjc x R θjc + T C 1-3 1-5 1-4 1-3 1-2.1 1 1 t 1, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 22 Fairchild Semiconductor Corporation IRF84 Rev. B
IRF84 Typical Performance Curves Unless Otherwise Specified (Continued) 1 2 1 1 OPERATION IN THIS REGION IS LIMITED BY r DS(ON) T C = 25 o C T J = MAX RATED SINGLE PULSE.1 1 1 1 2, DRAIN TO SOURCE VOLTAGE (V) 1µs 1µs 1ms 1ms DC 1 3 15 12 9 3 V GS = 1V PULSE DURATION = 8µs DUTY CYCLE =.5% MAX V GS =.V V GS = 5.5V V GS = 5.V V V GS = 4.V GS = 4.5V 5 1 15 2 25, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS 15 12 9 3 PULSE DURATION = 8µs DUTY CYCLE =.5% MAX V GS = 4.V V GS = 1V V GS =.V V GS = 5.5V V GS = 5.V V GS = 4.5V 3 9 12 15, DRAIN TO SOURCE VOLTAGE (V) I SD (ON), DRAIN TO SOURCE CURRENT (A) 1 1 1.1 PULSE DURATION = 8µs DUTY CYCLE =.5% MAX 5V T J = 15 o C T J = 25 o C.1 2 4 8 1 V SD, GATE TO SOURCE VOLTAGE (V) FIGURE. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS r DS(ON), DRAIN TO SOURCE ON RESISTANCE (Ω) 1 8 4 2 PULSE DURATION = 8µs DUTY CYCLE =.5% MAX V GS = 1V V GS = 2V NORMALIZED DRAIN TO SOURCE ON RESISTANCE VOLTAGE 3. 2.4 1.8 1.2. PULSE DURATION = 8µs DUTY CYCLE =.5% MAX I D = 4.4A, V GS = 1V 8 1 24 32 4 T C, CASE TEMPERATURE ( o C) - -4-2 2 4 8 1 12 14 1 T J, JUNCTION TEMPERATURE ( o C) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRF84 Rev. B
IRF84 Typical Performance Curves Unless Otherwise Specified (Continued) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 1.15 1.5.95.85 I D = 25µA C, CAPACITANCE (pf) 3 24 18 12 C RSS C OSS C ISS V GS = V, f = 1MHz C ISS = C GS + C GD C RSS = C GD C OSS C DS + C GD.75 - -4-2 2 4 8 1 12 14 1 T J, JUNCTION TEMPERATURE ( o C) 1 2 5 1 2 5 1 2, DRAIN TO SOURCE VOLTAGE (V) FIGURE 1. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE g fs, TRANSCONDUCTANCE (S) 15 12 9 3 PULSE DURATION = 8µs DUTY CYCLE =.5% MAX 5V T J = 25 o C T J = 15 o C 3 9 12 15 I SD, SOURCE TO DRAIN CURRENT (A) 1 1 1. PULSE DURATION = 8µs DUTY CYCLE =.5% MAX T J = 15 o C T J = 25 o C.1.3..9 1.2 1.5 V SD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE V GS, GATE TO SOURCE VOLTAGE (V) 2 I D = 8A 1 = 1V 12 = 25V V 8 DS = 4V 4 12 24 3 48 Q g, GATE CHARGE (nc) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 22 Fairchild Semiconductor Corporation IRF84 Rev. B
IRF84 Test Circuits and Waveforms BS L t P VARY t P TO OBTAIN REQUIRED PEAK I AS V GS R G + V DD - I AS V DD DUT V t P I AS.1Ω t AV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 1. UNCLAMPED ENERGY WAVEFORMS t ON t d(on) t OFF t d(off) R L t r t f 9% 9% + R G V DD - 1% 1% DUT 9% V GS V GS 1% 5% PULSE WIDTH 5% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS CURRENT REGULATOR (ISOLATED SUPPLY) V DD 12V BATTERY.2µF 5kΩ.3µF SAME TYPE AS DUT Q gs Q gd Q g(tot) V GS D G DUT I g(ref) I G CURRENT SAMPLING RESISTOR S I D CURRENT SAMPLING RESISTOR I g(ref) FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 2. GATE CHARGE WAVEFORMS IRF84 Rev. B
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